F-2,Block, Amity CampusSec-125, Nodia (UP) India 201303 ASSIGNMENTS PROGRAM: SEMESTER-I Subject Name : Study COUNTRY : Permanent Enrollment Number (PEN) : Roll Number : Student Name : INSTRUCTIONS a) Students are required to submit all three assignment sets. ASSIGNMENT Assignment A Assignment B Assignment C DETAILS Five Subjective Questions Three Subjective Questions + Case Study 45 Objective Questions MARKS 10 10 10 b) c) d) e) Total weightage given to these assignments is 30%. OR 30 Marks All assignments are to be completed as typed in word/pdf. All questions are required to be attempted. All the three assignments are to be completed by due dates (specified from time to time) and need to be submitted for evaluation by Amity University. f) The evaluated assignment marks will be made available within six weeks. Thereafter, these will be destroyed at the end of each semester. g) The students have to attached a scan signature in the form. Signature Date : : _________________________________ _________________________________ ( √ ) Tick mark in front of the assignments submitted Assignment ‘A’ Assignment ‘B’ Assignment ‘C’ 3. 6. 24. What is Race problem in flip.5) Q2 a) Explain the working of master-slave JK flip flop.Digital Electronics ASSIGNMENT ‘A’ Q1 a) Prove the Demorgan’s laws using Boolean algebra. 2. Q3 a) Differentiate between: i) Combinational and Sequential Logic Circuits. Otherwise under any other input condition. the output Q remains unchanged. hexadecimal. x5) = Sm (1. b) Find the minimal sum of product expression for the following Switching function. 17.55 base 10 into binary. . T(toggle) and C(clock) and output Q and Q’. The output state is complemented if T=1 and the clock C changes from 1 to 0. x4. 9. 30. 27. ii) Synchronous and Asynchronous Counters Q4 Do as directed a) Conversion of 100. 14. 26. x2. 31) + Sd(4. b) Design and explain Priority encoder. The circuit has two inputs. octal codes. 25. State its merit. b) Conversion of 1111010011011110 base 2 to decimal. F (x1. 8.flops? b) Design a negative edge triggered T flip flop. How this can be used as a DEMUX. Q5 a) Draw the circuit of a 3 to 8 decoder and explain its operation. x3. Q2 Mention the various A/D convertors. Case Study An m: 1 multiplexer has m data inputs. Q3 Draw the circuit of a 4-bit shift registers and explains its operation. Each different combination of control signals selects a different input. Present an implementation. of an 8: 1 multiplexer. . either as a circuit diagram or as equations. And Draw and discuss the circuit of a dual scope A/D convertor. Show how 8: 1 multiplexers can be cascaded to build a 64: 1 multiplexer. Design a counter made from JK flip-flops to produce a three-bit Gray code. 01. log2m control signals and produces a data output which is equal to the input selected by the control signals. 11. Also discuss the comparison of advantages and disadvantages of each of A/D convertor. 10. 00 …is a two-bit Gray code.ASSIGNMENT ‘B’ Q1 A Gray code is a sequence of codes which differ in one bit position at each step. Also explain Various different types of shift register with circuit diagram. For example 00. a) True b) False Q4 Decimal that converts from decimal to binary numbered is called________________ a) Encoder b) c) Decoder Converter d) CPU Q5 The binary number 101100.ASSIGNMENT ‘C Q1 8421 code is a) Self -complementing code b) Weighted code c) Non-weighted code d) Alphanumeric code Q2 ASCII code is a a)5-bit code b)7-bit code c) 8-bit code d)10-bit code Q3 In synchronous counters the clock input of each of the bi-stables are connected together so that each changes state at the same time.6 .110 in octal number will be a) 152. b) 154. 0. which of the following voltage levels does not denote logic '0'? a.4 volt c.100 b) Binary 1011 .1111 c)Binary 1111 .2 d) 174.111 d) Binary 11111 – 1111 Q8 Decimal 14 in binary system can be written as____ a) 1111 b) 1110 c)0111 d) 1100 Q9 In digital electronics.5 Q6 64 K is _____ . none of the above Q10 Aside from the binary system. none of the above Q11 In Boolean algebra the OR function is represented by the '+' sign. 0 volt b. <0. a) 6400 b) 64000 c)65536 d) 64536 Q7 Binary 1000 will be the result of which of the following a) Binary 1000 .8 volt d. a) True b) False Q12 A signal having discrete values is known as a) a digital signal b) an analog signal .6 c) 145. hexadecimal c. what other number system is commonly used in digital systems? a. scale-of-2 d. decimal b. c) a natural signal d) none of the above Q13 How many nibbles count in the number 1111 1110? a) 4 b) 8 c) 2 d) 16 Q14 If 2 in binary system 010 then 6 will be a) 011 b) 0111 c) 1110 d) None of the above Q15 What is binary equivalent of FC6 is __________ a) 1111 1100 0110 b) 011011001010 c) None of the above d) Both of the above Q16 The 2’s complement of 100001011 is ____________ a) 011110101 b) 001110100 c) d) 001111100 e) 000110100 Q17 Which of the following are universal gate: a) AND . c) A two-input OR gate.b) NAND c) NOR d) OR Q18 Which logic gate has the following truth table? Input Input Output A 0 0 1 1 B 0 1 0 1 C 1 0 0 0 a) An exclusive NOR gate. d) An exclusive OR gate Q19 In which gate output is complements of its input: a) AND b) NOT c) NOR d) None of the above Q20 In the Karnaugh map shown below. b) A two-input AND gate. which of the loops shown represents a legal grouping? . \ 00 01 CD t •____ 1 11 10 a) 1 0 0 11 0 1 _ h - <i \ v o \^ ¥ ^~~B ^~-c "^ l 0 ^-D A b) B c) C d) D Q21 How many gate inputs are required to realize the following expression? F=(B+C+D)(B+C+E)(A+B+C+E)(F+G) a) 14 b) 15 c) 16 d) All the above Q22 How many cells present in a 4-variable format? a) 16 b) 8 c) d) 32 None of t h a o e e b v . Q23 Is in positive logic circuits it is normal to use +5V for true and 0V for false? a) True b) False Q24 A logic circuit that accepts one data input and distributes it over several outputs is known as ______ . a) Two half adder b) Two half subtractor c) Both a and b . a) Decoder b) DMUX c) Priority Encoder d) All of the above Q25 The below circuit diagram is: a) 2-to-4 bit Binary decoder b) 4-to-2 bit Binary decoder c) 2-to-4 bit Priority decoder d) None of the above Q26 A full adder can be made by adding ______ . A7 d) 78. the output of the last flip-flop is connected back to the input of the first flip- flop.78_ c) 78.Q27 Master-Slave J-K flip-flop doesn’t solves the race around problem occurs in JK-flip-flop a) True b) False Q28 In a _________ .36)8 = (?)16 a) A6. a) b) c) d) Johnson counter Ring counter D-type flip-flop None of the above Q29 How many flip-flops are needed for an 8-bit counter? a) Two b) Three c) Four d) Eight Q30 Which of the following can be used in Keyboard encoder? a) b) c) d) Shift registers Flip-Flop Registers All of the above Q31 DAC converts ________ .A6 . a) Analog to Digital b) Digital to Analog c) Both a and b Q32 (247.78 b) A7. . a) b) c) d) Counter D Flip-Flop Register All of the above Q35 Which of the following are based on digital systems? a)Electronic calculator b) Voting Machine c) Traffic signal d) None of the above Q36 An OR gate is ENABLED by connecting one of its inputs to logic level____. a) 0 b) 1 c) 0 or 1 d) None of the above Q37 How many data inputs contains by a 64 output lines decoder? a) b) c) d) 64 6 2 All of the above Q38 A flip-flop with active low preset input will have Q’= _______ when preset is counted to low.Q33 (3F)16-(5C)16 = ( _______ )16 a) b) c) d) D1 1D_ D2 DE Q34 An array of flip-flop is also known as _________ . a) 1 b) 0 c) 1 and 0 d) None of the above. a) CMOS b) MOS c) CHIP .Q39 How many maximum possible number of states in a clocked sequential circuit having 6 Flip-flops? a) 32 b) 64 c) 16 d) None of the above Q40 A dynamic RAM is fabricated using ________ technology.