debussy0407

HDL Debugging with DebussyJul. 2004 財團法人國家實驗研究院國家晶片系統設計中心 Module 1 Module 2 Module 3 Module 4 Module 5 Module 6 Overview Design Understanding Watch Waveform Debug with Simulation Result Misc. nLint © 2000, Novas Software Duplication, reuse or transfer of ownership requires advance written authorization Page 1 HDL Debugging with Debussy Jul. 2004 財團法人國家實驗研究院國家晶片系統設計中心 Module 1 Module 2 Module 3 Module 4 Module 5 Module 6 Overview Design Understanding Watch Waveform Debug with Simulation Result Misc. nLint © 2000, Novas Software Duplication, reuse or transfer of ownership requires advance written authorization Page 1 The Engineer’s Desktop™ The Knowledge-Based ™ HDL Debugging & Analysis Environment for complex ICs, ASICs & Systems NOVAS Software, Inc. Module 1 Module 2 Module 3 Module 4 Module 5 Overview Design Understanding Watch Waveform Debug with Simulation Result Misc. © 2000, Novas Software Duplication, reuse or transfer of ownership requires advance written authorization Page 3 reuse or transfer of ownership requires advance written authorization .Introduction to Debussy Supported Simulators and File Formats License Environment Setup Invoke Debussy Common User Interface © 2000. Novas Software Duplication. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 4 Gate Level Source HDL Simulator High Level HDL Source Code Debussy PLI Routines VCD File CLDB Compact HDL Language Database FSDB Fast Signal Database FSDB R/W API nSchema nState nTrace nWave Debussy Page 5 © 2000. Debugging-Oriented Hierarchy Schematic Generator nState -. Novas Software Duplication.Finite State Machine Extraction and Analysis Tool Supported Platforms SUN SOLARIS 2.X or later Cadence NC-Verilog Viewlogic VCS 3.A Complete HDL Debugging Environment Four Key Components nTrace -. reuse or transfer of ownership requires advance written authorization Page 6 Supported Verilog Simulators through PLI/VCD files Cadence Verilog-XL 2.Hypertext Source Code Analysis and Browse Tool nWave -.X or later Linux Windows NT © 2000.Debussy .X IBM RS/6000 4.Universal Waveform Analysis Tool nSchema -. reuse or transfer of ownership requires advance written authorization Page 7 .1 or later Avant! Polaris Quickturn SpeedSim AXIS SureFire © 2000.X or later Model Tech ModelSim EE/Plus 5. Novas Software Duplication.5 or later HP-UX 10. Supported VHDL simulators through FLI/FMI/VCD files Cadence Leapfrog Cadence NC-VHDL Model Tech 5.out) Avant! HSPICE and STAR-SIM (.x or later Supported Simulators through VCD files Fintronic Finsim Any simulators that can generate VCD file © 2000.raw) Direct read / Translate to FSDB Direct read : No translation effort Translate to FSDB : less memory usage and thus better performance in nWave © 2000. Novas Software Duplication. Novas Software Duplication.trX) Silvaco SmartSpice (. reuse or transfer of ownership requires advance written authorization Page 9 . reuse or transfer of ownership requires advance written authorization Page 8 Other Simulators (time domain format only) Synopsys (EPIC) Timemill and Powermill (.x or later Support Mixed Language Simulators NC tools Model Tech 5. f <fileName> : specify a file which list all source files © 2000.vhdl | verilog : specify language type for import design from source (verilog by default) . reuse or transfer of ownership requires advance written authorization Page 11 .Add binary to the search path setenv NOVAS <install_dir> set path=($NOVAS/bin $path) Specify search path of license file setenv LM_LICENSE_FILE <license_file>:$LM_LICENSE_FILE Specify ASIC symbol library & path setenv TURBO_LIBS “<ASIC_NAME#1> <ASIC_NAME#2> . Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 10 Invoke Debussy by command : debussy [<options>] [<source files>] Some options : .lib++ % setenv TURBO_LIBS “artisan_u faraday_l” % setenv TURBO_LIBPATHS “/home/debussy/share/symlib /home/asic1/lib” © 2000.…” setenv TURBO_LIBPATHS “<Directory#1> <Directory#2> …” /home/debussy/share/symlib/artisan_u.lib <libName> : specify library name .top <topModule> : specify top module for import design . Novas Software Duplication.lib++ /home/asic1/lib/faraday_l. Always use Left Mouse Button Click the LMB to select single design objects like signals. Novas Software Duplication. instances. Drag & Drop with Mouse Perform the cross window operations. then drag the selected objects and drop to the destination window.. Press and hold the Right Mouse Button. You can invoke Debussy by : debussy -f run.Debussy takes all the simulator command line options. Press and hold the middle mouse button. then select the Drag/Drop command. © 2000. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 12 Select with Mouse -. Context Sensitive Menu with Right Mouse Button Context sensitive with the object be pointed Click Right Mouse Button and select command. Extract all the options from verilog. . Invoke Debussy the same way as you invoke Verilog: debussy [<your verilog options>] Use Makefile file Add Debussy to your Makefile with the same options as you run Verilog.log file and save them to an option file like run. reuse or transfer of ownership requires advance written authorization Page 13 . Drag LMB through an area to select the objects enclosed.f.f © 2000. Hold the Shift key and click the LMB to add object to selection list.. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 15 . Novas Software Duplication.Import Design Traverse Design Trace Driver and Load Schematic View Partial Schematic FSM Extraction © 2000. reuse or transfer of ownership requires advance written authorization Page 14 Source Window Hierarchical Browser Message Window © 2000. f © 2000.. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 16 Compile VHDL / Verilog code to library Use vhdlcom to compile VHDL source code to library Use vericom to compile Verilog source code to library Syntax vericom / vhdlcom [<options> . reuse or transfer of ownership requires advance written authorization Page 17 .(default: work) Example: vhdlcom –lib asic025 –93 -f cells.. Novas Software Duplication.Two ways to import design From library From file Why design library Use library in VHDL design Batch mode compilation for Verilog / VHDL Verilog incremental compilation Mixed language design (Compile two languages into the same database) © 2000.] [<files>] Options -lib <libname> : the library name which design is compiled into.f vericom –lib work –inc –f run. lib++ vital = .cpu” GUI mode Files->Import Design->From Library Select top scope from the list of Design Unit © 2000. Novas Software Duplication./work..rc Syntax [VHDL_libraries] logical name = physical location Example @debussy rc file Version 1. reuse or transfer of ownership requires advance written authorization Page 19 . debussy –top “work.0 .lib++ asic = ../asic025.Command line Specify library : -lib <libname> (default : work) Specify top : -top <cell name>+ e.system work.lib++ © 2000. reuse or transfer of ownership requires advance written authorization Page 18 Need library mapping before compiling VHDL design for which use library in it Map library logical name to physical location in debussy. Novas Software Duplication.g./work. [VHDL_libraries] work = . <product>/etc/debussy.std_logic_1164.Example: library IEEE.rc 2. Novas Software Duplication. © 2000. reuse or transfer of ownership requires advance written authorization Page 21 .rc © 2000. “IEEE” and “vital” are logical library name Search sequence of rc files: . Novas Software Duplication.VHDL-93 .Verilog Select source files or the file list to “Add” Top Design Unit Verilog : Find top scope automatically VHDL : a design unit list window will pop up for user specifing top scope after compilation. $HOME/debussy.VHDL-87 . use IEEE.all.all.VHDL Library Define Syntax . reuse or transfer of ownership requires advance written authorization Page 20 Language format . use vital.rc 3.(Setting in latter file will overwrite in former one) 1. .functions. use std./debussy.standard.all. reuse or transfer of ownership requires advance written authorization Page 23 . nSchema with new design and reload waveform data in nWave. reuse or transfer of ownership requires advance written authorization Page 22 Traverse Design .Update design in Debussy database Use Files->Reload Design if design is changed. Novas Software Duplication.Hierarchy Browser Expand/Collapse design tree by clicking on the Plus / Minus icon The Open Folder icon indicate the current scope displayed in the source window. Different icon for unused task/function © 2000. © 2000.incremental compile modified files with -inc Reload Design command will update nTrace. Novas Software Duplication. Re-compilation From File : all source files will be re-compiled From Library : VHDL .incremental compile modified files by default Verilog . Double click on a design unit to view the content in the source window. reuse or transfer of ownership requires advance written authorization Page 24 Color-coded source code display with built-in syntax-directed checker and editor. module . Novas Software Duplication. Double click to hyperlink between design unit definition and reference. The color can be changed in Tools->Preferences Display Parameter or Variable Defines with tips. Cursor will become a hand-sign when falling on an instance.Pop view up from port Select a port of a design unit Trace->Pop View Up From Port Push view in from port Select a net connects to the port of an instance Trace->Push View In From Port © 2000. Double click on a signal name to find the driver.task or signal. reuse or transfer of ownership requires advance written authorization Page 25 . © 2000. Novas Software Duplication. Novas Software Duplication. Click on Trace Load or Trace Driver icon to trace the selected signal's driver or load. Search in all files / current file Use Source -> Find String… to find with case sensitive / insensitive. © 2000. Novas Software Duplication. click on Show Next/Previous Instance icon to cycle through them. Forward and Backward commands to recall. © 2000.Quick Locating Strings in Source Window Search in current file Use Find String on toolbar with case sensitive. Use Show Next/Previous to cycle through the driver/load in the current Scope. reuse or transfer of ownership requires advance written authorization Page 27 . reuse or transfer of ownership requires advance written authorization Page 26 Double click on a signal to trace its driver. Trace history to keep track of the last 32 trace results. If there are multiple drivers located in multiple instance. reuse or transfer of ownership requires advance written authorization Page 28 Select an instance in Hierarchical Browser and click on New Schematic icon A nSchema window will be opened and the content of the instance is displayed. Novas Software Duplication. partial schematic Flatten. full scope schematic Hierarchical. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 29 .Forward History Show Next Show Previous Instance Trace Load Trace Driver Backward History Show Previous Show Next Instance © 2000. which includes the Hierarchical Browser. You can execute Tools -> New Schematic in nTrace and nSchema to invoke nSchema in different view. partial schematic © 2000. Hierarchical. (hierarchical schematic) D&D an instance from Hierarchical Browser to icon You can execute View->Schematic View in nTrace to use the nSchema as the main window. flip-flop output.nSchema will generate RTL schematic for your RTL Design from synthesis point of view. nSchema will generate a hardware meaning symbol for each RTL statement (either continuous assignment or always block). reuse or transfer of ownership requires advance written authorization Page 30 © 2000. Novas Software Duplication.clock. Novas Software Duplication. set. flip-flop or combination logic Signal type -. reset. latch output or tri-state output © 2000. reuse or transfer of ownership requires advance written authorization Page 31 .latch. The RTL block will represent the following things Block type -. • Directly Drag&Drop a schematic object to nTrace will display the corresponding source code. Novas Software Duplication. © 2000.Tools -> Options -> Preferences -> Schematics -> RTL Extraction -> Detail RTL Same schematic as 4.4 Detail RTL © 2000. reuse or transfer of ownership requires advance written authorization Page 33 . Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 32 • Double click on an bottom level RTL Block will bring up the corresponding source code in an INFORMATION dialog box. signal …) that you want to view. • Directly Drag&Drop objects into Full Hierarchical Window will change to corresponding scope and highlight them.• Select obejcts(instance.. • Directly Drag&Drop objects into partial schematic will add them. © 2000. finds signals or instances in current scope from the list. reuse or transfer of ownership requires advance written authorization Page 35 . reuse or transfer of ownership requires advance written authorization Page 34 Schematic -> Find In Current Scope. Schematic -> ViewMark © 2000. Novas Software Duplication. Novas Software Duplication.. Schematic -> Find Singal/Instance… finds signals or instances in whole design. Select object and use <Delete> key to remove object from schematic. Focus on a specified primitive for debugging Select a primitive and Tools->New Schematic->Flatten Window Focus on a specified net’s driver/load or path Select a net and Tools->New Schematic->Driver / Load / Connectivity / Fan-In Cone / Fan-Out Cone Double click on instance pin to expand driver/load. © 2000. reuse or transfer of ownership requires advance written authorization Page 37 . Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 36 View partial schematic of full design(cross hierarchy).Three kind of schematic windows supported • Full Hierarchical Window – show complete objects in specified scope • Browser Window – show partial schematic in specified scope. Novas Software Duplication. • Flatten Window – show partial schematic in flatten view Full Hierarchical Window Browser Window Flatten Window © 2000. Trace net to register/tri-state or design boundary Fan-In Cone – useful to show all logics that affect the specified net Fan-Out Cone – useful to show the clock tree Trace All Paths Between Two Points Specify two points by entering the net names or D&D from the schematic. Novas Software Duplication. Trace from one instance’s output port to another instance’s input port. The results are shown either directly in the schematic or in a generated partial schematic. © 2000. reuse or transfer of ownership requires advance written authorization Page 39 . always @(a or cs) begin ns=cs. rst. S3=2'b11. parameter [1:0] S0=2'b00. module FSM_2Proc (clk. input clk. ns. 2-process example on right. case (cs) S0 : if (a) ns=S1. 2-process. a. S2 : ns=S0. b). endcase end endmodule Double click on the state block to invoke nState. S1=2'b01. or 3process with conventional encoding of the state variable. default: ns=S0.S2=2'b10. a.1-process. else cs=ns. Novas Software Duplication. b. rst. reuse or transfer of ownership requires advance written authorization Page 41 . always @(posedge clk or posedge rst) if (rst) cs=S3. Option to view logic gates instead of bubble diagram: View -> Viewing Mode -> No FSM © 2000. reg [1:0] cs. S3 : if (a & b) ns=S2. S1 : ns=b ? S2 : S3. Complex Event Comparison Analog Waveform Overlap Analog Expression © 2000. Novas Software Duplication. Label Marker Signal Processing . Novas Software Duplication. Constraint. reuse or transfer of ownership requires advance written authorization Page 43 .Value.View -> State Action View -> Transition Condition View -> Transition Action © 2000. reuse or transfer of ownership requires advance written authorization Page 42 Overview Display Simulation Result Open a simulation output file and Get signal waveform Bus Operations Search .Logical Operation. LB Double Click on a Bus Name to Expand/Collapse Bus Mouse in Value Window .LB Drag: Zoom Area Mouse in Full Scale Ruler .LB: Set Cursor Position .LB Drag on Window Boundary Zoom Scale Ruler Signal Value Window Window Signal Cursor Position © 2000.LB: Set Cursor Position .MB: Set Marker Position .RB: Invoke Context Sensitive Menu .RB: Zoom Cursor .LB Drag: Zoom Area To Resize Signal/Value Window .RB: select bus value display format Mouse in Waveform Window . Novas Software Duplication.MB: Set Marker Position . reuse or transfer of ownership requires advance written authorization Page 44 Screen and Mouse Buttons Definitions Pull Down Cursor Marker Mouse in Signal Window .LB Double Click on a Group Name to Expand/Collapse Group . reuse or transfer of ownership requires advance written authorization Full Scale Ruler Scroll Bar Page 45 . You can invoke standalone nWave under UNIX by typing: Unix% nWave © 2000.MB: move Signal Cursor Position . Novas Software Duplication.LB: select/deselect Signal/Group Menu Position Position Delta Tool Bar .Click on the New Waveform icon to invoke nWave. Novas Software Duplication.. Right.Zoom Drag the area you want to see Fast zoom on the Full Scale Ruler Zoom Cursor Zoom Out.fsdb If you open a simulator output file in VCD or SmartSpice format. If you open a simulator output file in Spice binary format or Powermill / Timemill format. The default extension for FSDB file is . to specify which file is active You can convert a VCD file to FSDB file in UNIX environment: vfast <VCD File> [options] © 2000. nWave will open the new FSDB file automatically. Can open several files in the same window Use the File-> Set Active. nWave can either read it directly or translate into FSDB. Novas Software Duplication. Down with menu command or bind keys Pan to the area cursor at the center Pan to the area marker at the center With scroll bar Last View Use View -> Last View command © 2000. Up.fsdb. Fit Pan Left. reuse or transfer of ownership requires advance written authorization Page 46 Open an FSDB file which is generated by Verilog simulator (through PLI) or Debussy's translator. reuse or transfer of ownership requires advance written authorization Page 47 . Zoom In(2X). nWave will invoke the conversion utility vfast to translate it to an FSDB file with an file extension .. Use trace command and then Add Result to Wave in nSchema. Command Directly Drag & Drop signals from nTrace or nSchema to nWave. reuse or transfer of ownership requires advance written authorization Page 48 Use Signal -> Get Signals. reuse or transfer of ownership requires advance written authorization Page 49 .Load FSDB with specified time range Note : Need Debussy 5. double click on signal or click “Add” button to get signal © 2000. Novas Software Duplication... Select objects and use Add Select Set To Wave in nSchema. Novas Software Duplication.0 format FSDB © 2000. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 51 . reuse or transfer of ownership requires advance written authorization Page 50 Generate waveform for VHDL variable Approach 2 : Calculate variables’ value by Debussy Load FSDB file Calculate value of the selected variable by its related signals / variables Only support in D&D from nTrace to nWave © 2000.Generate waveform for VHDL variable Approach 1 : fsdbDumpVariable FLI Dump to FSDB file directly Need to specify the variables separately The naming rules of variables are different between different simulators (ModelSim and NC-VHDL) Ex: fsdbDumpVariable /system/line__85/flag © 2000. Novas Software Duplication. Octal. © 2000. Easy to choose alias table for a specified signals.Display Bus Value by Waveform -> Signal Value Radix -> Binary. reuse or transfer of ownership requires advance written authorization Page 53 . Novas Software Duplication. ASCII. Novas Software Duplication. Decimal. Expand Bus Double click on a bus name to expand / collapse the bus. © 2000. Alias Waveform -> Signal Value Notation -> Unsigned / Signed 2's Complement / Signed 1's Complement Add Alias to Selected Bus A Sample Alias File ADD 8’h00 SUB 8’h11 JMP 8’h12 Display SUB instead of 11 on Waveform and Value Window Create Bus Formed from the selected signals to create a new bus inserted at the signal cursor position. Hexadecimal. reuse or transfer of ownership requires advance written authorization Page 52 Record multiple alias tables in the same file. Easy to edit alias table through GUI. reuse or transfer of ownership requires advance written authorization Page 54 You can search bus value and signal transition. Novas Software Duplication. Open Auto-created alias table automatically. For analog signal.. Novas Software Duplication. For bus signal.. © 2000.Use Waveform -> Signal Value Radix -> Browse Alias . Search value takes alias. reuse or transfer of ownership requires advance written authorization Page 55 . use Analog -> Set Search Analog Value… . use Waveform -> Set Search Value… . Browse different Alias Tables Click OK to apply alias for selected signals © 2000. command to invoke it. You can set the width of searched value. Novas Software Duplication. © 2000. reuse or transfer of ownership requires advance written authorization Page 57 . Useful for searching glitch (width <= 0).Use Waveform -> Set Search Constraint… . reuse or transfer of ownership requires advance written authorization Page 56 Support Multiple markers User-defined label for each marker Waveform Marker… Labels always visible at the top of curve window © 2000. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 59 . reuse or transfer of ownership requires advance written authorization Page 58 Event/Complex Event Search Function as Logic Analyzer Editing specific Event Signal->Event->Event Editing complex event from existed Event Signal->Event->Complex Event Support Save/Restore © 2000. © 2000. command creates a new signal from other signals.Logical Operation. Novas Software Duplication... Novas Software Duplication. cursor/marker position Window->Sync. reuse or transfer of ownership requires advance written authorization Page 61 . Novas Software Duplication. Novas Software Duplication. Vertical Scrolling to synchronize signal viewing in vertical direction © 2000. reuse or transfer of ownership requires advance written authorization Page 60 Tools->New Waveform to open multiple nWave Window->Tile Waveform to tile window Window->Sync. Waveform View to synchronize viewing of two windows in viewing area.Event/Complex Event Search (cont.) Display captured event on waveform. © 2000. cycle or expression Tools -> Waveform Compare -> Options… One or two sets of condition signal settings Support Time range Mismatch tolerance Comparison stop control © 2000. Novas Software Duplication. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 62 Conditional Comparison of Waveforms Three ways to define comparison base: clock. reuse or transfer of ownership requires advance written authorization Page 63 .Open 2 waveform Load different simulation result to each window Use Tools Waveform Compare to compare 2 signal /selected signals /2 group Use Left / Right arrow on toolbar to step through the mismatch errors mismatch © 2000. Novas Software Duplication. Novas Software Duplication. .select bus signal and use Waveform -> Analog Waveform Display analog signal value in digital form.Display digital signal value in analog form. reuse or transfer of ownership requires advance written authorization Page 65 .Merge selected signals to one single signal inserted at the yellow signal cursor position bar. © 2000. reuse or transfer of ownership requires advance written authorization Page 64 Overlay . Two options.select analog signal and use Waveform -> Digital Waveform © 2000. Auto Fit and Auto Color/Pattern supported. . reuse or transfer of ownership requires advance written authorization Page 67 . reuse or transfer of ownership requires advance written authorization Page 66 Use Analog Expression to process analog waveform. Novas Software Duplication. © 2000.Select analog signals Analog->Zoom Value © 2000. Novas Software Duplication. .. reuse or transfer of ownership requires advance written authorization Page 68 Find all the X of register and tri-state outputs from the simulation result Organize the list of X signals by occurred time Support filter the X signals by time range signals / scopes X minimum width Double clicking to invoke Trace X (nTrace) Tools -> List X. reuse or transfer of ownership requires advance written authorization Page 69 .Module 4 Debug with Simulation Result List X / Trace X Active Annotation in nTrace / nSchema Active Trace / Bus Contention Active Fan-In Cone Show Memory FSM Analysis © 2000. Novas Software Duplication. Novas Software Duplication. © 2000. The extension name is . Novas Software Duplication. Novas Software Duplication.xloc. reuse or transfer of ownership requires advance written authorization Page 70 Support batch mode extraction xloc –o <output file> <FSDB file> [ other xloc options] Support Save result / Load result List X -> Build or xloc utility will generate binary format result. reuse or transfer of ownership requires advance written authorization Page 71 .Extract X from the opened FSDB and save result Load the designate signals from a list file Load the designate scopes from a list file Search Next/Previous © 2000. © 2000. List X -> Open File load the xloc file. and perform Tools->Trace X in nWave © 2000. Novas Software Duplication. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 72 Quickly find the cause of Unknown by one click © 2000.Generate partial flatten schematic to Show the X signal Trace driver to next register or tri-state output Annotate the value change How to invoke Trace X Double click on the report of List X Move cursor to the time point where the selected signal is X. reuse or transfer of ownership requires advance written authorization Page 73 . nTrace and nSchema. no matter whether their waveform are displayed © 2000. It will also display signal transition. reuse or transfer of ownership requires advance written authorization Page 75 . Any signals can be annotated if they are dumped.Active Annotation in Source Window Use Source ->Active Annotation to annotate simulation result to source window. It will annotate the signal values at the cursor time and display the values under each signal.Moving Cursor Time You can select a signal in the source window and search its next or previous transition . Novas Software Duplication. © 2000. reuse or transfer of ownership requires advance written authorization Page 74 Active Annotation . Novas Software Duplication. Execute the above commands will move the cursor time in nWave. The transition may be Any Change . Rising or Falling . You can select a signal first and use left / right icons to advance forward / backward the cursor time by value change. The annotated signals are not necessarily displayed. Novas Software Duplication. After turning on Active Annotation. Novas Software Duplication.Note: The waveform displayed here is just for your reference. the following icons will be enable on the nSchema toolbar. © 2000. reuse or transfer of ownership requires advance written authorization Page 76 Invoke Schematic -> Active Annotation command to annotate the current signal values on nSchema. © 2000. rising edge or falling edge. reuse or transfer of ownership requires advance written authorization Page 77 . Active Trace Static Trace – trace all the possible drivers based on connection Active Trace – trace the real driver based on FSDB at the cursor time How to invoke Active Trace Double clicking on the waveform Active Trace in RMB menu in nTrace window Double click to invoke Active Trace List all the drivers and mark real driver The real driving statement © 2000.s. reuse or transfer of ownership requires advance written authorization Page 79 . Novas Software Duplication. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 78 Static Trace v.© 2000. © 2000. reuse or transfer of ownership requires advance written authorization Page 80 Use List X in nTrace / nWave to list tri-state output which has value X. Use Tools -> Bus Contention in nWave to show all the real drivers.Select a signal and invoke Tools -> Active Fan-In Cone to generate Flatten Window with possible drivers in specified cycle time. © 2000. Select a signal and move Cursor Time to the time point that Unknown occurs and invoke Tools -> Trace X to generate Flatten Window with tracing X to next storage element. Novas Software Duplication. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 81 . Select a signal and move Cursor Time to the time point that Unknown occurs and invoke Tools -> Bus Contention to detect whether it is caused by Bus Contention. Double click tri-state bus in the list to invoke Trace X will generate Flatten Window to show the cause of X. reuse or transfer of ownership requires advance written authorization Page 82 Two situations need to find out X Register Simulation fail caused by timing violation Simulation fail caused by un-initialized storage element How to Find out X Register Use List X in to list register output which has X. Novas Software Duplication.Show active driver in partial schematic Select the signal which has multiple drivers in nWave Change cursor time to where you want to find the real driver Perform Tools->Bus Contention Show the partial flatten schematic of the real driver and annotate current value © 2000. Double click on a signal in the list to invoke Trace X to generate Flatten Window for this specified signal. Novas Software Duplication. Double click on instance port to expand driver. © 2000. reuse or transfer of ownership requires advance written authorization Page 83 . Active Fan-In Cone Trace Fan-In Cone to extract partial schematic which contains all the possible logic that affect the signal Back trace from here! © 2000. Novas Software Duplication.s.© 2000. reuse or transfer of ownership requires advance written authorization Page 84 Fan-In Cone v. reuse or transfer of ownership requires advance written authorization Page 85 . Novas Software Duplication. Support changing value radix for memory value and address. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 87 . Record memory contents only when $fsdbDumpMem is executed. reuse or transfer of ownership requires advance written authorization Page 86 Use Debussy PLI $fsdbDumpMem to record memory contents in FSDB. Binary to Hexadecimal © 2000. Novas Software Duplication.Active Fan-In Cone to trace the subset which have events occurred during specified period from the fan-in cone Back trace the signal to find the driving logic had events during the last 200 ns © 2000. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 88 Show Memory Contents in nWave Directly Drag & Drop selected memory to nWave. © 2000. The operation of memory is same as that of individual signal.Search specified value at current time point. reuse or transfer of ownership requires advance written authorization Page 89 . © 2000. The field fits the pattern will highlight. Click Search Next and Search Previous to find all fitted fields. Novas Software Duplication. FSM-> Analysis Report to display a report. Save to File command provided. Outputs. Inputs. reuse or transfer of ownership requires advance written authorization Page 91 . Clock and state signals report. Novas Software Duplication. State table list. © 2000. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 90 FSM -> State Animation State Sequence Animation © 2000. Load simulation result to detect unreached state and state transition. reuse or transfer of ownership requires advance written authorization Page 92 nTrace : Tools -> Extract Interactive FSM… nSchema : Tools -> Extract Interactive FSM… Use State Animation in each nState window. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 93 .© 2000. © 2000. Novas Software Duplication. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 94 Save Session / Signal Debussy PLI Start Interactive Simulation Control Invoke and Control Simulator Set Breakpoints Set Focus Step Through Source Code Watch Signals User-Defined Command nLint © 2000. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 95 .© 2000. openDirFile [-d delimiter] [-s time_offset] path_name f openDirFile -d / "/ae6a/evan/temp/Verilog/RTL" "deb44 . Magic 271485 Revision 1. – Recover previous debugging status from a session file.000000 marker 4150. windowTimeUnit is used for zoom.If there is a file opened in nWave.. Note: . fileTimeScale ### s|ms|us|ns|ps . . Window Layout <x> <y> <width> <height> <signalwi viewPort 5 30 960 332 102 67 . file time scale: . Restore Signals .Save current displayed signals to an ASCII file for future restore.. reuse or transfer of ownership requires advance written authorization Page 96 Save Signals .Display the signals with what you saved in the previous session. reuse or transfer of ownership requires advance written authorization Page 97 .000000 © 2000.Save Session command in nTrace will save the signals too.Save Session. . Novas Software Duplication.000000 12500.. Novas Software Duplication.rc file. the original signals must be kept..000000 cursor 6250. cursor & marker .0 . File list: . – Save the debugging status to a session file which includes : Displayed Waveform and Their Setting All the Windows and Their Content Preference Bookmark Restore Session. © 2000. waveform viewport range zoom 0. the Restore Signals command will ignore the Open command in the above .If there are signals created by other signals by user. signal spacing: signalSpacing 3 . . [<size>]]) – Dump the contents of specified memories.Turn on the FSDB dumping $fsdbDumpoff .Verilog $fsdbDumpvars([<level>]...all.PLI commands to Dump FSDB . .Turn off the FSDB dumping $fsdbDumpflush . "top").pkg. © 2000.vhd Set environment variable for modelsim FLI setenv LD_LIBRARY_PATH /usr/debussy/share/PLI/modelsim_fli53/SOLARIS2/:$LD_LIBRARY_PATH Refer to the novas package use novas_lib. <scope | signal>*) $fsdbDumpfile(“<FSDB name>”) $fsdbDumpMem(<reg name>. Novas Software Duplication.vhd into working directory and complie cp /usr/debussy/share/PLI/modelsim_fli53/SOLARIS2/novas.vhd \ . “<FSDB name>”.. fsdbDumpvars(0.< number of file>) – Limit FSDB file size and switch dumping to new FSDB file automatically $fsdbDumpon . Novas Software Duplication./novas.vhd vcom -work novas.Force to Dump Result to FSDB file © 2000. $fsdbSwitchDumpFile(“<new FSDB name>”) – switch dumping to another FSDB file $fsdbAutoSwitchDumpfile(<file size>. reuse or transfer of ownership requires advance written authorization Page 98 Create library in working directory cd ~working_directory vlib work Copy novas. [<start addr>. reuse or transfer of ownership requires advance written authorization Page 99 . VHDL fsdbDumplimit .Switch dumping to another FSDB file.fsdb –s /system –level 1 \ /system/I_cpu/I_ALUB –level 0 –o new.Limit FSDB file size fsdbDumpfile .Simulation Commands to Dump FSDB .fsdb –o all. fsdbDumpSingle . © 2000.Limit FSDB file size and switch dumping to new FSDB file automatically fsdbDumpflush . fsdbSwitchDumpFile . reuse or transfer of ownership requires advance written authorization Page 101 . Novas Software Duplication.fsdb –s /system/data –bt 0 –et 4000 © 2000. fsdbDumpvariable .Dump the specified signal.Specify FSDB file name fsdbDumpvars . Novas Software Duplication.fsdb 2.fsdb fsdbreport Report value change of the specified signal to a text file % fsdbreport verilog. % fsdbextract verilog. fsdbAutoSwitchDumpfile .fsdb fsdbmerge merge multiple FSDB into one FSDB file.Dump the specified VHDL variable. reuse or transfer of ownership requires advance written authorization Page 100 fsdbextract extract partial content of original FSDB to new FSDB by scope or time range.Force to Dump Result to FSDB file fsdbDumpMem . % fsdbmerge 1.Dump the contents of specified memories.Dump the specified scope. NCVerilog. Verilog_XL. Novas Software Duplication.Before You Start VHDL: You must link the FLI/FMIprogram provided by Debussy with your VHDL/Verilog simulator first.Two menu Simulation and Debug will be added in nTrace. Speedsim and VCS is supported at this release.A new toolbar will be added in nTrace. © 2000. reuse or transfer of ownership requires advance written authorization Page 103 . Please set simulator with Tools -> Options -> Preferences… command. . Interactive Toolbar © 2000. . Novas Software Duplication. Note: Only support Modelsim. reuse or transfer of ownership requires advance written authorization Page 102 Start Interactive Mode . NC_VHDL. LeapFrog.Use Tools -> Interactive Mode to go to Interactive Mode. reuse or transfer of ownership requires advance written authorization Page 105 . Novas Software Duplication.Click on the Run/Continue icon to start Verilog simulator. Novas Software Duplication. Verilog simulator will compile your design and go to Interactive Mode right away. Use Simulation -> Reset to reset simulator. © 2000. Use Simulation -> Finish to finish simulation. reuse or transfer of ownership requires advance written authorization Page 104 You can double click on the line number in source window to set a breakpoint. Double click on the line number again to delete the breakpoint. © 2000. Use Debug -> Breakpoints to set and control breakpoints. You can have the simulator run to some time by entering time value in the Time text field. Use Simulation -> Kill Simulator Process to kill the simulator process. Click on the Stop icon to stop your simulator while it is running. Novas Software Duplication.You can turn on Active Annotation to annotate signal values to source code.Next Event Next Unit Time Step . The values annotated will be updated in real time. © 2000. User can resize the window and place it anywhere.You can use the above commands to step though your source code in different style. reuse or transfer of ownership requires advance written authorization Page 106 Use Debug -> User-Defined Commands to bring up the userdefined commands window which contains the Verilog commands user defined. © 2000. reuse or transfer of ownership requires advance written authorization Page 107 . Novas Software Duplication. . Keyword in Command Line : ${Arg:<String>} With such keyword in Verilog command Debussy will pop up a form for user to enter a value . \n .Use the selected signals in the source window as arguments. Note : Command is case sensitive © 2000. Press <Insert> key to modify. reuse or transfer of ownership requires advance written authorization Page 109 . Novas Software Duplication.Use the selected instance in Hierarchical Browser as argument.Use the selected signal (only one signal allowed) in the source window as arguments. reuse or transfer of ownership requires advance written authorization Page 108 Button Name : The button name of this command shown on the command window. © 2000. Novas Software Duplication. which is used as the argument for this command . Command : The Verilog command.<CR Return> you have to add this at the end of your Verilog command if you want this command be executed immediately. ${treeSelScope} . while user click this command button. The editing is effective right away and stored to your environment automatically. . ${SelVars} ${SelVar} .Click on edit button to bring up editing user-defined commands window to add or edit commands. reuse or transfer of ownership requires advance written authorization Page 111 . © 2000. A form will be popped up: .\n When user push this command button the following form pop up.User needs to select a signal in the source code window first and then click this command button. Modelsim will force the selected signal to 1 © 2000.For this example.Example 1: Next ? Time - #${Arg:Next Time} $stop.\n .For this example. Modelsim will run 1000 Time Unit and stop. Novas Software Duplication. . - User needs to specify a number in Next Time Field and press OK. Novas Software Duplication.User can specify the value to force signal. . reuse or transfer of ownership requires advance written authorization Page 110 Example 2: Force Variable Force ${selVar} = ${Arg:New Value}.. . . Novas Software Duplication. Verilog will force the selected signal to 8'H00 © 2000. Novas Software Duplication. - User needs to specify a number in Next Time Field and press OK. . reuse or transfer of ownership requires advance written authorization Page 112 Example 2: Force Variable Force ${selVar} = ${Arg:New Value}.User needs to select a signal in the source code window first and then click this command button.For this example.\n . reuse or transfer of ownership requires advance written authorization Page 113 . A form will be popped up: .For this example. © 2000. Verilog will run 1000 Time Unit and stop.\n When user push this command button the following form pop up.Example 1: Next ? Time - #${Arg:Next Time} $stop.User can specify the value to force signal. reuse or transfer of ownership requires advance written authorization Page 115 . …) Enforce naming convention and coding style © 2000. gate-level) Purify coding errors based on hardware meaning (ex: asynchronous loop.HDL desing rule checker for Verilog/VHDL Create syntax and semantics correct HDL code Early-stage checking of EDA tool compliant Simulation. RTL. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 114 Command line options: nLint {[GUI options]|[batch options]} [general options] [simulator options] GUI options: -gui (invoke with GUI mode) batch options: -out <output_file>: ascii format of the checking result -df <file_name>: specify one source file not to be checked -dm <module_name>: specify one module name not to be checked -uf <file_name>: specify the file list not to be checked general options: -rs <rs_file>: specify extra rule setting file -udr <udr_directory>: specify the location of the user defined rules simulator options: same as Debussy notes: -help: to list all options general options: apply to batch and GUI modes batch options: ignored by -gui option © 2000. DFT Target all abstract levels (behavior. clock used as data. Novas Software Duplication. Synthesis. rs in working directory The file path in environment variable NLINTRS The file path in command line option -rs © 2000. reuse or transfer of ownership requires advance written authorization Page 117 .Import Design Main window File -> Open From command lines Compile Design Click hierarchy Run -> Compile Suppress Files Suppress module RMB -> UnCheck © 2000.rs) Default nLint.rs in user’s home directory nLint. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 116 E/D Rule enable / disable TOFF suppressed rule Rule setting Rule setting file (.rs in <nLint_inst_dir>/etc nLint. Novas Software Duplication. ..reportDB (File -> Save. Novas Software Duplication. reuse or transfer of ownership requires advance written authorization Page 118 © 2000. File -> Save As . reuse or transfer of ownership requires advance written authorization Page 119 .rdb violation list General violation messages in ASCII format File -> Export Violation List … Batch mode: nLint -out <output_file> © 2000. Novas Software Duplication.) Binary database to save complete information User can load the result into nLint GUI Default extension name is . CA 95110 1-888-NOVAS-38 (1-888-668-2738) . Suite 480 San Jose. Inc. 2025 Gateway Place.NOVAS Software. 2025 Gateway Place. Copyright © 1996-2001 NOVAS Software. No part of this manual may be reproduced in any form or by any means without written permission of: NOVAS Software.Printing Printed on January 4. Copyright All rights reserved.S. Suite 480 San Jose.A.0 and higher versions. 2001. . CA 95110 U. Inc. Inc. The product names used in this manual are the trademarks or registered trademarks of their respective owners. Restricted Rights The information contained in this document is subject to change without notice. Trademarks Debussy is a registered trademark and Knowledge-Based Debugging is a trademark of Novas Software. Inc. Version This manual supports Debussy 5. ................................................................................ 15 Laboratory 2-5 17 Objective ................................. You Can View Source Code........... Invoke Debussy with Importing a Verilog Design...........................Contents Laboratory 1 1 Objective ......................................................................................................................................... 17 Laboratory 3 19 Objective ................... Import Design from File..... Import Mixed-Language Design............................................................................ 3 1............................................... 11 2.................................. 17 1........................................................................................................ 15 1.................................. 11 1.................................................................. 19 2.................................... 12 Laboratory 2-4 15 Objective ............................... 7 2............................................... Build Library from Map File......... 4 Laboratory 2-2 7 Objective ....................... From Source Code Window................................. 19 1............................... 4 3....................... View Your Symbol Libraries....................................................................... Invoke Debussy with Importing Design from Library.. 8 Laboratory 2-3 11 Objective ................................................................................ 15 2................................ 3 2............................... Import Design from Library.............. ........ Bulid a Symbol Library from Synopsys ....................... View Hierarchy and Traverse Your Design from Hierarchy Browser.............................................................. ..................................................... 7 1........................................................ ................................................. Import Design from File...........................................................8 3..................................................................... 2 Laboratory 2-1 3 Objective . 1 2... Set Library's Environment Variables and then Import Design from File again............ 21 ........ ...................................................................................................................... 20 4......... Invoke and Quit Debussy. Import Design from Library.... Import Design from Library........ 1 1............................................................ Import Gate Level Design from File............ 17 2... Import Design from Library to Debussy....................... Compile a Mixed Language Design.......................................... Invoke Debussy with Replaying What You Had Done Before......................... 19 3......................................... 2 3............................................................................lib File... Traverse Design and Trace Signals' Drivers/Loads/Connectivity............................ .................................................................................. 28 Laboratory 4-2 33 Objective .... 37 2.................... The Signal in Question is carry_flag....... 44 4......................... 49 1............................................ 51 .. Display the Waveform of the Instance........ Understand FSM from nState............................. Compile and Elaborate the Verilog Design for NC_Verilog ........................................................................... Load Simulation Result............. carry_flag_reg................................................... 25 Laboratory 4-1 27 Objective .............. Understanding Your Design from nSchema .............. ................. 23 6.................................................................................................... Use User-Defined Commands to Run the Simulation.................. Display Signals' Waveform......................................... Invoke Debussy with the VHDL Design. 43 2........................................................................... 49 3..................... Watch Interested Signals....................................... Isolate the Problem..... Run Verilog-XL Interactive Mode Simulation ...................... Now We Assume the Transition from 3 to 55 of ALU[7:0] at Time 1051 Was Wrong and We Have to Find Out the Real Cause(s).................................................................. .. 44 3... Run Verilog-XL Simulation........... 49 2................... Use User-Defined Commands to Run the Simulation................. 39 5................... 34 4... Compare the Simulation Result ................. Re-Run Verilog-XL Simulation ...................................................... 25 7............................... Invoke Debussy with Importing Mixed Language Design from Library............................. 33 2................... 37 1. 28 4......................................................................... 33 3.................................................................................. 43 1................ 35 6...................... Invoke Debussy and Load the Gate-Level Design............. 38 4.......................................................................5........................................................ Quit Debussy.. Run ModelSim VHDL Interactive Mode Simulation ............. Invoke Debussy with the Verilog Design............................ Set Breakpoints......................... 27 2.................................................................. 36 Laboratory 5-1 37 Objective ...... then Choose Verilog-XL Simulator for Running Verilog-XL Interactive Mode in Debussy..... Load Gate-Level and RTL Simulation Results .................... Run NC_Verilog Interactive Mode Simulation................................................................... 27 1.. 33 1.......................... 27 3.............................................................................................................. . 50 4................................. ................................................. 45 Laboratory 5-3 49 Objective ................. 38 3......................................... Invoke Debussy with the Verilog Design ............................................................................... 34 5.. ............................... Compile and Elaborate the Verilog Design for NC_Verilog ..................... 40 Laboratory 5-2 43 Objective .......................................... % Debussy & Note This action will open an nTrace window. to keep some information. STEP 2: Quit the invoked Debussy. Note We will use File->Exit for this kind of action later. Debussy 5. click File and then choose Exit. DebussyLog. You can invoke Debussy by % debussy as well. Debussy will open a log directory. 1. Invoke and Quit Debussy STEP 1: Invoke Debussy.log will be opened if you imported a design into Debussy. Please execute each action of "%" below. compiler. % On nTrace's Pull-Down Menu. They are Debussy.0 Hand-On Labs Laboratory 1 • 1 .Laboratory 1 Objective This lab is purposed to give you a brief on invoking Debussy.cmd and turbo.log. log. Invoke Debussy with Replaying What You Had Done Before STEP 1: Invoke Debussy.log.0 Hand-On Labs . % File->Exit 2 • Laboratory 1 Debussy 5.2. compiler. Under it.f & Note This will open a log directory. Invoke Debussy with Importing a Verilog Design STEP 1: Invoke Debussy.cmd and turob. % debussy -f run. STEP 2: Quit the invoked Debussy. debussy. % Debussy -play Debussy.cmd & STEP 2: Quit the invoked Debussy. % File->Exit 3. debussyLog. there are three log files. lib file.lib++ Under <Debussy_Inst_Dir>/p_symlib directory. Build Library from Map File. A. % map2SymDB simple. Debussy will reference two symbol libraries. Please follow each action of "%". By default. we provide two approaches. Debussy recognizes the required properties. there are some built standard cell libraries for various foundries. such as.lib++. input/output/inout pins.Laboratory 2-1 Objective For your owned or licensed cell libraries. <Debussy_Inst_Dir>/share/symlib/default_l. With symbol libraries. Debussy 5. etc. <Debussy_Inst_Dir>/share/symlib/default_u. From Synopsys's . Below contains two examples of library building. From map file and B. 1.0 Hand-On Labs Laboratory 2-1 • 3 . To build symbol libraries. They are A. the control pin of tri-state and mux. clock and data pins of storage elements.lib++ and B. STEP 1: Use map2SymDB utility to build a symbol library.map Note This will build mapLib. you need to have symbol libraries before importing your Gate level design into Debussy. 0 Hand-On Labs . STEP 1: Use syn2SymDB utility to build a symbol library. STEP 2: Bulid symbol library and create a map file with a specified library name.lib File. then click OK.map. % On the opened Load Symbol form.lib. % Debussy -play replay. press Shift+L.map Note This will build simple_l. you will know syn2SymDB's use model. fill ". where "SIMPLE" is the declared library name in synopsys. % syn2SymDB synopsys. Please use help option to know map2SymDB's use model. % On the opened schematic window (nSchema).lib++ with lowercased cell and pin name.lib++.lib Note This will build simple_u. Bulid a Symbol Library from Synopsys . % syn2SymDB -m -o simple_u synopsys. View Your Symbol Libraries.STEP 2: Build symbol library with a designated library name and lowercased cell and pin name. 2.cmd & STEP 2: View the built symbol library. and simple_u.lib++. STEP 1: Replay the steps those had been done in the lab of importing RTL level design. 4 • Laboratory 2-1 Debussy 5. % map2SymDB -o simple_l -L -l simple." in Library Path and "simple_l" in Library Name. With -help option. 3.lib Note This will build SIMPLE. Debussy 5. you will find the symbols of "simple_l.Note On nSchema.0 Hand-On Labs Laboratory 2-1 • 5 . File->Exit. For other invoked windows.lib++". Note You can quit Debussy from nTrace window only. % On nTrace window. STEP 3: Quit Debussy. you can use File->Close to close them. . % On opened nTrace. Import design from file and B.Laboratory 2-2 Objective Debussy provides two approaches to import your designs: A. STEP 3: Quit Debussy. STEP 1: Import gate level design through a pre-prepared run file. % File->Exit Debussy 5. Please execute each action of % below as the labs of Gate level design importing. File->View Import Log Note The compiled result is stored in DebussyLog/compiler. 1.log.0 Hand-On Labs Laboratory 2-2 • 7 .f & STEP 2: View the compiled result from Debussy. Import Gate Level Design from File. Why there are so many errors? Those errors were caused by you did not set TURBO_LIBS and TURBO_LIBPATHS environment variables properly. you need to build your owned libraries and set two required environment variables properly to import your design correctly and view your design in nSchema. Import design from library For Gate-Level Designs. % Debussy -f run. Click + of i_cpu(CPU) % Drag & Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon. STEP 4: Quit Debussy. Set Library's Environment Variables and then Import Design from File again. you will see the schematic composed by the built symbols. % On Hierarchy Browser./lab2-1 % setenv TURBO_LIBS SIMPLE STEP 2: Import gate level design. 8 • Laboratory 2-2 Debussy 5. Import Design from Library.. File->Exit 3. % Debussy -f run. % On nTrace. STEP 1: Compile gate level design.2. STEP 2: Import design from pre-compiled library.0 Hand-On Labs . Note On the opened nSchema. STEP 1: Set library's environment variables.f & STEP 3: View schematic.lib++. % vericom -f run.f Note This will compile the design into work. % setenv TURBO_LIBPATHS . % On nTrace. File->Exit Debussy 5. Click + of i_cpu(CPU) % Drag & Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon STEP 4: Quit Debussy.% Debussy -lib work -top system & STEP 3: View the schematic view.0 Hand-On Labs Laboratory 2-2 • 9 . % On Hierarchy Browser. . STEP 1: Import design as the same way to run a Verilog simulation (specify all options and source files on command line).0 Hand-On Labs Laboratory 2-3 • 11 ..v \ ../design_src/verilog/rtl/CCU.log./design_src/verilog/rtl/alu.v \ .Laboratory 2-3 Objective This lab is purposed to give you a brief on importing a Verilog RTL design into Debussy.v \ . % File->View Import Log Note The imported result will be kept in DebussyLog/compiler./design_src/verilog/rtl/PCU. % File->Exit Debussy 5.v \ -v . Import Design from File./design_src/verilog/src/system..../design_src/verilog/src/mem./design_src/verilog/rtl/ALUB....v \ . Please execute each action of "%" below./design_src/verilog/rtl/BJkernel.v STEP 2: View the compiled result./design_src/verilog/rtl/TopModule.v \ . STEP 3: Quit Debussy. % Debussy +dump+strength \ ../design_src/verilog/rtl/BJsource. you will see the compiled result.v \ ./design_src/verilog/src/pram.. % On nTrace's message window. 1.v \ .v \ . /design_src/verilog/rtl/run_rtl. STEP 2: Import design from library by the specified library name and root (or top) module. such as mux and storage elements in the opened nSchema. Import Design from Library. % Drag&Drop i_ALUB(ALUB) to New Schematic icon Note You will see meaningful symbols. % On Hierarchy Browser. 12 • Laboratory 2-3 Debussy 5. % Debussy -lib work -top system & STEP 3: View the imported design. click + of i_cpu(CPU) Note After the action.f Note This will compile the design into work.lib++. File->Exit 2.STEP 4: Import design as the same way to run a Verilog simulation (specify all options and source files in a run file). i_CCU and i_PCU will be expanded from i_cpu(CPU).0 Hand-On Labs . i_ALUB.f & STEP 5: View the imported design. % On nTrace. % Debussy -f run.. % vericom -f . STEP 1: Compile the Verilog design. STEP 6: Quit Debussy. % On Hierarchy Browser. % On nTrace.0 Hand-On Labs Laboratory 2-3 • 13 . click + of i_cpu(CPU) % Drag&Drop i_ALUB(ALUB) to New Schematic icon STEP 4: Quit Debussy. File->Exit Debussy 5. . f & STEP 2: View the imported design on nSchema. % File->Exit 2. % Debussy -vhdl -f run. Import Design from Library. % On Hierarchy Browser. Import Design from File.f Debussy 5. % vhdlcom -f run. click + of i_cpu(cpu(blk)) % Drag&Drop i_alub(alub(rtl)) to New Schematic icon STEP 3: Quit Debussy. 1. Please execute each action of % below. STEP 1: Compile your VHDL design. STEP 1: Import design from a run file. % On Set Top Module window. double click system to choose it as the top module.Laboratory 2-4 Objective This lab is purposed to give you a brief on importing a VHDL RTL design into Debussy.0 Hand-On Labs Laboratory 2-4 • 15 . % On the Import form.lib++.Note This will compile the design into work. click + of i_cpu(cpu(blk)) % Drag&Drop i_alub(alub(rtl)) to New Schematic icon STEP 4: Quit Debussy.0 Hand-On Labs . % On Hierarchy Browser. % Debussy -lib work -top system & STEP 3: View the imported design on nSchema. % File->Exit 16 • Laboratory 2-4 Debussy 5. STEP 2: Import design from library by the specified library name and top architecture. click system to choose it as the top design. f STEP 2: Compile VHDL part. Use vhdlcom to compile all VHDL design files. First. Import Mixed-Language Design STEP 1: Compile Verilog part. Please execute each action of "%" below. only importing from library is supported. and B. STEP 2: Quit Debussy. % Debussy -lib work -top system & Note We will have some more detail analysis to understand this mixed language design later. Invoke Debussy with Importing Design from Library STEP 1: Import design from library by specifying the library name and root (or top) module. % vhdlcom -f run_vhdl. A. Then import your mixed-language design from library. you have to compile your design into Debussy. 1.f 2. Debussy 5. Use vericom to compile all Verilog design files.0 Hand-On Labs Laboratory 2-5 • 17 .Laboratory 2-5 Objective To import mixed-language design. % vericom -f run_verilog. % File->Exit 18 • Laboratory 2-5 Debussy 5.0 Hand-On Labs . Laboratory 3 Objective This lab will give you a brief scenario on design understanding. The design is in mixed language. Please execute each action of "%" below. 1. Compile a Mixed Language Design STEP 1: Compile Verilog source code. % vericom -f run_verilog.f STEP 2: Compile VHDL source code. % vhdlcom -f run_vhdl.f 2. Import Design from Library to Debussy STEP 1: Import design by the specified library and top module. % Debussy -lib work -top system & Note nTrace window will be opened. On nTrace, it contains three windows. a. On the left side, it's the Hierarchical Browser to show design hierarchy. b. On the right side, it's the Source Code window to display the design's content. c. On the bottom, it's the Message window for reporting the result of operations. Debussy 5.0 Hand-On Labs Laboratory 3 • 19 3. View Hierarchy and Traverse Your Design from Hierarchy Browser STEP 1: Collapse the design tree of system. % Click at "-" which locates on the left side of system(blk). Note "-" will be change to "+". From Source Code window, you can see system is in VHDL. STEP 2: Expand the design tree of system. % Click at "+" which locates on the left side of system(blk). Note "+" will be changed to "-". STEP 3: Expand the design tree of i_cpu and change the viewing scope of Source Code window to CPU module. % Double click at i_cpu(CPU). Note From Source Code window, you will know CPU is in Verilog. STEP 4: Expand the design tree of i_ALUB(ALUB) and change the viewing scope of Source Code window to ALUB module. % Double click at i_ALUB(ALUB). Note On Source View Window, the scope will be changed to ALUB which is a Verilog module. Also, the tree of i_ALUB(ALUB) was expanded. STEP 5: Change the viewing scope to arithlogic. % Double click at i_alu(arithlogic(arithlogic)). Note On Source View Window, design scope was changed to arithlogic which is a VHDL entity. 20 • Laboratory 3 Debussy 5.0 Hand-On Labs STEP 6: Change the viewing scope to CPU module. % Double click at i_cpu(CPU). 4. From Source Code Window, You Can View Source Code, Traverse Design and Trace Signals' Drivers/Loads/Connectivity. STEP 1: Jump to the first instantiation. % On Source Code window, double click at CPU in line 30. Note On Source Code window, the design scope had been changed to line 107 of system. Line 107 is the Verilog instantiation of CPU. STEP 2: Jump to the module declaration. % Double click at i_CPU on line 107. Note Now, the design scope was changed back to CPU module. STEP 3: Trace signal's drivers. % Double click at data in line 35. Note This action is used to find the drivers of the clicked signal. You can see all the traced drivers are reported in the Message Window. STEP 4: Trace the next or previous drivers in the same design scope. % Click Show Next and then Show Previous icons. Note This will jump to the drivers in the same design scope. For this case, it is i_pram(pram2(pram)). Debussy 5.0 Hand-On Labs Laboratory 3 • 21 You can do STEP 4 ~ 6 to jump to the load in the same way as tracing signal's drivers. STEP 8: Select a signal./design_src/mixed/vhdl/RTL/PCU_record.STEP 5: Trace the next or previous drivers in different design scope.. click at data in line 35. % Click Trace Load icon.vhd(100): data <= n_q0. Note This will jump to the drivers in different design scope. STEP 9: Add a bookmark. % On Source Code Window. double click icpu(CPU). Note This will directly jump to the driver you are interested. double click *<D> . % On Message Window. % Source->Toggle Bookmark STEP 10: Trace loads of data[7:0]. STEP 7: Change the viewing scope to i_cpu. % Click Show Previous In Hierarchy and then Show Next In Hierarchy icons. data[7:0] bus. STEP 6: Jump to the driver's location from Message Window. Note This will list all of loads that are drove by data. % On Hierarchy Browser.0 Hand-On Labs . 22 • Laboratory 3 Debussy 5. 5. % Drag&Drop any mux symbol from nSchema to nTrace. Understanding Your Design from nSchema STEP 1: Invoke nSchema window. click at data in line 35. STEP 12: Trace the connectivity of data[7:0]. % Source->Bookmark->1 Note This will go back to line 35 of TopModule. Debussy 5. Note This will display RTL in schematic representation.0 Hand-On Labs Laboratory 3 • 23 . % On Source Code Window.STEP 11: Jump to the interested bookmark. Note The respective code of the symbol will be highlighted and selected. % Double click at any mux symbol Note A View Source Code window will be opened to show the contents of the symbol. % Drag&Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon.v. STEP 2: Know the content of extracted RTL symbols. % Trace->Connectivity Note This will trace all of connections of data and report them on Message Window. click PopView Up icon.i_ALUB to system. % On nTrace. Note This will pop up design one level. STEP 7: Push down the design hierarchy of ALUB % On nSchema. % On nSchema. 24 • Laboratory 3 Debussy 5. % (nTrace)Source->Bookmark->1 STEP 5: Select data[7:0] bus again.i_cpu. double click at ALUB. % Drag&Drop data from nTrace to nSchema. STEP 8: Pop up the design hierarchy. select second output from the top on the ALUB symbol. STEP 4: Jump to the marked bookmark. STEP 9: Generate the fan in cone logic of ALU[7:0] bus % On nSchema. STEP 6: Select data[7:0] bus on nSchema. the design scope will be changed from system. Note On nSchema.0 Hand-On Labs . click data in line 35.STEP 3: Select the signals those were selected in nTrace window. % Drag&Drop the highlighted source code on nTrace to nSchema.i_cpu. % Double click at fsm_master symbol block % Double click at the FSM symbol to invoke nState. % Turn on (nState) View->Transition Action to display each transition's actions. % On the first opened nSchema. click PopView Up icon until it reaches to system level. Quit Debussy % (nTrace)File->Exit Debussy 5.% (nSchema)Tools->New Schematic->Fan-In Cone Note The fan-in cone logic of ALU[7:0] will be displayed in another nSchema window. STEP 3: Show the FSM's properties. % Turn on (nState) View->Transition Condition to display each transition's conditions. STEP 4: Show the content of a state. Understand FSM from nState STEP 1: Invoke nState from nSchema.0 Hand-On Labs Laboratory 3 • 25 . 7. you will know their design hierarchy. % Turn on (nState) View->State Action to display each state's action. % Turn on (nState)FSM->Machine Properties to display FSM's properties. Click any extracted symbol blocks to select them. 6. STEP 2: Show states' behave. The fan-in cone logic is in flatten mode. % Drag and Drop ST0 from nState to nTrace's Source Code window to show its content. 0 Hand-On Labs .26 • Laboratory 3 Debussy 5. the work library had mapped to .. % On nWave toolbar. 1.fsdb to open it.lib++. % On nTrace toolbar. Invoke Debussy with Importing Mixed Language Design from Library. Load Simulation Result.Laboratory 4-1 Objective This lab will give you a brief scenario on how to debug your design with simulation result. % Debussy -lib work -top system & Note In debussy./understanding/work. you can do it from (nTrace)File->Load Simulation Result. Note To load simulation result. Please execute each action of "%" below. too. STEP 2: Load the simulation result.rc file. click at New Waveform icon or Tools->New Waveform. % On the Open Dump File. STEP 1: Invoke nWave window. STEP 1: Use the library pre-compiled for the lab of understanding you designs. 2. Debussy 5. click Open File icon or File->Open.0 Hand-On Labs Laboratory 4-1 • 27 .. double click demo./. STEP 3: Calculate VHDL variables' value. (So far. then Drag&Drop i_ALUB(ALUB) to nWave. 4. STEP 1: Get signals from FSDB's tree structure. double click at the transition from 3 to 55 of ALU[7:0] at time 1051 ns. Now We Assume the Transition from 3 to 55 of ALU[7:0] at Time 1051 Was Wrong and We Have to Find Out the Real Cause(s). Note This action will show you the active drivers of the signal at the transition on nTrace's Source Code window.0 Hand-On Labs . STEP 1: Annotate the simulation result onto nTrace's Source Code window. none of VHDL simulators provide functions to dump VHDL's variables).3. % On Hierarchy Browser. 28 • Laboratory 4-1 Debussy 5. % On waveform window. % (nTrace)Source->Active Annotation STEP 2: Find out where is the transition from. For this example. it's line 96 of i_alu(arithlogic(arithlogic)). STEP 2: Get IO boundary of i_ALUB. click at "+" of i_cpu(CPU). % Click Get Signal icon and then select some signals and OK. Display Signals' Waveform. % Drag&Drop result in line 96 from nTrace to nWave. Note signal "a" will be changed name to "X0" in ALUB. Note There are 14 drivers reported on the message window. It will be time consumed if we trace back the logic of all drivers.v since the design connectivity. in line 96. Debussy calculates VHDL's variable value of the same process. STEP 5: Find the real driver (active trace) of result (Please note.). Debussy 5. Note There will pup-up a warning message since the time was changed back by 1ns. Now. % Select a_var which is the real driver of result and RMB->Active Trace to find out the real driver of a_var. Note RMB means click the Right Mouse Button.Note Drag&Drop a variable from nTrace to nWave. It means the real driver is coming from this line. % Select "a" which is the real driver of a_var and RMB->Active Trace to find out the real driver of "a". the time is 1051 ns now. STEP 6: Find the real drivers of the traced real drivers. % Click Backward History icon on nTrace toolbar for backwarding to STEP 4. The changed back was resulted from the delay of after 1 ns. % Double click on result in line 96 of nTrace. Will you do that? Let's find the real active drivers to reduce the efforts dramatically.0 Hand-On Labs Laboratory 4-1 • 29 . % RMB->Active Trace to find the real drivers of result. STEP 4: Find out all drivers of result. result in line 65 was selected. % Select "IDB" in line 80 on Source Code window and then Tools->New Schematic>Fan-In Cone Note An nSchema is opened with the logic driving "IDB". 30 • Laboratory 4-1 Debussy 5. Double click the input pin of the storage element to trace the logic back. It is another mux with the select line value is 1. % Double click at the second input of the MUX. generate another Fan-In Cone to make schematic more clean by Tools->New Schematic->Fan-In Cone.Note You can do the active trace again. so the first (the topest) input is what we need to concentrate in advance. so you have to know the value of the select line in order to know which input is active. You can select some blocks to know they are from different hierarchy and in flatten mode. wouldn't it be great if we could see a schematic that shows only the logic driving "IDB" (the active driver of "X0"). it's the logic drove by a tri-state. % Annotate simulation result from Schematic->Active Annotation. STEP 7: Generate the Fan-In Cone for "IDB". The select line is 0 now. Please zoom into regions those you want to know the value of nets detailly by yourself. it's a functional block. Note Fan-In Cone will stop at storage elements. STEP 8: Annotate simulation result on the generate Fan-In Cone window.0 Hand-On Labs . it's schematic with the output is drove by a tri-state and memory component. % On the newly opened nSchema. % The top input of the MUX is coming from a storage element. % IDB is driven by a MUX. functional blocks. FSMs and primary IOs. % Select the output of the tri-state and then. indenpendent of hierarchy? Let see the following. % (nSchema)Schematic->Active Annotation STEP 9: Analyze the generated Fan-In Cone to find the real cause. % Double click at the input of the functional block. But. Note The enable pin of the tri-state is low active and now its value is 1. you can see the output value is 34->55 which is 55 coming from. STEP 10: Analyze the memory's content to know what resulted in the transition (from 3 to 55 of ALU[7:0]). So it means the output is driving by the memory.0 Hand-On Labs Laboratory 4-1 • 31 . % Steps forward or backward on the memory content window until time is 900ns. Note You can step through time and see the memory values change. (If you step forward on the memory content window again. This is the cause of ALU[7:0] changing from 3->55. File->Get Memory->Variable and Time->Sync Cursor Time. the time will shift to 1200ns that is not the cause since the timing is wrong. Note On the second Fan-In Cone schematic window. % Display memory content by (nTrace)Tools->Memory.) Debussy 5. . % syn2SymDB synopsys. Please execute each action of "%" below. % setenv TURBO_LIBPATHS . % setenv TURBO_LIBS SIMPLE STEP 3: Compile the Gate-Level design. STEP 1: Find carry_flag through a string search. Invoke Debussy and Load the Gate-Level Design.lib STEP 2: Set environment variable for the built symbol library. STEP 1: Build Gate-Level symbol library.0 Hand-On Labs Laboratory 4-2 • 33 . The Signal in Question is carry_flag. 1. % vericom -f run.f STEP 4: Load the compiled design.Laboratory 4-2 Objective This lab will give you a scenario on how to debug your design when you find un-matches between RTL and Gate-Level simulations. % Debussy -lib work -top system & 2. Debussy 5. you can find carry_flag is the output of carry_flag_reg. carry_flag_reg. STEP 2: On the nTrace's message window. STEP 2: Load Gate-Level simulation result. invoke an nWave. % (nWave)Tools->New Waveform STEP 4: From the newly opened nWave. STEP 1: Drag&Drop the instance carry_flag_reg to both nWave windows. load the RTL simulation result. double click on the driver. % On the message window. % (nWave)File->Open->gate. enter carry_flag. then click Find. % File->Open->rtl. Note This will figure out the position of the instance. choose In All Files.fsdb 4. 34 • Laboratory 4-2 Debussy 5. % Tools->New Waveform or click New Waveform icon.fsdb STEP 3: Open another nWave from the opened nWave. Display the Waveform of the Instance. Load Gate-Level and RTL Simulation Results STEP 1: From nTrace.0 Hand-On Labs . 3. Deselect Match Case.% (nTrace)Source->Find String. TFD2. STEP 3: Locate the mismatch. select carry_flag. % On the Gate-Level nWave window.0 Hand-On Labs Laboratory 4-2 • 35 . Compare the Simulation Result STEP 1: Select carry_flag on both nWave windows. Window->Sync Waveform View 5. % On the Gate-Level nWave window. % On the Gate-Level nWave window. STEP 2: Compare the simulation result.% Drag&Drop carry_flag_reg from nTrace to both nWave windows STEP 2: Tile and synchronous both nWave windows. Window->Sync Waveform View % On the RTL nWave window. Note The input to the register in Gate-Level design (carry) changes right around the clock edge to cause the mismatch. Tools->Waveform Compare->Compare Selected Signals Note One error was reported and the Search By toolbar will be changed to Search By Mismatches. click the right arrow toolbar. Window->Tile Waveform Note You can tile windows on any nWave window. % On the RTL nWave window. select carry_flag. % On the Gate-Level nWave window. % On the Gate-Level nWave window. Debussy 5. % On the Gate-Level nWave. the Fan-in cone logic had been reduced and it is very clean for you to do further analyses. we need to reduce it to easily analyze. STEP 2: On nTrace. Isolate the Problem STEP 1: Show active driver of carry in nTrace. STEP 3: Since there are too much logic. select carry and the rising edge. % Double click on the rising edge of carry. 36 • Laboratory 4-2 Debussy 5. % (nTrace)Tools->New Schematic->Fan-In Cone Note It will take couple seconds since the Fan-In Cone is big. then Tools->Active FanIn Cone. then click Apply button.6. Note Now.0 Hand-On Labs . generate Fan-In Cone for carry. specify 10ns in Back Trace Time Period. In this lab. Before your start. In the file. 1./SOURCEME to set your working environment properly..:$CDS_INST_DIR/tools. Solaris2 platform will be taken as the working platform.sun4v/lib:$LD_LIBRARY_PATH Debussy 5. and b. DEBUSSY_INST_DIR STEP 1: Generate shared libraries for linking PLIs % source .Laboratory 5-1 Objective This lab will give you a scenario on how to control your Verilog-XL simulation in Debussy.. Please execute each action of "%" below. Run Verilog-XL Interactive Mode Simulation You have to link Debussy provided PLI to Verilog-XL by Cadence's vconfig utility. modify . to execute cr_vlog_sol2_dym to generate shared libraries.so and libvpi.sl.. For different platforms.0 Hand-On Labs Laboratory 5-1 • 37 . % setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib % setenv LD_LIBRARY_PATH \ .so will be created./SOURCEME % cr_vlog_sol2_dym Note Two shared library libpli. it will generate libpli. The cr_vlog_sol2_dym file is the pre-prepared configure file. it marked how to configure vconfig to generate the shared libraries by a dynamic PLI linking at the beginning of the file. you have to set the correct environment variable for a. Take HP as an example.sl and libvpi. CDS_INST_DIR./. the configured file and the generate shared libraries will be different. STEP 2: Add the path of the shared library to LD_LIBRARY_PATH environment variable. Also. STEP 1: Set a line breakpoint. 38 • Laboratory 5-1 Debussy 5. % Double click at the line number 78 on line number section./debussy. 3.f & STEP 2: Choose the simulator to Verilog-XL and control the simulation to stop at 0 initially and remember the Breakpoints. Watch Interested Signals. this won't set the line breakpoint successfully. (The setting is kept in . STEP 1: Invoke Debussy with the Verilog design. % Debussy -f run. Invoke Debussy with the Verilog Design. % Tools->Interactive Note The toolbar was changed to interactive mode's toolbar. Note If you run the simulation under the same directory.2. the setting will be kept until you modify it.rc file.) STEP 3: Change Debussy's working mode to interactive mode.0 Hand-On Labs . Set Breakpoints. % Tools->Options->Preferences->Simulation->Verilog-XL % Turn on Stop At Time 0 % Turn on Remember Breakpoints For Next Simulation % Click OK button. Note If you double click in line 78 on Source Code Window. then Choose Verilog-XL Simulator for Running Verilog-XL Interactive Mode in Debussy. Debussy 5. STEP 2: Continue the Simulation.0 Hand-On Labs Laboratory 5-1 • 39 . % Click Run/Continue icon on the toolbar or Simulation->Run/Continue Note You will see the design was compiled for Verilog-XL and some information. 4. % Source->Active Annotation Note The value of all signals are NF (Not Found) since The simulation didn't start yet. % Tools->Watch Signals % Drag&Drop alu_mode in line 39 to the opened Watch window. In Watch window. then click Any Changed button. % Fill in 350 in Time Field and click Break At Absolute Time button.STEP 2: Set a conditional breakpoint.fsdb and the pre-set breakpoints on message window. such as. STEP 3: Set Time-based breakpoint. STEP 4: Watch some interested signals. then Drag&Drop alu_mode in line 39 to the Signal field. % Debug->Set Breakpoints. value of the watched signals is NF. Run Verilog-XL Simulation STEP 1: Compile the design. opened verilog_i. double click i_cpu on Hierarchy Browser to change the viewing scope on Source Code Window to CPU. % Click Run/Continue icon. the line break. Note It stooped at 550 ns which was caused by alu_mode[2:0] was changed from 0 to 3. the time is 350 ns. % Click Run/Continue icon. In Watch window. % Click Run/Continue icon. The obviously declared finish time in line 70 of system.v. % Click Run/Continue icon. % Click Run/Continue icon on the toolbar or Simulation->Run/Continue 40 • Laboratory 5-1 Debussy 5. % Click Next Unit Time Step icon Note It stooped at line 69 of Bjsource. % Click Next Event icon Note It stooped at line 69 of Bjsource.i_cpu. % Click Run/Continue icon. the value of all_mode[2:0] was changed from NF to X since the initialization had been done. occurred. Re-Run Verilog-XL Simulation STEP 1: Compile the design.v.0 Hand-On Labs .Note The simulation is stop at line 78. Note The simulation still stop at 25 ns since the breakpoint. alu_mode changed from X to 0. Note The simulation is terminated since it reaches 12500ns. 5. Note The simulation will stop at 350. the time-based breakpoint.v. % Remove Any Change on system. but the time is 351 ns.alu_mode from Breakpoints window. % Click Run/Continue icon. the time-based breakpoint since the breakpoint of alu_mode[2:0] had been removed. the line break.STEP 2: Continue the Simulation.v. % File->Exit Debussy 5. Note The simulation will stop at 350. Note The simulation is terminated since it reaches 12500ns. % Click Run/Continue icon.0 Hand-On Labs Laboratory 5-1 • 41 . % Source->Active Annotation % Click Run/Continue icon. Note The simulation is stop at line 78. STEP 3: Quit Debussy. The obviously declared finish time in line 70 of system. . DEBUSSY_INST_DIR STEP 1: Generate shared libraries for linking PLIs../SOURCEME % make -f Makefile. you have to source . INSTALL_DIR. For different platforms. we customized them for dynamic link already..Laboratory 5-2 Objective This lab will give you a scenario on how to control your NC_Verilog simulation in Debussy.. 1.0 Hand-On Labs Laboratory 5-2 • 43 . the customized options in Makefiles and the generate shared libraries are different. Run NC_Verilog Interactive Mode Simulation To run NC_Verilog interactive mode simulation./. Before your start.so and libvpi. In this lab./.. % source . you have to link Debussy provided PLI to NC_Verilog by customizing the Cadence provided Makefiles.. We will use Solaris2 platform to go through the lab.sun4v shared_libs Note Two shared library libpli./SOURCEME or set the correct environment variable for a. CDS_INST_DIR b. it will generate libpli. Take HP as an example. and c.sl and libvpi./SOURCEME to set your working environment properly. STEP 2: Add the path of the shared libraries to LD_LIBRARY_PATH environment variable. You can get the original Makefiles from <CDS_INST_DIR>/tools/inca/files directory. To execute Makefile to generate shared libraries. To know how to customize the Makefiles. Debussy 5. Please execute each action of "%" below.so will be generated. modify .sl. please look at Debussy's installation document. ncelab. then choose NC-Verilog simulator for running NC_Verilog interactive mode in Debussy. 2.args for simulation. % ncprep -f run.% setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib % setenv LD_LIBRARY_PATH \ . Invoke Debussy with the Verilog Design Invoke Debussy with the Verilog design.args for compilation b. 3. ncsim.0 Hand-On Labs .:$CDS_INST_DIR/tools. you have to use the same flow to link the provided PLI. Compile and Elaborate the Verilog Design for NC_Verilog STEP 1: Prepare NC_Verilog working environment.sun4v/lib:$LD_LIBRARY_PATH Note For ncxlmode and ncverilog executable.args -access +r Note We won't run ncsim here since we will control the simulation in Debussy. ncvlog. and c. % Debussy -f run.args for elaboration.args -LINEDEBUG STEP 3: Elaborate Verilog design with -access +r to set default access visibility. STEP 2: Compile Verilog design with -LINEDEBUG option to enable line breakpoint and show current position.f +overwrite Note This will generate a. % ncvlog -f ncvlog. STEP 1: Invoke Debussy with the Verilog design.f & 44 • Laboratory 5-2 Debussy 5. % ncelab -f ncelab. % Click New Waveform icon % Drag&Drop i_cpu(CPU) from Hierarchy Browser to nWave Note The signal's values are x or XX. Debussy 5.0 Hand-On Labs Laboratory 5-2 • 45 .) STEP 3: Change Debussy's working mode to interactive mode. 4. Note If you run the simulation under the same directory. % Tools->Interactive Note The toolbar was changed to interactive mode's toolbar.STEP 2: Choose the simulator to NC-Verilog and control the simulation to stop at 0 initially and remember the Breakpoints./debussy. STEP 3: Edit User-Defined Commands. (The setting is kept in . % Click Run/Continue icon STEP 2: Open nWave window.rc file. % Tools->Options->Preferences->Simulation->NC-Verilog % Turn on Stop At Time 0 % Turn on Remember Breakpoints For Next Simulation % Click OK button. Use User-Defined Commands to Run the Simulation STEP 1: Start the simulation. the setting will be kept until you modify it. Note The simulation time is going to 575 ns. % On the Editing form.0 Hand-On Labs . click the left side of the bottom line % Type Next Cycle and then Entry key % Type Next 50 -relative\n and then Entry key % Click OK STEP 5: Run the Verilog Simulation. % Click Run/Continue button 46 • Laboratory 5-2 Debussy 5. % Click Next Cycle button Note The simulation time is going to 550 ns. then OK. STEP 6: Finish the simulation. click Next 500 Time button Note The simulation time is going to 500 ns and waveform of the displayed signals is changing. click the left side of the secondary line % Type Next 500 Time and then Enter key to change command from Next 1000 Time to Next 500 Time % Click the right side of the secondary line % Type run 500 -relative\n and then Enter key to change command from run 1000 relative\n to run 500 -relative\n STEP 4: Add a User-Defined Commands.% Debug->User Defined Commands % Click Edit button on the opened User-Defined Commands form % On the Editing form. % Click Next > Time button and fill in 25. % On User-Defined Command form. % File->Exit Debussy 5. STEP 7: Terminate the simulation.0 Hand-On Labs Laboratory 5-2 • 47 .Note The simulation time is going to 12500ns that is the obviously declared finish time in line 70 of system.v. % Simulation->Finish STEP 8: Quit Debussy. . Laboratory 5-3 Objective This lab will give you a scenario on how to control your ModelSim/VHDL simulation in Debussy. Before your start, modify ../../SOURCEME to set your working environment properly. Then execute each action of "%" below. 1. Run ModelSim VHDL Interactive Mode Simulation To run ModelSim VHDL interactive mode simulation, you have to link Debussy provided FLI shared library to ModelSim. To Link the FLI, in ../../SOURCEME, please set the following two variables properly. a. DEBUSSY_INST_DIR, and b. MTI_HOME STEP 1: Link the provided FLI shared library to ModelSim by adding the path of the provided FLI to LD_LIBRARY_PATH. % source ../SOURCEME % setenv LD_LIBRARY_PATH \ $DEBUSSY_INST_DIR/share/PLI/modelsim_fli53/SOLARIS2 % setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib:$LD_LIBRARY_PATH 2. Compile and Elaborate the Verilog Design for NC_Verilog STEP 1: Use vlib to create work and novas library directories. % vlib work Note If work/ directory existed, please use rm -rf work to remove it. % vlib novas Debussy 5.0 Hand-On Labs Laboratory 5-3 • 49 Note If novas/ directory existed, please use rm -rf novas to remove it. STEP 2: Use vcom to compile design into modelsim's library directories. % vcom -f run.f % vcom -work novas ../design_src/vhdl/src/novas.vhd 3. Invoke Debussy with the VHDL Design Invoke Debussy with the VHDL design, then choose ModelSim simulator for running ModelSim interactive mode in Debussy. STEP 1: Compile the VHDL design into Debussy library. % vhdlcom -f run.f STEP 2: Invoke Debussy with the VHDL design. % Debussy -lib work -top system & STEP 3: Choose the simulator to ModelSim and control the simulation to remember the breakpoints on next simulation. % Tools->Options->Preferences->Simulation->ModelSim % Click OK button. Note If you run the simulation under the same directory, the setting will be kept until you modify it. (The setting is kept in ./debussy.rc file.) STEP 4: Change Debussy's working mode to interactive mode. % Tools->Interactive Note The toolbar was changed to interactive mode's toolbar. 50 • Laboratory 5-3 Debussy 5.0 Hand-On Labs 4. Use User-Defined Commands to Run the Simulation STEP 1: Start the simulation. % Click Run/Continue icon STEP 2: Open nWave window. % Click New Waveform icon % Drag&Drop i_cpu(cpu(blk)) from Hierarchy Browser to nWave Note Some signal's value are U or UU those are the initialized VHDL values. STEP 3: Run the VHDL Simulation. % Debug->User Defined Commands % On User-Defined Command form, click Next 1000 Time button Note The simulation time is going to 1000 ps since the time unit defined in modelsim.ini is 1 ps. % Click Next ? Time button and fill in 10000, then OK Note The simulation time is going to 11000 ps. % On the Message Window, in the VSIM n> prompt, keyin run 12500 ns, then return STEP 4: Terminate the simulation. % Simulation->Finish STEP 5: Quit Debussy. % File->Exit Debussy 5.0 Hand-On Labs Laboratory 5-3 • 51