CS1104: Computer Organisation http://www.comp.nus.edu.sg/~cs1104 School of Computing National University of Singapore Lecture 1: Introduction CS1104-P2-1 Computer Organisation/Architecture Machine Organisation Buses Instruction Set Architecture (ISA) Questions Clock Cycles Central Processing Unit (CPU) Introduction 2 Lecture 1: Introduction Code Execution Memory CS1104-P2-1 Introduction 3 Computer Organisation/Architecture Computer organisation: electronics engineer’s view of a computer system. Computer architecture: assembly programmer’s view of a computer system – an abstract view. In practice, difficult to distinguish the two. Who needs to study this? Software engineers, embedded systems programmers, computer engineers. Introduction 4 CS1104-P2-1 Computer Organisation/Architecture (2) In-depth understanding of the inner-workings of modern computers, and trade-offs present at the hardware/software boundary. Emphasis is on the concept understanding and not on the hardware implementation. Textbook: Computer Organizations and Design (The hardware/software interface) by David A. Patterson and John L. Hennessy, Morgan Kaufmann, 2nd ed, 1998. Read Chapter 1.2 and 1.3. Introduction 5 CS1104-P2-1 Machine Organisation von Neumann architecture: Programs and data are stored in memory (stored-memory concept). Consists of processor, memory and devices. Data are carried along buses between components. CS1104-P2-1 Introduction 6 Machine Organisation (2) Bus Processor Control Memory Devices Input Cache Datapath Output Registers CS1104-P2-1 Introduction 7 Buses Bus: A communication path between components. Data bus, control bus, address bus. Bus width: the number of lines (bits). Data bus width usually coincides with word size, which is also usually the register size. Address bus width determines the addressable address range. A n-bit address bus can address up to 2n locations. Introduction 8 CS1104-P2-1 Instruction Set Architecture (ISA) Computer Architecture = Instruction Set + Machine Organisation. The Instruction Set serves as the interface between hardware and software. ISA: “… the attribute of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.” – Amdahl, Blaaw and Brooks, 1964. CS1104-P2-1 Introduction 9 Instruction Set Architecture (ISA) (2) Applications Operating System Compiler Processor Firmware Instruction Set Architecture I/O system Memory organization Datapath & Control Digital Design Circuit Design Layout PART 1 Electrical Engineering 10 CS1104-P2-1 Introduction Instruction Set Architecture (ISA) (3) Some examples of ISAs: Digital Alpha HP PA-RISC Sun Sparc SGI MIPS Intel (v1, v3) (v1.1, v2.0) (v8, v9) (MIPS I,II,III,IV,V) (8086,80286,80286, 80486,Pentium,…) 1992-97 1986-96 1987-95 1986-96 1978-96 CS1104-P2-1 Introduction 11 Instruction Set Architecture (ISA) (4) Issues concerning an ISA design: Organisation of programmable storage Data types and data structures: encoding and representations Instruction set Instruction formats Modes of addressing and accessing data items and instructions Exceptional conditions CS1104-P2-1 Introduction 12 Questions 1) Computer architecture is a study of a) b) c) d) e) instruction set architecture only. programming language only. machine organisation only. (a) and (c) [Answer] (a), (b) and (c) 2) Instruction set architecture is an important interface between a) b) c) d) e) digital circuit and datapath control. application software and operating system. application software and hardware organisation. [Answer] compiler and programming language. high-level programming language and assembly language. Introduction 13 CS1104-P2-1 Questions (2) 3) Which of the following does not belong to the definition of an ISA? a) b) c) d) e) Instruction formats and types. Compilation of a C program into machine code. [Answer] Encoding and representation of data in memory. Modes of addressing and accessing data in memory. None of the above. Hardware implementation of machine organization is part of the instruction set architecture definition. Instruction set architecture is an interface between the assembly language and the machine language. A Pentium II processor running at 450 MHz & a Pentium II processor running at 500 MHz have the same ISA. [Ans] Computer architecture is a subset of the instruction set architecture. None of the above. Introduction 14 4) Which of the following statements is true? a) b) c) d) e) CS1104-P2-1 Questions (3) 5) Which of the following statements is true about ISA? a) b) c) d) e) If two machines can read and understand the same piece of memory data, they must have the same ISA. If two machines have the same ISA, they must have the same performance. In general, executable codes for one ISA cannot be run on another, different ISA. [Answer] The ISA of a processor defines the hardware implementation of the processor. None of the above. “Changing the hardware machine organisation will definitely change the instruction set architecture (ISA).” [False] CS1104-P2-1 Introduction 15 6) State whether this statement is true or false: Questions (4) 7) Which of the following can be considered as part of the ISA design? a) b) c) d) e) Specification of high level languages such as JAVA or “C”. Compiler that translates high level language programs into machine language codes. Machine instruction types such as “ADD” or “LOAD”. Data accessing method by the processor. Implementation of hardware functional units in the processor. [Answer: (c), (d)] CS1104-P2-1 Introduction 16 Clock Cycles A synchronous system is synchronised according to a clock. Rising edge Falling edge Clock period A clock cycle is the duration between two consecutive rising (falling) edges, and its duration is also known as the clock period. CS1104-P2-1 Introduction 17 Clock Cycles (2) The clock frequency is the reciprocal of clock period, measured in Hertz (Hz): number of cycles per second. A clock with period of 250ns (nano-seconds) has a frequency of 4MHz. A B Clock A has twice the clock period than that of clock B, and half the frequency of B’s. CS1104-P2-1 Introduction 18 Central Processing Unit (CPU) CPU = Control Unit + ALU + Registers. Control Unit: monitors and directs sequences of instructions. ALU (Arithmetic-Logic Unit): performs simple arithmetic and logical operations. Examples: Add, subtract, and, or, invert, increment, etc. A B R = A op B select ALU R CS1104-P2-1 Introduction 19 n-bits operations Central Processing Unit (CPU) (2) Registers: Fast memories in the CPU, storing operands, temporary results and status information. General-purpose registers and special registers: CS1104-P2-1 PC (program counter) ACC (accumulator) IR (instruction register) MAR (memory address register) MBR (memory buffer register) or MDR (memory data register) Introduction 20 Code Execution Program in High-level language (C, Pascal, etc) Compile program into assembly language Link multiple machine-language programs to one program Load program into computer’s memory Assemble program to machine language Execute program CS1104-P2-1 Introduction 21 Code Execution (2) Instruction execution cycle: fetch, decode, execute. Fetch: fetch next instruction (using PC) from memory into IR. Decode: decode the instruction. Execute: execute instruction. Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next CS1104-P2-1 Introduction Instruction 22 Memory Memory stores programs and data. Definitions: 1 byte = 8 bits 1 word: in multiple of bytes; a unit of transfer Desirable properties: fast access, large between main memory and registers, usually size of register. 1 KB (kilo-bytes) = 210 bytes; 1 MB (mega-bytes) = 220 bytes; 1 GB (giga-bytes) = 230 bytes; 1TB (tera-bytes) = 240 bytes. capacity, economical cost, non-volatile. However, most memory devices do not possess all these properties. Introduction 23 CS1104-P2-1 Memory (2) Memory hierarchy: Fast, expensive (small numbers), volatile registers main memory disk storage magnetic tapes Slow, cheap (large numbers), non-volatile CS1104-P2-1 Introduction 24 Memory (3) Data transfer: Processor MAR n-bit data bus Up to 2k addressable locations. Address 0 1 2 3 4 5 Memory k-bit address bus MDR : Control lines (R/W, etc.) CS1104-P2-1 Introduction 25 Memory (4) A memory unit stores binary information in groups of bits called words. The data consists of n lines (for n-bit words). Data input lines provide the information to be stored (written) into the memory, while data output lines carry the information out (read) from the memory. The address consists of k lines which specify which word (among the 2k words available) to be selected for reading or writing. The control lines Read and Write (usually combined into a single control line Read/Write) specifies the direction of transfer of the data. CS1104-P2-1 Introduction 26 Memory (5) Block diagram of a memory unit: n data input lines n k address lines k Memory unit 2k words n bits per word Read/Write n n data output lines CS1104-P2-1 Introduction 27 Memory (6) The Write operation: Transfers the address of the desired word to the address lines. Transfers the data bits (the word) to be stored in memory to the data input lines. Activates the Write control line (set Read/Write to 0). The Read operation: Transfers the address of the desired word to the CS1104-P2-1 address lines. Activates the Read control line (set Read/Write to 1). Introduction 28 Memory (7) The Read/Write operation: Memory Enable Read/Write Memory Operation 0 X None 1 0 Write to selected word 1 1 Read from selected word Two types of RAM: Static and dynamic. Static RAMs use flip-flops as the memory cells. Dynamic RAMs use capacitor charges to represent data. Though simpler in circuitry, they have to be constantly refreshed. CS1104-P2-1 Introduction 29 Memory (8) A single memory cell of the static RAM has the following logic and block diagrams: Select Select R Input S Q Output Input BC Output Read/Write Read/Write Logic diagram CS1104-P2-1 Introduction Block diagram 30 Memory (9) Logic construction of a 4 x 3 RAM (with decoder and OR gates): CS1104-P2-1 Introduction 31 Memory (10) An array of RAM chips: memory chips are combined to form larger memory. A 1K x 8-bit RAM chip: RAM 1K x 8 Input data 8 Address 10 Chip select Read/write DATA (8) ADRS (10) CS RW (8) 8 Output data Block diagram of a 1K x 8 RAM chip CS1104-P2-1 Introduction 32 Memory (11) Address Lines 11 10 Lines 0–9 Input data 8 lines 0–1023 DATA (8) (8) ADRS (10) CS 1K x 8 RW 2x4 decoder S0 S1 0 1 2 3 1024 – 2047 DATA (8) (8) ADRS (10) CS 1K x 8 RW Read/write 2048 – 3071 DATA (8) (8) ADRS (10) CS 1K x 8 RW 4K x 8 RAM. CS1104-P2-1 Introduction 3072 – 4095 DATA (8) (8) ADRS (10) CS 1K x 8 RW Output data 33 Memory (12) 21-bit addresses A0 A1 19-bit internal chip address A19 A20 2-bit decoder 512K x 8 memory chip 19-bit address 8-bit data input/output 512k X 8 memory chip D31-24 D23-16 D 15-8 D7-0 Chip select Another example: Organization of a 2M 32 memory module using 512K 8 static memory chips. Introduction 34 CS1104-P2-1 End of file