CS1104 – Computer Organizationhttp://www.comp.nus.edu.sg/~cs1104 Aaron Tan Tuck Choy School of Computing National University of Singapore CS1103 Lecture 14: Introduction to Algorithmic State Machines (ASM) Large Digital Systems Top-Down Approach Controller and Data Processor Flowcharts ASM Charts Components of ASM Charts ASM Charts: An Example Register Operations Timing in ASM Charts CS1104-14 Lecture 14: Introdu 2 Lecture 14: Introduction to Algorithmic State Machines (ASM) ASM Charts => Digital System ASM Charts => Controller ASM Charts => Architecture/Data Processor Implementing the Controller With JK Flip-flops Decoder + D flip-flops One Flip-flop per State Multiplexers PLA/ROM CS1104-14 Lecture 14: Introdu 3 Large Digital Systems In both combinational and sequential circuit design: small circuits via gate-level design (truth tables, K maps, etc) large circuits via block-level design (MSI components, etc.) However, larger digital systems need more abstract and systematic design techniques. One such systematic design method has the following characteristics: top-down approach separation of controller from controlled hardware develop an overall architecture (at block levels) before proceeding into the details of hardware. CS1104-14 Large Digital Syste 4 Top-Down Approach Top-down approach is immensely important for large complex system (whether hardware, software, or manual systems). Emphasis on macroscopic view, starting from original problem and gradually refine it towards solution. Steps for a top-down design procedure: Specify the problem clearly (at global/top level without unnecessary details). Break the problem into smaller sub-problems. Repeat the process until subproblems are small enough to be solved directly (implementable). CS1104-14 Top-Down Approac 5 Top-Down Approach Corresponds to goal-directed approach. Pass CS1103 Do Tutorials Ask questions CS1104-14 Pass Tests Practice Revise Top-Down Approac Pass Exam Sleep well 6 . then find sub-goals to solve main goal. Repeat until sub-goals are directly solvable. State goal. multipliers. CS1104-14 Controller & Data P 7 . They store data through flip-flops. and process them using combinational circuits like adders. etc. registers and memory.Controller & Data Processor Digital systems are typically processors of information. These processing may pass through complicated sequences. Controller & Data Processor A digital system consists of two components A control algorithm (controller) and An architecture (data processor) Status condition Commands External command CS1104-14 Control unit (Controller) Input data Data Processor (Architecture) Controller & Data P Output data 8 . Car (data processor): transports people from one location to another.Controller & Data Processor Separation of the controller operations from the data processing operations Control operations give commands that direct the data processing operations to accomplish the desired tasks. Data processing operations manupulates the data according to requirements. A mechanical analogy: Automobile. Driver (controller): gives instructions to car to achieve objective. CS1104-14 Controller & Data P 9 . Main symbols: Operation box: contains tasks/operations to perform. Decision box: alternative actions based on decisions to be taken. Specify tasks to perform and their sequencing. Arrows: indicate appropriate sequencing.Flowcharts Flowcharts: a tool for precise description of algorithms/procedures. CS1104-14 Flowcharts 10 . and is used to specify one or more subtasks to be performed. Sub-task or operation to perform CS1104-14 Flowcharts 11 .Flowcharts An operation box is rectangular in shape. It has at most one entry point and one exit point. Flowcharts A decision box is diamond-shaped. It has one entry point and multiple (but mutually exclusive) exit points. choice option A CS1104-14 option B option C Flowcharts 12 . Lines without arrows are sometimes used. the default flow direction is top-to-bottom and left-to-right.Flowcharts Sequential flow: simplest type of sequencing. tasks are done in sequential order. Drink soup Main course Eat dessert Boxes are connected by lines with arrows. In the absence of arrows. An example: Eating a 3-course Western meal. CS1104-14 Flowcharts 13 . Decision box is used to determine when to terminate the loop. This is achieved through the loop-back in the flowchart. CS1104-14 Flowcharts 14 .Flowcharts Iteration: some tasks/operations may be repeatedly/iteratively done. Flowcharts An example: Eating a Western meal in oriental style. Drink soup Main course no enough? yes Eat dessert CS1104-14 Flowcharts 15 . Flowcharts Flowcharts can be used to implement complex decisions. nice colour & style? no yes affordable? no yes made in Europe? no poor insulting yes test out fitting? acceptable BF’s opinion? encouraging reject CS1104-14 Flowcharts get BF to buy 16 . ASM Charts Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems. flowcharts impose a relative timing order for the operations. Major differences from flowcharts are: uses 3 types of boxes: state box (similar to operation box). decision box and conditional box contains exact (or precise) timing information. From the ASM chart it is possible to obtain the control the architecture (data processor) CS1104-14 ASM Charts 17 . Components of ASM Charts The state box is rectangular in shape. It has at most one entry point and one exit point and is used to specify one or more operations which could be simultaneously completed in one clock cycle. state binary code one or more operations CS1104-14 Components of ASM 18 . It has one entry point but multiple exit points and is used to specify a number of alternative paths that can be followed. deciding factors CS1104-14 deciding factors Components of ASM 19 .Components of ASM Charts The decision box is diamond in shape. Components of ASM Charts The conditional box is represented by a rectangle with rounded corners. conditional operations CS1104-14 Components of ASM 20 . It always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box. Ai stands for ith bit of the A register. 0 A 0 F 0 A A+ 1 1 A2 E 0 E 1 0 A3 T2 1 F 1 CS1104-14 ASM Charts: An Ex 21 . S 1 A = A4A3A2A1 T1 E and F are singlebit flip-flops.ASM Charts: An Example An example: T0 Initial state 0 A is a register. Register Operations Registers are present in the data processor for storing and processing data. The register operations are specified in either the state and/or conditional boxes. and are written in the form: destination register function(other registers) where the LHS contains a destination register (or part of one) and the RHS is some function over one or more of the available registers. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers. CS1104-14 Register Operations 22 . Register Operations Examples of register operations: AB A0 AA 1 CS1104-14 Transfer contents of register B into register A. Decrement register A by 1. Register Operations 23 . Clear register A. Each state box.Timing in ASM Charts Precise timing is implicitly present in ASM charts. occurs within one clock cycle. CS1104-14 Timing in ASM Char 24 . together with its immediately following decision and conditional boxes. A group of boxes which occur within a single clock cycle is called an ASM block. Timing in ASM Charts T0 Initial state 0 S 1 T1 A 0 F 0 A A+ 1 0 3 ASM blocks 1 A2 E 0 E 1 0 A3 T2 1 F 1 CS1104-14 Timing in ASM Char 25 . Two factors which must be considered are operations in an ASM block occur at the same time in one clock cycle decision boxes are dependent on the status of the previous clock cycle (that is.Timing in ASM Charts Operations of ASM can be illustrated through a timing diagram. they do not depend on operations of current block) CS1104-14 Timing in ASM Char 26 . Timing in ASM Charts clock 1 2 3 4 5 6 7 8 9 10 11 12 13 states T0 T0 T1 T1 T1 T1 T1 T1 T1 T2 T0 T0 input S=0 S=1 A=2 A=3 A=4 register values Operations T0 S=0 A=0 F=0 A=1 A=7 F=1 E=0 A0 F0 A=5 A=6 E=0 AA+1 E0 AA+1 E0 E=1 E=1 AA+1 E1 AA+1 E1 E=0 E=0 E=1 AA+1 E0 AA+1 E0 F1 AA+1 E1 A = A4A3A2A1 CS1104-14 Timing in ASM Char 27 . Timing in ASM Charts T0 Initial state 0 clock 1 2 3 4 5 6 states T0 T0 T1 T1 T1 T1 input S=0 S=1 A=1 A=2 A=3 E=0 E=0 E=1 register values S S=0 A=0 F=0 1 T1 A 0 F 0 A0 F0 Operations A A+ 1 0 1 A2 E 0 T2 0 1 F 1 A = A4A3A2A1 CS1104-14 clock 7 8 9 10 11 12 13 states T1 T1 T1 T2 T0 T0 T0 input E 1 A3 AA+1 AA+1 E0 E1 AA+1 AA+1 E0 E1 register values A=4 A=5 A=6 A=7 E=1 E=0 E=1 F=1 E=0 AA+1 F1 E0 AA+1 AA+1 E0 E1 Operations Timing in ASM Char 28 . ASM Chart => Digital System ASM chart describes a digital system. CS1104-14 ASM Chart => Digit 29 . we may obtain: Controller logic (via State Table/Diagram) Architecture/Data Processor Design of controller is determined from the decision boxes and the required state transitions. Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes. From ASM chart. ASM Chart => Controller Procedure: Step 1: Identify all states and assign suitable codes. Step 3: Formulate state table using State from state boxes Inputs from decision boxes Outputs from operations of state/conditional boxes. Step 2: Draw state diagram. Step 4: Obtain state/output equations and draw circuit. CS1104-14 ASM Chart => Contr 30 . ASM Chart => Contr 31 .ASM Chart => Controller T0 0 S T2 A 0 F 0 Present state G1 G0 A A+ 1 0 T0 = 00 T1 = 01 T2 = 11 T1 1 T1 Assign codes to states: T0 Initial state 1 A2 E 0 E 1 0 A3 T2 1 F 1 CS1104-14 0 0 0 0 0 1 0 0 1 1 1 1 Next state inputs outputs S A2 A3 G1+ G0+ T0 T1 T2 0 1 X X X X X X 0 1 1 X X X X 0 1 X 0 0 0 0 1 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 Inputs from conditions in decision boxes. Outputs = present state of controller. Guidelines: always use high-level units simplest architecture possible. In particular. CS1104-14 ASM Chart => Archi 32 .ASM Chart => Architecture/Data Processor Architecture is more difficult to design than controller. it can be deduced from the ASM chart. the operations from the ASM chart determine: What registers to use How they can be connected What operations to support How these operations are activated. Nevertheless. F is set (F 1) when state = T2.ASM Chart => Architecture/Data Processor Various operations are: Counter incremented (A A + 1) when state = T1. E is cleared (E 0) when state = T1 and A2 = 0.g. CS1104-14 ASM Chart => Archi 33 . Two flip-flops needed for E and F (e.: JK flip-flops). Deduce: One 4-bit register A (e. E is set (E 1) when state = T1 and A2 = 1.: 4-bit synchronous counter with clear/increment). Counter cleared (A 0) when state = T0 and S = 1.g. (E 1) when state = T1 and A2 = 1.ASM Chart => Architecture/Data Processor S A3 start (A A + 1) when state = T1. (A 0) when state = T0 and S = 1. counter A CS1104-14 A1 K count CP clear clock ASM Chart => Archi 34 . T0 Controller T1 Clk A2 T2 J Q E Q F K J A4 A3 A2 4-bit syn. Decoder + D flip-flops suitable for moderately large controllers. the controller can be implemented using one of these techniques. use K-maps to obtain next- state/output functions.Implementing the Controller Once the state table is obtained. CS1104-14 Implementing the Co 35 . 1. obtain the next-state functions by inspection. Traditional method: With JK flip-flops. from the state table. procedure: prepare state table. 2. design done at gate level. suitable for small controllers. procedure: use decoder to obtain individual states. Multiplexers a more structured approach to implement controller. second level is a register that holds the present state. suitable for moderately large controllers. third level has a decoder to provide separate output for each controller state. CS1104-14 Implementing the Co 36 . three level structure: first level consists of multiplexers that determine the next state of the register.Implementing the Controller 3. from state table. must ensure that controller is properly initialised. PLA can handle don’t care states well but design method is still at gate-level. determine the formulae to set each flip-flop. CS1104-14 Implementing the Co 37 . 5. procedure: allocate one flip-flop per state. ROM approach uses a very simple table lookup technique but suffers from large number of don’t care states. PLA/ROM highly regular approach.Implementing the Controller 4. One flip-flop per state also known as One-Hot Spot Method of ASM synthesis. Implementing Controller: With JK Flip-flops State table obtained from ASM chart: Present state G1 G0 0 0 0 0 0 1 0 1 0 1 1 1 inputs S 0 1 X X X X A2 X X 0 1 1 X A3 X X X 0 1 X Next state G1+ G0+ 0 0 0 1 0 1 0 1 1 1 0 0 outputs T0 1 1 0 0 0 0 T1 0 0 1 1 1 0 T2 0 0 0 0 0 1 Corresponding state table using JK flip-flops: Present state G1 G0 0 0 0 0 0 1 0 1 0 1 1 1 CS1104-14 inputs S A2 0 X 1 X X 0 X 1 X 1 X X Next state Flip-flop inputs A3 G1+ G0+ JG1 KG1 JG0 KG0 X 0 0 0 X 0 X X 0 1 0 X 1 X X 0 1 0 X X 0 0 0 1 0 X X 0 1 1 1 1 X X 0 X 0 0 X 1 X 1 Implementing Control 38 . Implementing Controller: Decoder + D Flip-flops The flip-flop input functions can be obtained directly from the state table by inspection. ? G1 D Q D Q ? G0 2x4 decoder T0 T1 unused T2 clock CS1104-14 Implementing Contro 39 . Decoder is then used to provide signals to represent different states. the next state = flip-flop D input. This is because for the D flip-flops. DG1 = T1.A3 DG0 = T0.A2.Implementing Controller: Decoder + D Flip-flops Given the state table: Present state G1 G0 0 0 0 0 0 1 0 0 1 1 1 1 Next state inputs outputs S A2 A3 G1+ G0+ T0 T1 T2 0 1 X X X X X X 0 1 1 X X X X 0 1 X 0 0 0 0 1 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 We can directly determine the inputs of the D flip-flops for G1 and G0.S + T1 CS1104-14 Implementing Contro 40 . Implementing Controller: Decoder + D Flip-flops Flip-flop input functions: DG1 = T1.A3 DG0 = T0.S + T1 Circuit: A2 A3 G1 D Q D Q S G0 2x4 decoder T0 T1 unused T2 clock CS1104-14 Implementing Contro 41 .A2. ) ? D Q T0 ? D Q T1 : : clock CS1104-14 Implementing Control 42 . (Other methods: n flip-flops for up to 2n states. each flip-flop represents one state.Implementing Controller: One Flip-flop per State Require n flip-flops for n states. then formula = input condition ANDed with the previous state. 2. If there is only one line going into the state.Implementing Controller: One Flip-flop per State Formulae for next state can be obtained directly from state table: 1. If there are more than one line. then formula = Ored of all the conditions found in (1). CS1104-14 Implementing Control 43 . T0 + A2'.A3. A3=0 A2=1.T0 + (A2.T1 DT2 = A2.T0 DT1 = S.A3)'.A3'.T1 + A2.T1 = S.T1 CS1104-14 Implementing Control 44 .Implementing Controller: One Flip-flop per State State table: Present state Next state inputs S A2 A3 T0 T0 T1 T1 T1 T2 0 1 X X X X X X 0 1 1 X X X X 0 1 X State diagram: S=0 A2=0 S=1 T0 T1 T1 T1 T2 T0 T0 T1 T2 A2=1. A3=1 Flip-flop input functions: DT0 = T2 + S'. preset S A2 A3 DT0 = T2 + S'.T1 CS1104-14 D Q T0 D Q T1 D Q T2 clock clear Implementing Control 45 .T0 DT1 = S.T1 DT2 = A2.A3)'.A3.T0 + (A2. set flip-flop of T0 to 1 and clear the rest to zero. To initialise to state T0.Implementing Controller: One Flip-flop per State Circuit diagram below. D Q S Q' A2 A3 DT0 = (T2 + S'. To initialise.T1 CS1104-14 T0 D Q T1 D Q T2 clock clear Implementing Control 46 .A3.T0 + (A2.T1 DT2 = A2.T0)' DT1 = S. and input function for T0 is complemented.Implementing Controller: One Flip-flop per State Alternative: Use Q' output for T0.A3)'. clear all flip-flops to zero. The inputs of multiplexers are determined from the decision boxes and state transitions in the ASM chart.Implementing Controller:Multiplexers Purpose of multiplexer is to produce an input to its corresponding flip-flop equals to the value of the next state. CS1104-14 Implementing Control 47 . A3 1 Implementing Control Multiplexer inputs MUX1 MUX0 ? ? ? ? ? ? 48 . Reformat the state table.Implementing Controller:Multiplexers Example 1: Given the state table. A3' A2. CS1104-14 Present state G1 G0 0 0 0 0 0 1 0 1 0 1 1 1 Present state inputs S 0 1 X X X X Next state G1 G0 G1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 + Next state A2 A3 G1+ G0+ X X 0 0 X X 0 1 0 X 0 1 1 0 0 1 1 1 1 1 X X 0 0 G0+ Input conditions 0 1 1 1 1 0 S' S A2' A2. A3' + A2.Implementing Controller:Multiplexers Obtain multiplexer inputs: Present state Next state G1 G0 G1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 CS1104-14 + G0 0 1 1 1 1 0 + Input conditions S' S A2' A2. A3 1 Multiplexer inputs MUX1 MUX0 0 S A2. A3 A2' + A2. A3 =1 0 0 Implementing Control 49 . A3' A2. A3 0 MUX0 S 1 0 G1 2x4 decoder S 1 Multiplexer inputs G0 T0 T1 T2 clock Hold present state Implementing Control 50 .Implementing Controller:Multiplexers Present state Draw circuit: T0 T1 T2 A2 A3 0 0 0 1 MUX1 2 3 S1 S0 D Q G1 G0 0 0 0 1 1 1 0 S1 S0 0 1 MUX0 2 3 Determine next state of register CS1104-14 D Q MUX1 0 A2. z' + y.z =y 1 1 y + y'.z' Multiplexer inputs G1 G0 MUX1 MUX0 0 0 0 w 0 1 x+x'=1 x' 1 0 y.Implementing Controller:Multiplexers Present state Example 2: T0 T1 0 T3 0 0 z 0 w 1 01 1 11 y T2 1 1 CS1104-14 G1 G0 G1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 00 x 1 1 z Next state Present state 10 y 0 0 T0 T1 T2 T3 + G0 0 1 0 1 0 0 1 1 0 1 + Input conditions w' w x x' y' y.z' y'.z y'.z' = y' Implementing Control 51 .z + = y + z' y'.z y.z y y'.z' y. z y' G1 2x4 decoder y z CS1104-14 w x' y' S1 S0 0 1 MUX0 2 3 D Q G0 T0 T1 T2 T3 clock Implementing Control 52 .Implementing Controller:Multiplexers Present state T0 T1 T2 T3 y z' 0 1 y G1 G0 0 0 0 1 1 0 1 1 Multiplexer inputs MUX1 0 1 y y + z' 0 1 MUX1 2 3 S1 S0 D Q MUX0 w x' y. External command Commands to architecture PLA/ROM Present state Next state Register to represent states CS1104-14 Implementing Contr 53 .Implementing Controller: PLA/ROM Similar to the design using D flip-flops and a decoder. The only difference is PLA essentially replaces the decoder and all the gates in the inputs of the flipflops. End of segment CS1103 .