Class D amp

Project Number: JKM-2A03Class-D Audio Amplifier A Major Qualifying Report: submitted to the Faculty of the WORCESTER POLYTECHNIC INSTITUTE in partial fulfillment of the requirements for the Degree of Bachelor of Science by ______________________________________________ Alex C. DiDonato ______________________________________________ Ryan T. Dupuis ______________________________________________ Tyler W. Folsom Date: April 29, 2004 Approved: __________________________________________ __________________________________________ Professor John McNeill Professor Demetrios Papageorgiou Project Advisor Project Advisor 1 ABSTRACT This MQP involved the design, construction, and testing of an Ultra-Efficient, High-Powered, Class-D audio amplifier. The main goal was to achieve 95% efficiency using the 42 Volt PowerNet Standard. The signal processing stage was completed using a three-level Sigma-Delta Modulation scheme which powered a MOSFET H-Bridge configuration. Testing confirmed that the goal of 95% efficiency was met, and an RMS power of 400 Watts was produced using a 42 Volt supply. 2 Acknowledgements We would first like to thank Analog Devices, Texas Instruments, and Allegro Microsystems for sponsoring the Analog MQP lab. Without their continued support, the resources needed to fund this project would not have been available. We would also like to thank all the companies that were willing to donate free samples for us to perform testing in lab. These companies included Fairchild Semiconductor, Texas Instruments, Intersil, and Analog Devices. A huge thank you goes out to Tom Angelotti for all his patience and willingness to help us when we needed anything from the shop. The most thanks goes out to our MQP advisors Professor McNeill and Professor Papageorgiou for all their guidance and support throughout the year. Without their willingness to always bestow their knowledge and help when in dire need, our MQP would not have been a success. 3 ...............................................................................................................................4 2...............................................................35 CONTROLS THEORY........................................................................................................................................... 2 ACKNOWLEDGEMENTS .........................................................................43 POWER STAGE .................3 4..............................................................................76 SIGNAL TO NOISE RATIO .....50 FILTER ......................15 2......................................................................................................................4 3.......................... 62 TESTING AND RESULTS .....................3....................................................................................................................................4 5............................67 EFFICIENCY TESTING ............................ 68 RECOMMENDATIONS......................28 Filtering ...........................................................75 OUTPUT POWER........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... 10 2.....................5 5.........................................1 4....................................................................................................28 Electromagnetic Interference (EMI) .......................................................................39 TEST MEASUREMENT METHODOLOGY ...........................................................................2 5............................................................................................................. 91 APPENDIX ................ 19 2...............................................................................................................................3 Digital Signal Processing .......................................3 2..........12 2..............18 2.............................................................................................................................. 7 1 2 INTRODUCTION........................................................................................................................................................................................4 5 5............................62 SECOND PCB.....................................................................................1 2............TABLE OF CONTENTS ABSTRACT .......................................................... 88 CONCLUSIONS ........................................................................1 S/PDIF ......................................................5 3.............2 METHODS OF ACHIEVING CLASS-D.......................................................................................................................................................................................................................................................80 DESIGN ...................................................................32 EFFICIENCY ................................2................................................10 2...............................................................................................................................................................................................41 SIGMA DELTA MODULATION......................................................................................3 5........................................................ 3 TABLE OF FIGURES ................................8 3 3........6 6 7 8 POWERNET 42V STANDARD .......71 ACOUSTIC CLARITY...................................................1 3................................................................................65 FOURTH PCB.......................................................................................................................................................................................................................................................................................................................................................................................2 Sigma-Delta Modulation..........................................................................................................................................................................................................57 PRINTED CIRCUIT BOARD ...................................................2 2.................................. 9 BACKGROUND ......................................5..............................................................................1 5..........................6 2......................................................................................................................................... 43 PROJECT EVOLUTION...........................................22 POWER MOSFETS ..................12 2............................................. 92 4 ...................................................................................................................................................................................53 HEAT SINK ....................................................1 WHAT IS CLASS-D..............................2 4...........................................................................................................................................................................................................2 3...............................................................................................................................................................78 EFFICIENCY LOSS ..........................................................................................................2.................................................................7 2..5 2..................5..............................59 FIRST PCB.......................................6 4 4.....................................................................................................................1 Pulse Width Modulation ...................68 “DEAD-ZONE”.... 5 EXECUTIVE SUMMARY .....63 THIRD PCB.....................2..........................................3 3............ 90 REFERENCES......................................................................................................................................................................................................................................................................................................................................................................48 SYSTEM STABILITY ...........................................................25 POTENTIAL CONCERNS ..2.......................................................................................................................................... .......................................................... 38 Figure 27: Block Diagram ..................................................................................................... 41 Figure 30: Basic Sigma-Delta Modulation ............................................................................................................................................................................................. 45 Figure 34: Quantizers........................................................................................................................................... 47 Figure 36: Feedback Attenuation........................................................... 33 Figure 24: Basic level circuit model ..................................... 33 Figure 23: EMI Interference ............. 40 Figure 28: Duty Cycle........................................................................................................... 31 Figure 20: Bode Plot for 4 Ohm Load ..................................................................................................................................................................................................................................... 47 Figure 35: Three-Level Switching .......................................................................................................................................................................................................................................................................................................... 52 Figure 40: H-Bridge Filter Configuration........................................................... 44 Figure 32: Three-Level Sigma-Delta Modulation .................................................................................................................................. 49 Figure 38: Graphical Bode Plot Method... 52 Figure 39: Bode Plot .......... Three-Level PWM .................................................................................................................................................. 16 Figure 9: Block Diagram of Sigma-Delta (Σ-∆) Modulation ................................................ 21 Figure 12: Maximum Over-voltage ........................................................... 13 Figure 6: Two-Level vs................................................................................................................. 31 Figure 21: Bode Plot for 8 Ohm Load ............... 44 Figure 33: Integrator .. 41 Figure 29: Testing Diagram ............................. 11 Figure 4: Switch Closed................................................................................................................................................................................................................................................................................................................... 25 Figure 15: H-Bridge............ 56 Figure 43: H-Bridge Filter Configuration............................ 30 Figure 18: Bode Plot for 1 Ohm Load ...................................................................................................................................................................................................................................................................... 14 Figure 7: PWM Comparator ....................... 11 Figure 3: Switch Open ........................................ 36 Figure 25: Current paths through the H-bridge........................................................................................................................................................................................... 48 Figure 37: Three possible MOSFET configurations......................... 27 Figure 16: Typical Low-Pass Filter ............................................ 43 Figure 31: Noise Spectrum ............................................. 17 Figure 10: DSP Block Diagram .............................................................................................................................. 11 Figure 5: Input Sine Wave vs......................................................... 29 Figure 17: H-Bridge Output Low-Pass Filter ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... 15 Figure 8: Delta Modulation and Demodulation ................................................................... 58 5 ................... 10 Figure 2: Class-D explanation with resistor added to reduce brightness............................................................ PWM Output.................. 55 Figure 42: H-Bridge Filter Design Configuration ....................................... 30 Figure 19: Bode Plot for 2 Ohm Load ......Table of Figures Figure 1: Class-D explanation without modulation or brightness reduction ............................................ 23 Figure 13: Maximum Dynamic Voltage ................................................. 54 Figure 41: H-Bridge Filter Half Representation ............................................................................................................................................................................... 37 Figure 26: MOSFET Switching Losses ............................ 57 Figure 44: Heat sink used for testing .............................. 24 Figure 14: Starting Voltage.... 31 Figure 22: Braided Speaker Wire Example ............................................................................................................................................. 19 Figure 11: Biphase-Mark-Code Example ...... ..........................................................................................................01uF Capacitor Impedance ................................................................................................................................ 58 Figure 46: Placement of MOSFETs for Heat Sink ...................................................................................................................................................... 65 Figure 51: Third PCB Ground Plane (Top) ....Figure 45: Heat sink shown with supports............................................... 65 Figure 50: Second PCB 42V Power Plane (Bottom) .................................................................. 63 Figure 49: Second PCB Ground Plane (Top) ......................................................... 72 Figure 57: Vdz = 7.......... 86 6 .......... Dissipation Factor ............................... 66 Figure 52: Third PCB 42V Power Plane (Bottom).......................................................................................... f = 1kHz ................................................................................................................. 60 Figure 47: Two Separate Sections of Board Layout................... Clock Speed ..................................................................... 10kHz ...... 85 Figure 70: Efficiency vs............................................................... 69 Figure 55: Efficiency vs....................................................................................................................................................................................................................................................................... 75 Figure 62: Speaker Test ............. 77 Figure 64: FFT used to obtain SNR............ f = 10kHz ......................................................................................................................................................................................5mV (Too Small).............................. 61 Figure 48: Original PCB ................... 84 Figure 69: Efficiency vs...................... 76 Figure 63: Input vs......................................... Ideal 0................................................ Switching Frequency.. 70 Figure 56: Ideal Integrator Output .................................. Switching Speed....................... 1kHz ...... 74 Figure 60: Vdz = 50mV (Near-Ideal Value)....................................................................................................... 74 Figure 59: Vdz = 150mV (Too Large)............................................... 67 Figure 54: Oscilloscope Snapshot.................................................. Output........................ 79 Figure 65: Power Loss ............................................................................................................................... 84 Figure 68: Power Loss vs.............. 75 Figure 61: Vdz = 50mV (Near-Ideal Value)...................... Clock Speed ................................................................................................................................................................. 83 Figure 67: Power Loss vs............................................... 73 Figure 58: Vdz = 150mV (Too Large)................ 81 Figure 66: Actual vs.............................................................. 66 Figure 53: Third PCB Fully Populated ....................................... f = 1kHz ............................................................................................................... this project meant more than just exceeding the goals of previous MQP groups that have tackled similar projects. In order to achieve a three-level modulation scheme. After an immense amount of research. We also discovered that the MOSFET selection and the filter components would be a critical choice in our amplifier design. This project. For us. After an extensive study. there would be four signals controlling the output.000 Watts of power requiring the evolution of the 42 Volt PowerNet Standard. Sigma-Delta Modulation. It is because of projects like this. Also researched were electrical systems that would be incorporated into future automobiles that would ultimately revolutionize the design of Class-D amplifiers. The MQP was a wonderful hands-on experience that one can only achieve by participating in a project of this nature. such as how to implement the signal processing of the amplifier. This makes it extremely important to find components with a minimal DC on resistance to minimize voltage drops across these elements. Instead of having one signal to control the output. sponsored by Analog Device. The reason that it is able to do so is because with a three-level signal. The time invested and the struggles that we overcame left us with a sense of self-satisfaction and a broader knowledge that can be used in future endeavors. Texas Instruments. Sigma-Delta Modulation was decided upon to carry out the signal processing due to various advantages it brought to the design. it was necessary to alter the typical scheme of Sigma-Delta Modulation. which covered Pulse-Width Modulation. The current that passes through the load passes through the MOSFETs and the inductors of the filter as well.Executive Summary Completing a project in the Analog Lab at WPI involves an enormous amount of growth. These signals are the cornerstone for the three-level modulation. The reason that three-level was chosen over two-level was to maximize efficiency. and Allegro was to design a Class-D Audio Amplifier with an efficiency of at least 90%. maturity and perseverance. These new concepts ultimately changed the goal of the project to design a Class-D amplifier capable of 95% efficiency. This project would therefore be designed around the new standard allowing for greater power potential. Many topics were researched. It meant exploring a larger scope of what could and will be done with Class-D design in the near future. you have the ability to control the load with either a 7 . more research was spent investigating the leading causes of power loss in Class-D amplifiers. that WPI is such a highly touted academic institution. Future luxury cars are predicted to consume 5. With such a small window for power loss. and Digital Signal Processing. we decided to implement a three-level modulation scheme that would allow for better efficiency than a twolevel design. During the positive state. This produced a power to size ratio greater than many other amplifiers found on the market today. Instead. The driver chip could also drive the MOSFET gates with up to 1 Amp of current. both terminals across the load are grounded. The design of the printed circuit board was done in a program called Ultiboard 2001. during the negative state. With the completion of our project. In our filter design. we ordered a printed circuit board to limit the inductive and capacitive effects found in typical breadboards. current is drawn through the load in one direction. a negative state. causing any residual current to exit through the ground plane. we like to think that we are paving the way for future designs of Class-D amplifiers utilizing the 42 Volt PowerNet Standard. This is the configuration used in most Class-D amplifiers on the market. The low-pass filter was necessary to reduce the amount of electromagnetic interference that would radiate out of the amplifier without it. we used a driver chip to drive the MOSFETs. We did this because it had built in logic protection preventing a short from the power plane to ground. current is not required to flow from the supply.positive state. In the end. This would allow the MOSFETs to turn on and off faster than without the use of a driver chip. The output power of the final product met its goal of being high powered with a measured output of 400 Watts RMS. The total footprint size of the amplifier measured to be only 29 square inches. The filter was created with two separate cut-off frequencies at both 14 kHz and 37 kHz. It was also necessary to transform the digital logic stream back into an analog signal that more closely represents the input signal. we were happy to report that the amplifier we designed and built was a success. This last block was the filter. The reasoning behind separating the poles was to maintain stability throughout the amplifier. the signal had to pass through one more block before it could reach the load. When the design of the amplifier had taken shape and was ready to be tested. we used an inductor and a capacitor to create a low-pass filter. or a neutral state. The efficiency goal of the amplifier was also met reaching 95% efficiency with a fully clipped input signal. 8 . and during the neutral state. The configuration that we used for the MOSFETs was a standard H-Bridge. To add more safety into the design. These faster switching speeds would result in greater efficiency. current is drawn through the load in the opposite direction. This program gave us the freedom to design the board in any matter that we saw fit. The end result was a professional looking populated printed circuit board that avoided the side effects of a breadboard. After the MOSFET stage of our amplifier. Unlike present amplifiers on the market. car-audio amplifier with an efficiency of at least 95%. and lower cost. Instead. they typically are used as subwoofer amplifiers. The goal of this project is to create a Class-D. Sigma-Delta Modulation will be used to drive the MOSFET switching stage by means of discrete components. This combination would provide an amplifier that is smaller in size with higher efficiency. an amplifier with both the advantages of the Class-AB and Class-D amplifiers combined. Similar to all Class-AB amplifiers. this amplifier will have a goal of running full audible bandwidth (20 to 20 kHz).1 Introduction Currently there are many Class-D amplifiers on the market for car audio applications. Imagine now. The overall scheme of the project will be to foresee the future of car audio amplifiers assuming the adoption of the new 42 Volt PowerNet standard. very low distortion. this Class-D amplifier will not use Pulse-Width Modulation (PWM). 9 . The method of creating a Sigma-Delta modulated signal ensures a high level of efficiency which utilizes feedback to create a clean output signal. The footprint size of the amplifier will be reduced dramatically due to the fact that the power supply of the amplifier will be eliminated from the design. and are generally lower quality than conventional Class-A or ClassAB amplifiers. This allows the amplifier to produce the same amount of power as other Class-D amplifiers with twice the footprint size. The conventional Class-D amplifier has several drawbacks: most have only 85% efficiency. 1 What is Class-D Before this report goes into detail on how to construct a Class-D amplifier. This would decrease the voltage across the light bulb. it is important to discuss the theory behind a Class-D amplifier. the current through this bulb equals 12 Amps. This can bee seen in Figure 2. Since this bulb has a resistance of 1Ω. Figure 1: Class-D explanation without modulation or brightness reduction Now if it was determined that this particular light bulb was running much brighter than intended. The subsequent topics include relevant information on the PowerNet 42 Volt Standard. we’ll add a resistor to the circuit of the same resistance. P = V ∗ I . 2. The simplest solution to fix this problem would be to implement a resistor in series with the light bulb. Power MOSFETs. resulting in less current flow through it. and Controls Theory. Also by using the power formula. we have a 12 Volt battery connected to nothing but a light bulb. Filtering. The topics include a brief overview of what Class-D really is and methods of creating a Class-D amplifier. 1Ω. 10 . we would need to decrease the power that the light bulb dissipates. it can be found that the power dissipated by the light bulb is 144 Watts. using the formula V = I ∗ R . For simplicity of explanation.2 Background This section is included to provide the necessary background information and design concepts to build a Class-D amplifier. One way to explain and show the relevance of a Class-D amplifier is to start a discussion about the simple circuit shown in Figure 1. Efficiency. Here. What this means is that there is now only 6 Amps running through the bulb. Energy is 11 . the controlling switch would have to be switched very rapidly between “off” and “on. Figure 3: Switch Open Figure 4: Switch Closed Notice that when the switch is in the open position. the brightness. and in effect. which reduces the power the light bulb dissipates. In order for the light bulb to be dimmer than it was originally. we see that the voltage across the light bulb has dropped from the full 12 Volts down to 6 Volts. the bulb appears to remain on for the entire duration. illuminated at approximately half of its full capable brightness. Please take a look at Figure 3 & Figure 4 below. However. The problem however is that the resistor is also consuming 36 Watts of power.Figure 2: Class-D explanation with resistor added to reduce brightness Notice that now when we calculate the current. when the switch is in the closed position the current is back to the original 12 Amps resulting in the light bulb being on again. It turns out that adding a switch to the circuit instead of a resistor achieves this goal. Now this light bulb is emitting 36 Watts of power instead of the original 144 Watts which is what we wanted. If only there was a way to decrease the power consumption of the light bulb to reduce the brightness while conserving energy at the same time. which is being released in the form of heat. but still remain on for the entire duration.” If this happens. there is no current flowing through the light bulb. resulting in the light bulb being off. which is detrimental to achieving high efficiency. Those three methods that we investigated were Pulse Width Modulation. Sigma-Delta Modulation. If we calculate the power of these three circuits. In this circuit there is no wasted energy as there was in the resistor circuit. This is running at 100% efficiency. Assuming the switch is lossless. but at the full 12 Amps of current. This example briefly explains and shows the relevance behind a Class-D amplifier. comparing both advantages and disadvantages of each scheme.2. 2. an efficiency of 100% would be reached. which was our goal. Instead of an amplifier using a sine wave throughout its amplification process. we focused on three different methods that were studied and analyzed to determine which method we thought would be most appropriate for our project. The 36 Watts of power dissipated by the resistor. it uses a series of square waves in which the duty 12 . 2. In this circuit we have 50% efficiency since the light bulb gets only 50% of the total power in the circuit.2 Methods of Achieving Class-D While there are many possible ways of designing a Class-D amplifier. Again we see the potential for 100% efficiency in this circuit while the bulb is running at 50% brightness. This leads into a few possible techniques to control the switching of various devices. in the form of heat.1 Pulse Width Modulation PWM is what makes a Class-D amplifier digital. or at least quasi-digital. and Digital Signal Processing.conserved in this situation in the respect that a resistor is not absorbing half the power. it is intuitive that by implementing switching into a circuit. there are endless possibilities to what one may control. therefore there is no power loss due to non-bulb elements. is actually wasted since it does not become dissipated by the light bulb. Even though the example has nothing to do with music or sound. In the circuit we have the resistor and the light bulb which both dissipate 36 Watts of power. but we want the light bulb to be much dimmer. In the last circuit the light bulb averaged 72 watts of power due to the fact that it received 6 Volts across it on average. we can see that in the first circuit we have 144 watts of power being dissipated by the light bulb. the pulse widths get smaller. positive. The Class-D amplifier utilizes an H-bridge to convert the PWM square-wave to an acoustic wave that ultimately drives the speakers at the output stage. Figure 6 illustrates the 13 . difference between the two PWM methods. Notice when the sinusoidal waveform reaches its peaks. Figure 5 depicts a PWM signal. Two-level PWM contains two possible output levels. and zero. the pulse width remains wider versus when the sinusoidal waveform approaches zero volts. Three-level PWM contains three possible output levels. negative. the duration of the pulses increase. As an input signal approaches its upper limits. Class-D amplifiers typically use two-level rather than three-level PWM to control the switching of the H-bridge circuit. high and low. The average of all the varying width pulses is equivalent to the original input.cycles vary according to the input signal. PWM Output The red line in Figure 5 is the input sine wave that was needed to generate the PWM signal. Figure 5: Input Sine Wave vs. The longer the audio signal’s amplitude remains larger than the reference signal’s amplitude. the terminals on the comparator circuit become switched. typically a triangle wave. The analog input goes to the inverting terminal and the reference signal goes to the non-inverting terminal. When the audio signal’s amplitude is larger than the reference signal’s amplitude the resulting PWM signal is high. This conserves energy by minimizing MOSFET switching. The three-level’s duty cycle will be zero because there is no need to draw current through the load.Figure 6: Two-Level vs. The two-level’s duty cycle will be 50% because the MOSFETs will be switching on and off equally. we must look at the input when it is zero volts. In the case when the audio signal changes polarity. the longer the PWM will remain high. To prove this. Three-Level PWM Three-level PWM is more beneficial because it increases the efficiency of the H-bridge circuit. 14 . increasing the efficiency. The comparator’s job is simply to compare the audio signal to a reference signal. the PWM signal is created by a comparator. In today’s standard Class-D amplifier. Figure 7: PWM Comparator To achieve a proper PWM signal that will represent an analog input. 15 . 1MHz and up. The analog input will be a standard 1. the reference signal amplitude must be larger than the maximum input amplitude. Another important factor of the reference signal is the operating frequency or clock speed of that waveform. The advantage of an extremely high clock speed.1 The faster the clock speed of the reference signal.2.2 For the purposes of this project. 2. the Xtant 1. a comparator will not be used to create a square wave signal in the manner just discussed.4 Volt peak. “Delta modulation is based on quantizing the change in the signal from sample to sample rather than the absolute value of the signal at each sample. As of 2003. is full audible bandwidth capabilities of the amplifier.”3 Figure 8 shows the block diagram of the delta modulator and demodulator. The operating frequency must be faster than the audio signal to assure an accurate sampling rate.2 Sigma-Delta Modulation To understand Sigma-Delta Modulation it is important to first understand how it originated. 20 to 20 kHz. A drawback is more Electromagnetic Interference (EMI) will be radiated from the circuit which will be talked about later.1i was the only Class D amplifier on the market with this capability. The SDM will be created using discrete components that accept an analog input. Before Sigma-Delta Modulation there was delta modulation. A Sigma-Delta modulated signal (SDM) will be used as opposed to a PWM signal. the closer the output will represent the input. Finally. The quantized prediction error (delta modulation output) is integrated in the receiver just as it is in the feedback loop. Granular noise occurs when the step size is too large and causes excessive quantization noise when the input changes slowly. The step size is explained in much greater detail later in the report. On the reverse end. This signifies that the integrator works as a predictor and the equation x(t ) − x(t ) is the prediction error term.Figure 8: Delta Modulation and Demodulation3 Notice how the output of the integrator in the feedback loop of Figure 8(a) tries to predict the input x(t ) . the predicted signal is smoothed out with a low-pass filter and produces the channel output. 16 . granular noise can also be a problem when implanting SDM. The prediction error term in each current prediction is quantized and is used in the subsequent prediction.3 It is important to mention that delta modulators exhibit slope-overload for rapidly rising input signals. Slope-overload happens because the output takes a long time to catch up and follow the input. delta modulators performance is dependent on the frequency of the input signal. Thus. The performance of this system is insensitive to the rate of change of the signal. The PWM signals are averaged over one switching cycle where 17 .”3 Sigma-Delta Modulation and Pulse-Width Modulation are similar and are applicable in the same topologies. Both SDM and PWM quantize the signal of interest directly. Later in this report. Both delta modulation and Sigma-Delta Modulation use a simple quantizer (comparator) but only in Sigma-Delta Modulation does this comparator encode the integral of the signal itself. Figure 9 shows the Sigma-Delta (Σ-∆) Modulator. these noise-shaping properties will be discussed in more detail and will show why Sigma-Delta Modulation is “well suited to signal processing applications such as digital audio and communications. which is why it was chosen for this project. a linear operation.Integration. The product of the encoded waveforms when filtered can be represented in both cases by the ratio of the time the signal spends in the high position to the time it spends in the low position over a given time. Figure 9: Block Diagram of Sigma-Delta (Σ-∆) Modulation3 Sigma-Delta Modulation is a smoothed out version of delta modulation. The only difference is the time the two use to modulate the signal. allows the two integrators in delta modulation to be combined into one without altering the input/output characteristics. 2. the ADSP-21161 SHARC® would be an excellent choice for the signal processing. This chip is extremely versatile and meets all of our specifications. The arrangement below shows an example of what the block diagram for the DSP chip would look like. PWM uses only one switching cycle. This results in a more spread out spectral density for SDM.SDM are averaged over several cycles. the fact that SDM has a more spread out spectral density really separates it apart from PWM. 18 . and electromagnetic interference. With first order SDM. which will have a tendency for its power spectrum to be concentrated about the switching frequency and its harmonics. These spikes can produce many drawbacks for PWM with unwanted effects such as acoustic noise. the switching frequency is “hidden” and less harmonic energy is contained at lower frequencies. Dither will help reduce the spikes and open the door for SDM. We found that an Analog Devices chip. spectral spikes will degrade the performance unless a dither is added. switching occurs at every instance of the reference signal. With PWM. Some of these specifications include an S/PDIF (Sony Philips Digital Interface) input. When comparing these two methods. the capability of controlling the level of accuracy needed to generate a Sigma-Delta Modulated signal. One case where the drawbacks of SDM exceed those of PWM is at low modulation indices. and an analog input for a controlled feedback loop. Due to the modulation strategy for SDM. 2.3 The frequency is “hidden” due to the MOSFETs not switching every cycle of the clock.3 Digital Signal Processing For this project we explored implementing a digital DSP chip as the brains of the operation. which give rise to harmonic spikes. torque ripple. In the subsequent paragraphs. and minimize the level of total harmonic distortion in the final audio signal with analog feedback. More information about the benefits of feedback can be found in the Controls Theory section of this report. due to the automobile’s power consumption and excessive charging voltage.Figure 10: DSP Block Diagram The main function of the DSP chip would be to process the audio input and create an equivalent square wave output to drive the H-bridge.”4 S/PDIF is used on DAT. “Many audiophiles and industry professionals feel that the S/PDIF protocol allows for better sound quality than TOSlink.3. and CD hardware. “The ‘red book’ describes in detail the workings of digital audio transmission. 19 . Minidisc. storage and replay within a compact disc digital audio environment. and TOSLink (Toshiba) is sent over fiber optic cable.”4 S/PDIF is sent over coaxial cable. but they are otherwise identical. is a standard that is specified in the compact disc “red book”.2. 2. The DSP chip would utilize the new S/PDIF input for signal processing and regulate both the output voltage level from fluctuating.1 S/PDIF Sony Philips Digital Interface (S\PSIF) format. a deeper understanding of the S/PDIF input will be explored. also known as TOSlink. Sampling rates and resolutions between 16 and 24 bits can be supported as well as up to 4 channels.The S/PDIF (IEC-958) is a 'consumer' version of the AES/EBU-professional interface. The next table illustrates other important details about the Standard IEC958 "Digital audio interface" from EBU (European Broadcasting Union). Table 1: AES/EBU vs. The data protocol is universal across all S/PDIF devices. S/PDIF5 There are two distinct parts that make up an S/PDIF signal: data protocol and hardware interface. Below is table that shows the differences between S/PDIF and AES/EBU. The hardware interface is what has already been mentioned and that is how to send S/PDIF data. Table 2: EBU Details Pertaining to Digital Audio Input5 20 . The length of a cell is knows as a “time slot” which is also equal to the length of a data bit. with amplitude of 500 mVolts and a frequency of almost 3 MHz.8224 Mbit/s at a 44. These are necessary points that allow signal processing to be carried out. Figure 11 shows an example of BMC. It can be easily seen that each bit of the data signal is represented by two logical states for a cell. Figure 11: Biphase-Mark-Code Example5 In the figure above. Each sample contains two 32-bit words that are transmitted which result in a bit-rate of 2. 21 .1 kHz sampling rate for CD and DAT. The signal on the digital output of any device looks like an almost perfect sine-wave. This is as far as we got with S/PDIF as we chose to use an analog input to our Sigma-Delta Modulation . the signal records a logical 1 and if there is one zero-crossing. the clock frequency is twice the bit rate.5 The S/PDIF signal is coded using the 'biphase-mark-code' (BMC). a logical 0 will be recorded. which is a kind of phasemodulation.Some key points in this table are the sampling frequencies and control information about the inputs. BMC uses two-level modulation where the logical level at the start of a bit is always inverted to the level at the end of the previous bit. What this means is that if two zero-crossings exist. 500 Watts. many systems that have been operated by mechanical or hydraulic power such as brakes.3 PowerNet 42V Standard In the very near future. The transition to a 42 Volt standard from 12 Volt is something that will occur over time. will soon be obsolete due to its inability to support the expected 5. Today’s cars rarely consume greater than 1. For instance. As soon as 2005 some luxury cars are expected to implement these electronic devices. Other electronically driven devices are expected to replace complex transmissions. and steering will be replaced by electrically driven devices. These 22 . infinitely variable cabin climate control systems.000 Watts of power for the future average-sized car. It was introduced in FAKRA (DIN Standards Committee for Road Vehicles) and VDA (Association of German Automotive Industry) in November 1996. which was adopted in the 1920s. we will see a change in the technology incorporated into all of our automobiles.2. etc. It is clearly visible that the standard 12 Volt battery. The 42 Volt system called “PowerNet” was first conceptualized in 1996 and is currently seeking standardization. valves. Companies such as DaimlerChrysler and BMW are pioneering 14/42 Volt dual voltage systems. Currently the Working Group “Standardization“(WGS) has 19 members participating including: • • • • • • • • FAKRA DaimlerChrysler BMW VW Hella Varta TÜV Automotive Süddeutschland Infineon • • • • • • • • Siemens AT AMP Valeo Bosch Delphi Sican Renault PSA.6 In 1997 both associations agreed upon its standardization and are currently working out a draft acceptable by DIN and ISO. engine power management control system processors. In the PowerNet. One of the obvious reasons is the greater potential that the 42 Volt system allows over the 12 Volt system. of 42 Volt to the vehicle’s electrical system whereas the maximum static over-voltage is to be no more than 52 Volt including ripple due to load dump protection (LDP) ± 5%. Each of the MOSFETs used in this project are able to withstand this voltage since their 23 . components such as aftermarket car stereos and other mobile electronics are not ready for this jump. The maximum dynamic voltage for the PowerNet is determined to be 58 Volts due to LDP. the generator must supply a voltage. As the 42 Volt system becomes more prevalent. Perhaps the most important factors with regards to this project are the maximum and minimum dynamic voltages. the peak static voltage is not to exceed 52 Volts given an 8 Volt (peak-to-peak) ripple riding on the effective voltage level.cars will have the ability to power both 14 Volt and 42 Volt components using two separate circuits. Figure 12: Maximum Over-voltage6 The 48 Volt effective level was determined to be the power recharging voltage of the battery. This is an important parameter when selecting semiconductors that see this unregulated power source. it can be assumed that companies producing devices such as car audio amplifiers will take advantage of this new system. Therefore. UPN. A primary concern of the 42 Volt standard is limiting the maximum allowed voltage produced by the automobile. Currently. This is shown in Figure 12. The minimum voltage in the PowerNet standard measured at the battery terminals is never to drop below 18 Volts at any point and 21 Volts at startup. including brakes and engine power management. Figure 13 shows a test waveform of the maximum overshoot voltage.breakdown limitation is at least 60 Volts. 24 . Figure 14 depicts what the voltage level may look like at the startup of the system. Often turn-on delay circuits are implemented in order to minimize current draw to the amplifier at start-up. it is not necessary for all circuits to be immediately operable. Figure 13: Maximum Dynamic Voltage6 Another issue that must be considered is the minimum start voltage of the system. then slowly increasing to a nominal 42/48 Volts. For an audio amplifier application. This is to provide full functionality of all loads which are relevant for startup and safety. first dropping to its minimum value. the 48 Volt PowerNet standard will demand compliance within a 36 to 52 Volt range. The first step in choosing output MOSFETS was figuring the appropriate breakdown voltage or Vss. Each chip is built with a particular purpose in mind. since voltage 25 . “No undesired functions shall appear when decreasing the operating voltage from max 42 Volts to 0 Volts and increasing it from 0 Volts to max 42 Volts. The job was to determine the model that would meet or exceed the demands while remaining within the project’s budget of $1000.Figure 14: Starting Voltage6 Many other factors such as slow decrease and increase of the power supply voltage have also been determined. In the future.”6 2.6 However. This was not difficult to calculate since it was known that the rail voltages would be +/-42 Volts plus any additional charging voltage. Today. the automotive 12 Volt standard requires all electronics to be able to run between the operating voltages of 8 Volts to 18 Volts. This limitation is defined.4 Power MOSFETs It was decided to use a completely discrete set of components for the output stage for this amplifier. The selection of the best MOSFET for this application is one of the most important steps in achieving peak efficiency. 1 = [ Hz ] + t fall Conduction ( DC ) Loss = VRds * I d / 2 = [Watts ] ⎡⎛ 2 Rds C. power dissipation (W).spikes are common with automotive alternators. This helped narrow the search significantly. Understanding how Sigma-Delta Modulation works. and power loss. = ⎢⎜ ⎜R ⎣⎝ Load + 2 Rds C. rise time (tr).7 Switching speeds are not a limiting factor since all MOSFET values considered were into the 5-10 MHz range. onresistance (Rds). Specifications that were decided upon were peak drain current (Id). and fall time (tf). energy loss due to switching. Derivations for each equation can be found in Appendix A. It would be difficult to compute the actual speed at which the MOSFETs are switching using SDM.L. it has been decided that a Vgs of 12 Volts will be a sufficient value based on manufacturer’s 26 . = Vds * 2 Rds 2 MaxSwitchingSpeed = t rise ⎤ ⎞ ⎤ ⎡ Vds ⎟Vds ⎥ * ⎢ ⎥/2 ⎟ RLoad + 2 Rds ⎦ ⎠ ⎦ ⎣ 2 2(RLoad + 2 Rds ) SwitchingP owerLoss (Gate − Source ) = Q g * V gs * f clk = [Watts ] 1 SwitchingPowerLoss ( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts] 2 Table 3: Table of Equations Several values remain constant throughout the calculations. gate charge (Qg).001% and a signal-to-noise ratio >110dB. Switching will be at an absolute maximum frequency of 2 MHz however this is very unlikely. This sampling rate is used in high-end processors and can produce THD at or below 0. the MOSFETs are not going to switch at every clock pulse.L. conduction loss. Table 3 below shows the equations that were used to calculate these factors. The next step was to enter all other important specifications from each chip’s datasheet onto a spreadsheet for comparison. From these values it was possible to calculate many important factors such as max switching speed. a MOSFET was chosen with no less than 60 Volts for a breakdown voltage. Also. Appendix A also shows comparison tables and charts that were used in determining which MOSFET to choose for the Hbridge of this amplifier. 1W = 98.6W Further details about efficiency calculations are given in the Efficiency section of this report. Figure 15: H-Bridge Therefore. All efficiency calculations have been considered at the predetermined load of 4Ω.14% 1750. As seen in Appendix A.14% given by the following equation. 27 .3 Watts/chip with an Rload of 1Ω. Since the H-bridge configuration allows flow of current through two chips at a time we can find the total power loss in the MOSFETs by doubling this value. Based on calculated results. this MOSFET dissipated a loss of 16. Conduction loss is the largest factor in determining efficiency for the operating frequency of 2 MHz. the ideal efficiency limited by the output MOSFETs will be 98. Efficiency = Efficiency = PLoad PTotal 1718.data in order to minimize DC on-resistance. the Fairchild FDP038AN06A0 seems to be the best MOSFET due to its low Rds and conduction loss. Rds. Filtering benefits this project in that it reduces the signal range that the speaker would have to play.2. For this project an inductor and capacitor will be used to construct the filter. Without filtering.5 Potential Concerns Before this project even began. we briefly describe the types of complications we thought each might contribute to the project.5. 2. A passive filter is able to achieve higher efficiency because it theoretically gives back all the energy that it absorbs. Energy is wasted in trying to play frequencies higher than the human ear can hear and will result in a loss of energy in the form of heat. the Sigma-Delta Modulated signal would remain digital instead of converting back to analog. the following formulas were used:8 ω 0 = 2π * f 0 2 ⎛ ⎜ ⎟ 2 ⎛ 1 ⎞⎞ 1 = ⎜ω 0 − ⎜ ⎟⎟ 2 RC ⎜ ⎝ 2RC ⎠ ⎟ ⎝ ⎠ 28 . EMI caused from high frequencies will be kept to a minimum. it was decided to use a passive filter. Additionally. Because of this fact.1 Filtering In the audio industry. the audible bandwidth range is considered to be 20 – 20 kHz. These items were filtering. and electromagnetic interference. all frequencies above 20 kHz will be filtered out. To ensure the goal of 95% efficiency. To address these issues. there were certain issues that we thought might give us trouble in later stages of the project. To determine the values for the two components. the inductor value is half. and a 1Ω load will only be able to play up to 5 kHz. A 4Ω load was chosen because it matches the typical speaker impedance.71V_rms 1000kHz 0Deg 45uH C3 1. These were based on a 4Ω load in a typical low-pass filter configuration as seen below in Figure 16. This means that a 2Ω or 1Ω load should be reserved for subwoofer applications where the cut-off frequency is not as much of an issue. This may look like the typical low-pass filter. and the capacitor value is doubled. but notice that based on the filter described above. This means that if 2 speakers are connected in series yielding an 8Ω load. our typical low-pass filter setup had to be altered slightly. This is due to the fact that there will be two of 29 . a 2Ω load will only be able to play up to 10 kHz.4 µF and the inductor value was calculated to be 45 µH. L3 V3 1V 0. the amplifier will be capable of playing up to 40 kHz rather than the cut-off frequency of 20 kHz. the capacitor value was calculated to be 1. A basic schematic of the layout and the values for the components can be seen below in Figure 17. the lower impedances generally lose their quality. the input voltage is half. the load output is half.ω 0 = 1 LC From these equations. A typical subwoofer is reserved for very low frequencies less than 500 Hz.4uF R2 4ohm Figure 16: Typical Low-Pass Filter Because a MOSFET H-bridge configuration will be used to drive the speaker in this project. Conversely. We chose this configuration because when trying to achieve high quality sound. these filters in place at the H-bridge. L1 V1 0. the model was done in this manner. Figure 18: Bode Plot for 1 Ohm Load 30 . simulations were in order.5V 0.5uH C1 2.8uF R1 2ohm Figure 17: H-Bridge Output Low-Pass Filter To ensure that the design will perform in the manner that it was designed.35V_rms 1000kHz 0Deg 22. for simplicity and ease of explanation. Figure 19: Bode Plot for 2 Ohm Load Figure 20: Bode Plot for 4 Ohm Load Figure 21: Bode Plot for 8 Ohm Load 31 . The simulations show where the cut-off frequency will be for each speaker load configuration. these same wires could receive EMI that the car might transmit. The actual -3dB point is in fact 40 kHz. The calculations were very close to the simulated results with the margin of error increasing as the impedance decreased. the voltage change is not a major issue as long as capacitively coupled currents can be returned directly to the source using electrostatic shielding. This is due to the fact that there is a slight rise in the filter response before the cut-off. Contrary to popular belief. Notice that the last figure of the 8Ω load shows a frequency of approximately 20 kHz.9 32 . the switch’s output changes across the entire power supply voltage and the loudspeaker current is re-routed through the output stage. and that is what is shown. The rise is approximately 3db. 2. Also. High changes in current value. This is why it is important to keep the speaker wires as short as possible. the EMI from one speaker wire is cancelled out by the other one. which is the main cause of electromagnetic interference. The longer they become the better the chances are that they will either receive or transmit EMI.2 Electromagnetic Interference (EMI) Electromagnetic interference is caused by rapid changes in currents. interfering with the signal that the speaker is trying to play. Another way to keep the EMI to a minimum is to use a braided speaker wire as shown in Figure 22. on the other hand. EMI becomes a problem when the speaker wires from the amplifier to the speaker act like an antennae and transmit the EMI throughout the car’s vehicle. will cause magnetic radiation. This is the main cause of electromagnetic interference in Class-D amplifiers.5. Theoretically. When the power stage transitions. A typical Class-D amplifier should be at least 3 feet away preventing the occurrence of interference. the Class-D amplifier can be detrimental to the operation of the vehicle’s central computer.10 Long speaker lines will act as an antenna to receive that high-frequency noise. An example of this is in Toyota pickup trucks when the amplifier is mounted under the seat. and also EMI shielded. there is always going to be residual high-frequency noise. Even though it can not be heard in the speaker. This interference is minor but it can also cause problems with the operation of the vehicle’s sensors. one of the goals is to create an amplifier that remains high powered. Figure 23: EMI Interference The high-frequency noise could also present a problem on the speaker lines. in this project. small in size.Figure 22: Braided Speaker Wire Example9 Another major concern is due to the high-frequency noise caused by the fast switching speeds of the MOSFETs. In a mobile environment. This residual noise can also interfere with your radio reception. However. The reason this is a problem is because the 33 . This noise is extra energy that the voice coil absorbs. the amplifier will be designed so that the user may place it wherever it is convenient without worrying about where the central computer is located. Another material to look at is steel. which is great at shielding. the heat transfer from the component to the heat-sink would be compromised due to the nylon casing that surrounds the sheilding. This poses a problem because if the EMI affects the computer of the vehicle. Currently. implementing lead as a heat sink and an effective EMI shield would greatly increase the weight of the entire amp which would not be good in a mobile environment.vehicle’s central computer is also located there. Also. EMI shielding must be implemented into the design of the amplifier. but also waste energy in the process. To face these problems. three methods have been considered.12 34 . One example would be lead. but lacks the thermal capabilities of heat dissipation to the heat sink. The manufacturers warn consumers that the amplifier must be at least 3 feet from the car’s central computer. causing it to not only heat up. and could create a safety concern. but not as great at dissipating the heat like aluminum. Steel is a compromise between both shielding and heat transfer but adds weight and does not fully shield against all frequencies and still does not dissipate heat as well as aluminum. The tradeoff is that if the braided material is wrapped around several of the components such as the MOSFETs. To do this. the high-frequency noise carried through the line will be absorbed by the voice coil of the speaker. The second possibility is to design both a base and heat sink for the amplifier that is naturally EMI shielded. there is no shielding in Class-D amplifiers. The first is a braided material that can be purchased that shields EMI very effectively.11 Also.10 In this project. it will affect the vehicles performance. This could solve the EMI problem without adding excessive cost to the amplifier. This is certainly an area that must be fully explored but will be much easier once the design of the amplifier is complete. The theoretical efficiency of a Class-D amplifier is 100%. but the cost of implementing perforated aluminum has yet to be determined.A third method is to use perforated metals. but unfortunately it is also limited by non-ideal components.997% effectiveness. Slightly more expensive Naturally Shielded Heat Sink Perforated Aluminum 1. however the attenuation required for the amplifier in uncertain at this time. Most metals either good at shielding or heat sink. 2. Serves as both shielding and heat-sink 1. the increasing switching speed necessary to produce a clean audio output also 35 . Lightweight Table 4: Shield Possibilities Active research continues on reducing interference by inspecting new arrangements for components to either reduce or completely eliminate the electromagnetic waves. In-expensive Dis-Advantage 1. Shielding Possibilities Material Shielded Material Braiding Advantage 1. 1. 2.000% attenuation of EMI. and that a shielding effectiveness of 92dB provides 99. Serves as both shielding and heat-sink 2. Tests have proven that a shielding effectiveness of 40dB provides 99. Very heavy 2. Thicker heat-sink 2. In addition.13 Our amplifier will meet or exceed the FCC regulation of 100 µVolts/m at a distance of 3 meters. The perforated aluminum appears to be the most effective way to go. Aluminum can still be used as the heat sink. but if we used perforated aluminum we can serve the purpose of both shielding and heat-sink. Lacks heat transfer properties 1. not both. Difficult to work with.6 Efficiency The most limiting factor in achieving high-efficiency is in the final stage of any amplifier. As the input sweeps from VEE to VCC. This dead zone causes crossover distortion which can be avoided when using MOSFETS and either a Sigma-Delta or PulseWidth modulated signal.reduces this factor by a great deal. This allows us to apply both a positive and negative voltage to the load somewhat easily. Another alternative commonly used in an amplifier output stage is the push-pull BJT pair found in Class-AB amplifiers where the output stage consists of an NPN and a PNP transistor. In an H-bridge configuration as the one depicted below. the output passes through a dead zone of 1. Figure 24 below shows a basic model of our circuit. 36 . current may take one of two paths. Figure 24: Basic level circuit model In Figure 24 there are four N-MOS devices. This section will attempt to describe the effects of discrete MOSFET shortcomings. In our amplifier.4 Volts in which both transistors are off. we chose to use a standard MOSFET H-bridge power stage. Figure 25: Current paths through the H-bridge Sigma-Delta technology implies that the signal be switched from 0 Volts to either rail voltage rapidly enough to represent an analog signal. In order to simulate the effects of such characteristics one would need to simulate the complex model of each MOSFET in a circuit. This means that for any given pulse.14 37 . For our purposes. There are in fact two sources of loss from switching a MOSFET. the output must change 42 Volts. The first is due to changing the drain to source voltage limited by Cds and the second from changing the gate to source voltage by Cgs. Figure 26 gives an accurate representation of what we are trying to calculate. a linear approximation of the power loss due to switching from both the drain to source and gate to source will suffice. We have circumvented such testing due to time limitations and have found equations to give linear approximations of the output. The fact that MOSFETS are not ideal and contain capacitive and inductive properties limits the speed at which this switching occurs. These can be found further along in this section. = Vds * 2 Rds 2 ⎞ ⎤ ⎡ ⎤ Vds ⎟Vds ⎥ * ⎢ ⎥/2 ⎟ ⎠ ⎦ ⎣ RLoad + 2 Rds ⎦ 2 Efficiency = 100 − 100 * 2 Efficiency = 100 − 100 * 2 Ploss Ptotal ( Psw. While other MOSFETs met or exceeded 95% efficiency at our test frequency of 192 kHz.d − s + Psw. The equations used to find the power loss are listed in Table 5 and are explained in the Appendix. Currently it is not 38 . This has been made possible by a small Rds value and reasonably small Qg value. = ⎢⎜ ⎜R ⎣⎝ Load + 2 Rds C.Figure 26: MOSFET Switching Losses The new simplified equation uses common specifications given by manufacturers and therefore may be estimated before purchasing any of the MOSFETs. one can see that the efficiency of the Fairchild FDP038AN06A0 is adequate enough for us to achieve our goal of 95% efficiency. These two specifications are the most significant in gaining efficiency. efficiency decreases proportionally.L.L. As Rds or Qg increase. SwitchingP owerLoss (Gate − Source ) = Q g * V gs * f clk = [Watts ] 1 SwitchingPowerLoss ( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts ] 2 Conduction ( DC ) Loss = VRds * I d / 2 = [Watts ] ⎡⎛ 2 Rds C. g − s + PDC ) ⎛ Vrail ⎜ ⎜ 2* R + R ds load ⎝ ⎞ ⎟ * Rds ⎟ ⎠ 2 2(RLoad + 2 Rds ) Table 5: Power Loss and Efficiency Equations From the calculations in the Power MOSFET section of this report. this model was the most efficient. These specifications are also inversely related which means that a When manufacturing a MOSFET a design consideration has to be made because it is not possible to decrease both Rds and Qg at the same time. higherpower. Feedback is a common method for dealing with this instability. The advent of these new components shall push the limits of efficiency and give engineers the tools they need to make amplifiers switch faster and ultimately produce higher fidelity sound.15 These minimize both the size and cost of the electronic devices. unless switching speeds are in excess of 10 MHz.possible to decrease both factors at the same time. we chose the MOSFET with the least DC-on resistance. Next year there will be an even better selection of MOSFETs to implement and raise efficiency once again. If employed correctly. New ways of making faster. 2. since Rds is a much larger factor to consider. Perhaps a different fabrication process will some day minimize these limiting factors. However. The most important factors to look for when deciding on any switching device would be its DC-on resistance. 39 .7 Controls Theory A certain level of control must be implemented in the system to protect against the frequent instability of an automobile environment. it may safeguard the overall output of the amplifier from variations in the rail voltages and unwanted energy produced by the signal processing. A simple block diagram of the system gives a better understanding of how the output can be used to correct these simple problems. and smaller devices are being discovered all the time. Semiconductor technology continues to advance every year. Analog Input Sigma Delta Modulation H-Bridge Low Pass Filter Feedback Figure 27: Block Diagram A main concern of this MQP is to maintain a certain level of total harmonic distortion (THD). By using the average output voltage as a midpoint. Conversely. the output will remain high for a shorter period of time.33%.33% if rail voltage rises to 52 Volts. DutyCycle = V f − Vi Vi = 48 − 44 = 8. then the output may need to remain “high” for a longer period of time to reach an equivalent analog value. This means that if a lower voltage is present. the duty cycle must increase by 8. if the average voltage of a PowerNet system is 48 Volts and voltage drops to 44 Volts. the output should not deviate from the input apart from the gain. relative voltage swings can be calculated and used to modify the duty cycle of the Sigma-Delta modulated signal. 40 . the duty cycle must be decreased by 8. For instance. the duty cycle must be changed to achieve a steady output. Since the rail voltage of the H-bridge is entirely dependent on the automobile’s PowerNet voltage. Figure 28 shows that as the rail voltage changes. if a higher rail voltage is present.33% 48 Conversely. a wide range of values must be tolerated without alteration to the speaker output. If done properly. the output should be a clean representation of the input. some of the excess energy generated by the switching output can be negated. 2. it will be show on the most basic level how the amplifier will be tested in terms of power and efficiency. All other noise generated will be attenuated by the output low-pass filter. The control circuit must be fast enough.Figure 28: Duty Cycle This same technique serves a dual purpose. i. clock speed remains much higher than 20 kHz. Theoretically. in order for this theory to work. Figure 29: Testing Diagram 41 . For this reason. In addition to opposing the effects of rail voltage swings.e.8 Test Measurement Methodology It is often times overlooked as to how the actual testing of a system will be done. Please note the following figure. 42 . If the measured output is divided by the input power. the efficiency can be calculated. this will yield the efficiency of the amplifier. we will not be testing at such a low load impedance. efficiency has already been determined in the MOSFET section of this paper. However. and might not be readily available. the testing equipment would have to be capable of handling 42 Amps of current. the output power of the amplifier can be determined using the following formula: POUT = V2 R The theoretical From the actual power of the amplifier. OutputPower = Efficiency InputPower If a 1Ω load was used for testing in lab.By measuring both the voltage and current at the power supply. the input power of the amplifier can be determined using the following formula: PIN = I ∗ V By finding the RMS voltage out of the amplifier. Such equipment is expensive. Figure 30: Basic Sigma-Delta Modulation The open loop response of this system would look something like a pole at the integration constant and a -20dB/dec slope thereafter. The design considerations we took into account for this project were signal processing.3 Design The design of a Class-D car audio amplifier is a complex and faceted undertaking. Ideally. A brief description of this technique can be found in the Background information section on Sigma-Delta Modulation. 3. This is due to its transfer function H (s) = 1 sτ int where τint is the integrator time constant. noise would be introduced mostly at the switching frequency of the system but would be minimal at audible listening levels due to the inherent noise-shaping characteristic of Sigma-Delta. thermal relief. Previous to designing the circuitry involved in transforming an analog input signal into several quasi-digital gate drive signals.16 Figure 31 shows the normal (average) distribution of energy in the 43 . Transforming Σ-∆ into a reality is not a difficult process and can be broken down into several designable stages fairly easily. one must understand the whole amplifier as a system. The design stage of any project requires the most time and effort. one is able to map the signal flow and its transformation from stage to stage. power output and amplification. and is also the most crucial to success. Using control theory. filtering. Figure 30 below shows a basic Sigma-Delta Modulation scheme with no additional components. and printed circuit board layout. It is an analogto-digital conversion (ADC) method that is an adapted version of delta-modulation. This section will focus on the design of these sections and the workings of the whole system.1 Sigma Delta Modulation The signal processing scheme that we chose was Sigma-Delta Modulation (Σ-∆). All higher frequency noise is filtered out using a low-pass filter as described in the Filter section of this report. One can see the decline in magnitude within the audible band. we were able to generate four separate gate signals to drive the four n-channel enhancement mode MOSFET devices in our H-bridge configuration separately. 2 Discussion of this topic can be found in the Efficiency section of the report.harmonics of this noise. This more advanced SigmaDelta Modulation scheme is shown in Figure 32. Figure 32: Three-Level Sigma-Delta Modulation 44 . This additional control would minimize power loss from drain to source switching. By adding a second 1-bit quantizer. we chose to modify the basic modulation scheme depicted in Figure 30. The functionality of how the MOSFETs create these three states can be found in further detail in the Power Stage section of this report. This control over all the MOSFETs simultaneously was crucial in creating a three-level output signal. Figure 31: Noise Spectrum In the design of our amplifier. given the following equation: 17 1 PDS − = Vin I o (t ON + t OFF ) f s = [Watts ] . or comparator. the signal arrives at the amplifier from the audio source as an analog waveform of either music or a test tone. Since the input and output are roughly the same but opposite in sign. After the amplified signal is filtered using a 2-pole Butterworth filter. Starting with the integrator. the result is signal 6.” In order to keep track of this error. we did not capture this waveform since the magnitude was essentially zero. At location 5. The first is to take the difference between input and feedback. an amplified version of the original analog signal. Figure 33: Integrator The integrator portion of the signal processing loop shown above has three important tasks.the rail voltage. Signal 2 is therefore the difference between the input and output waveforms. First. Now that the system has been described. are generated to control the gates of the H-bridge. The power stage of the amplifier receives these streams and is able to interpret them in such a manner to switch the four MOSFET devices. signal 4. continuous integration takes place resulting in a “sum of errors” waveform at signal 3. one can expect this waveform to fluctuate closely around zero volts. (1). the signal is very much still digital but greatly amplified to the level of +/. the schematic in Figure 33 shows the basic configuration. This may also be called the “error. This is shown in the blue square marked Delta including a pair of resistors whose center is the output. signal 7 is best described as a scaled down version of the output. This loop is continued indefinitely. While testing. four quasi-digital streams.The signal path can be described using Figure 32 above as a visual aide. each module involved can be delineated separately. Since Sigma-Delta Modulation requires a feedback loop in order to take the difference from input versus output. The second task is to 45 . Using two 1-bit quantizers. The pole of the integrator was determined 2πRz C by using the same equation. The 100kΩ + 620Ω need and application of a resistor divider network to accomplish this voltage margin can be read about in the Dead-Zone section of this report. in testing. This voltage margin was called the “dead-zone” voltage due to the fact that any output of the integrator between zero and this level resulted in zero switching of the output. it is necessary to implement both a pole and zero into the integration of the signal to achieve stability. Figure 34 shows the resistive voltage divider. Q 2 . The resistor value that yielded the least crossover distortion and optimal switching efficiency was 620Ω. We found that the calculation of such a value is a trivial matter since. and Q 2 . and flip-flop.compute the integral of the signal at its negative input terminal. This was actually performed by using two comparators whose negative inputs saw either a voltage slightly higher or lower than zero. comparators. As described in the Stability section of this report. Using this ratio of resistors. The zero of the integrator was determined to be 20 kHz using a Miller integrator equation of f z = 1 . it was best to finely tune this margin using a plug-and-check method. however this time the resistor value used to determine the pole was taken from the negative feedback of the integrator. TTL logic level voltages are sent to a D-latch flip-flop which converts the two outputs to four quasidigital streams: Q1 .18 2πR p C The next stage of Sigma-Delta Modulation was to implement comparators as high and low 1-bit quantizers. This yielded a pole at 7 kHz using the equation fp = 1 . As the sum of errors was compared to these near zero voltages. The final duty required for the integrator to accomplish is the addition of a zero as illustrated in the next paragraph. 46 . Q1 . the corresponding voltage for the dead-zone was computed to be VDZ = 15V * 620Ω = 90mV . To further clarify. this gives the illusion of three-level Sigma-Delta switching. the output of the H-bridge does follow the switching pattern seen in Figure 35. Figure 35: Three-Level Switching 47 . which is why we say that it does not directly exist. However this three-level state is what the load thinks it is seeing. what appears to be switching either positive or negative is really a change in polarity at the load. While this waveform does not directly exist.Figure 34: Quantizers If the Q1 and Q 2 waveforms are plotted on the same axis. Because the signal is three-level. The feedback attenuation block is simply an instrumentation amplifier. 3. 48 .Since the H-Bridge is described in a different section of this report. A = − R1 19 . there are 3 possible output configurations that the MOSFETs must be in.2 Power Stage After the input signal passes through our Sigma-Delta Modulation scheme. so R2 must be 30 R2 times greater than R1. that has been calibrated to the specific gain of our amplifier. the amplification factor of the amplifier is about 30. or In-amp. Figure 37 shows the three possible MOSFET configurations. Figure 36: Feedback Attenuation We were able to determine the values of these resistors by using the low frequency gain of the system. In our case. This completes the Sigma-Delta Modulation signal processing piece of our report and is now important to discuss the power output and final stage of the amplifier. we then devised a way to control the MOSFETs of the H-Bridge. we can jump to the final division of designing the signal processing segment of the amplifier. we need a third state. then we want the B-Side High MOSFET (BH) to be turned on. the BL MOSFET must be off to prevent a short to ground as well. Having this third state is what allows us to maximize efficiency because we are not wasting energy when not needed. On the flip side. if the logic output sees a negative high. which we will call the zero state. the AL MOSFET was connected to the Q1 output pin of the flip-flop. we used the output of the Q1 pin from the flip-flop to control the A-side High MOSFET. we had to use all the resources available to us. This meant that we had to use all four outputs of the flip-flop to control the MOSFETs individually. The same type of configuration occurs on the B-Side. To accomplish this goal. This means the BL MOSFET must be connected to the Q 2 output pin of the flip-flop to ensure it is always opposite from the BH MOSFET. grounding both sides of the speaker. it triggers this MOSFET on. When the BH MOSFET is on. otherwise known as AH. These two states are what control the majority of the switching. 49 . In order to achieve this. we turn both the AL and the BL MOSFETs on. The way the flip-flop is configured. This means that if the logic output sees a high. This leads us into a discussion of the final configuration of the MOSFETs. however there are still two more connections to be made. this corresponds to the Q 2 pin. During this time. When the AH MOSFET is on. zero. For the time duration when neither the AH or the BH MOSFETs are on. the AL MOSFET must be off.Figure 37: Three possible MOSFET configurations In order to achieve the three states shown above. This ensures that the AH MOSFET and the AL MOSFET will never be both on or off at the same time. Transfer functions are equations that help relate both gain and phase shift to a circuit. This section of the report discusses the different parts of the amplifier and how they each help or hurt the stability of the system. Z(s) and P(s). instead of the negative feedback being able to correct for any imperfection in the output as described in the Sigma-Delta section of the report. These frequencies are calculated in the Filter section of this report to be at 14 kHz and 40 kHz. It is preferable to have a phase at which gain is 0dB of 145°or less. A driver chip was chosen for two reasons. causing the system to crash. a zero produces a phase-shift of +90° while a pole produces a phase-shift of -90°. which means it has two cutoff frequencies.22 This is also called the phase margin. Poles are values that make P(s) = 0 and the overall gain infinite20. Between the flip-flop and the MOSFETs is a driver chip. 3. A circuit must be able to operate without unwanted resonance that may be damaging to its components. In addition. This could be detrimental to any system taking negative feedback from the output because the resonance could oscillate indefinitely. resulting in quicker turn-on and turn-off times. The first reason is because it has built in logic protection to ensure that 42 Volts is never shorted to ground. Zeros are values for s that make Z(s) = 0 and the overall gain of the system zero. The second reason is because the driver chip we chose can source up to 1 Amp of current per gate drive. but there is one other device that was not yet mentioned. The two polynomials. If the open-loop gain at these frequencies approaching -180° phase shift is not less than 1. A typical transfer function has the form H ( s ) = Z (s) . or 0dB. allow the zeros and P( s) poles of the system to be found. resonance may become a problem. 21 The low pass filter used in the power output stage of the amplifier plays a large role in maintaining stability. This filter is 2nd order.3 System Stability A major concern in designing our amplifier was how stable it would be under normal operating conditions. The actual schematic of the Power Stage can be found in the Appendix.The output from our Sigma-Delta Modulation is what tells the MOSFETs when to turn off and on. What this means is that it will turn each of the MOSFETs off and on with more power. the noise is reinforced. Together these two poles (low-pass cutoffs) add an additional -90° of phase shift to frequencies above each of their cutoffs. Each part of the amplifier was tackled by finding their individual transfer functions to avoid unwanted resonance. Now. or difference between 50 . we had to determine the DC gain of our system. The pole of the integrator was located at 7 kHz while the zero was introduced at 20 kHz. it was computed to be the following: ⎛V A = 20 log⎜ OUT ⎜V ⎝ IN ⎞ ⎟ ⎟ ⎠ ⎛ 42V ⎞ A = 20 log⎜ ⎟ ⎝ 6V ⎠ A = 16dB We then decided to draw a Bode Plot of our system.0dB phase and -180°. increasing the frequency of the integrator pole shifts the magnitude curve up and phase margin increased. The location of the zero was chosen purposely close to the 14 kHz pole of the output low-pass filter. It was determined that our system could not tolerate any more poles without zeros. The result of this action is such that neither pole nor zero have an overall effect on the system. therefore an additional resistor was added in series with the capacitor of the integrator. The value at which the resulting phase margin is 35° is 7 kHz and can be seen in Figure 38. Please reference the Sigma-Delta section of this report for this schematic and cutoff frequency calculation. The cancellation of pole and zero then allowed us to determine the frequency at which to make our integration pole while maintaining a phase margin greater than 35°. 51 . Using the equation below. By reducing the frequency of this pole location. Therefore a graphical method was used to determine this value. This zero would offset the phase shift and decrease the attenuation [in dB per decade] caused by the pole. Conversely. the magnitude curve is shifted down and phase margin decreased. First. Figure 38 helps illustrate the graphical method we used in obtaining the integrator pole. The DC gain of our amplifier is 16dB and therefore can be regarded at the starting point of our Bode Plot. Later in this section it is shown that a phase margin of 35° is required for stability. This calculation was not a simple one to make. The other source of poles and zeros comes from the Miller integrator used in Sigma-Delta processing. In this amplifier. the output filter relies on a 4Ω load for stability. This is justified by the phase margin of about 35°. Figure 39: Bode Plot From Figure 39 one can see that the system is stable.Figure 38: Graphical Bode Plot Method The final bode plot of the system can then be plotted. This can be seen in Figure 39. 52 . If the gain of the amplifier was increased or load changed to different impedance. the system may become unstable. However. the inductors had to be custom made. In order to solve this problem. 1 f1 = 2π L ∗ C R f2 = 2π ∗ L 53 . The problem that arose was that we then had to be concerned with the stability of our system. Early in the project. we knew that inductors would have to be ordered. Separating the poles of the filter turned out to be a much more difficult task than anticipated. In order to determine the cut-off frequencies for our filter. Originally. This signal would contain a great deal of unwanted high frequency content. Because of the high current rating of the inductors required for our specifications. This is because the human ear can only hear from 20-20 kHz. This resulted in a fairly costly investment for our amplifier. so any frequencies higher than this would result in wasted energy that the speaker would try to play. the filter got slightly more complicated when we introduced our Sigma-Delta circuit. Originally. a sinusoidal input would remain in the form of a three-level Sigma-Delta Modulated output. we thought that we would be able to run a 1Ω load. we could not afford to send away for new ones. a low-pass filter was introduced to the circuit to cutoff any frequencies higher than approximately 20 kHz.4 Filter One of the most critical stages of our amplifier was our filter. meaning that there could not be a double pole at 20 kHz. the two equations below were used. This energy at frequencies up to the fastest response frequency of the driver chip may be potentially damaging to a speaker and would use any speaker wire as an antenna for radiating EMI. so once we had the inductors in our possession. Again. Without it. resulting in nearly 50 Amps of current to be drawn through the inductors. The details on the stability of our system can be found in the Stability section of this report. we thought we could create a second order Butterworth filter with a double pole at 20 kHz.3. From a design standpoint the only thing we needed to know was that the poles had to be separated. the reasoning for this can be found in the Stability section of this report. This posed a bit of a problem for our design. thinking ahead to the testing of our amplifier. we decided to stick with a fixed load resistance of 4Ω. This can be seen in Figure 40 below.5µH Notice that the cut-off frequency is only 14 kHz. one for each half of the bridge. Figure 40: H-Bridge Filter Configuration When trying to design a filter for an H-Bridge configuration. there are two separate filters. we were limited in the range of cutoff frequencies we could obtain.Notice that the inductor value is used to obtain both cut-off frequencies. This means that because we were stuck with our original inductor value of 22. because half would belong to each side of the filter. Also. Please refer to Figure 41. f2 = R 2Ω = = 14kHz 2π ∗ L 2π ∗ 22. Also notice that a resistance of 2Ω was used in the equation instead of 4Ω. most people can only hear up to 16 kHz.5 µH. This meant that the cut-off frequency for f2 was predetermined. What this means is that it is necessary to divide the bridge in half. you will notice that the inductor value and capacitor values remain the same. the easiest way to approach the situation is to look at only half the bridge at a time. Although the first cut-off frequency is lower than 20 kHz. This is because in an H-bridge configuration. 54 .23 By taking that into consideration. The only variable that changes is the resistive load. The benefit of purchasing new inductors was not worth the small increase in cut-off frequency of the low-pass filter. This is a design trade-off that we had to make in keeping our original inductor values. we decided as a group that it was one design decision we were willing to live with. If that is done. so we decided to use those as well.7 µF Based on this formula. This was not as big of a concern because we had the ability to add as many 0. Notice that the inductor value is also included in this equation.7 µF. when looking at the filter half representation. f1 = 1 2π L ∗ C → 40kHz = 1 2π 22. we were able to compute what capacitor value was desirable to yield a cut-off frequency of 40 kHz.1 µF as we wanted. but still low enough in frequency to reduce EMI. Using the formula for f1. After we accepted the first cut-off frequency to be 14 kHz. giving us a range of overall capacitance. only 2Ω belongs to each filter. Knowing that our first cut-off frequency was 14 kHz.1 µF capacitors that we already had by configuring 7 of them in parallel. This would be well past the audible range.5µH ∗ C → C = 0. and you will notice that there is still a 4Ω load in place. Once again we already had purchased several 0. This would be easy to obtain from the 0. 55 . which is the reasoning behind the 2Ω being used in the f2 equation rather than the 4Ω. the capacitance value that should be used is 0.1 µF capacitors. but we do have the flexibility to change the capacitor value. it was then time to set the second cutoff frequency. However. Figure 42 shows how the filter may look from a schematic perspective. we decided to make the second cut-off frequency approximately 40 kHz.Figure 41: H-Bridge Filter Half Representation The circuitry remains exactly the same. 6Ω for the capacitors we chose. This was an important factor to take into consideration because at low frequencies. or ESR of the capacitors. the ESR is relatively high. As the frequency increases.Figure 42: H-Bridge Filter Design Configuration One of the reasons that we decided to use multiple capacitors in parallel rather than one big capacitor was to reduce the equivalent series resistance. There is a way to reduce the total number of capacitors used that create the same filtering effects. Although the configuration shown in Figure 42 would have worked. measuring at 1. If you count the total number of capacitors in the circuit. you will find that 14 capacitors would be necessary in order to produce our filter. The ESR is a calculated resistance at a particular frequency. However. A high ESR would be detrimental to our efficiency. AC current through this series resistance would be lower at low frequency since I = C dv . dt and will be talked about in further detail in the Efficiency Losses section of this report. this was not the layout that we chose for our filter. Please refer to Figure 43 for further clarification. The way to achieve that is to use some of the capacitors across the load instead. 56 . the ESR decreases linearly. If this amplifier is to be marketable. Also notice that the total capacitor count was reduced from 14 to 12. three rows of 4 capacitors would have to be used.7 µF and 0. rather than one side at a time. This is because they contribute to both sides of the H-Bridge filter. then a capacitor count of 16 would have been necessary instead of the 12 we used in our filter design. Well this is true. and in order to achieve that. we knew that the MOSFETs used for our H-Bridge would get hot due to the fast switching speeds. Had we not added the capacitors across the load.5 Heat sink For the testing of our project. Two different considerations were taken into account. To increase the performance.7µF. the heat sink would have to be large enough to keep the MOSFETs cool for long durations of playtime.8 µF of effective capacitance. We decided that this was also a design tradeoff we were willing to accept because the difference between 0. The second consideration was to design a heat sink for marketing purposes. We decided that we wanted a symmetrical looking board. 3.8 µF resulted in a cut-off frequency of 40 kHz and 37 kHz respectively. they essentially become twice as effective. for 57 .Figure 43: H-Bridge Filter Configuration By placing some of the capacitors across the load. then that yields an overall capacitance of 0. However. not 0. while still increasing the effective capacitance. Notice that if the 4 capacitors across the load count for each side. and still wanted 0. a large heat sink was created to help maintain a reasonable temperature for the MOSFETs.8µF. The first consideration was to build a heat sink for testing purposes. the testing of our amplifier in lab. The design of the heat sinks presented some constraints. but since the product was already finished. in order to maximize the surface area of the heat sink to the ambient air. Because we had a machine shop at our disposal. we decided to drill and tap some supports into the fins of the heat sink. This would allow us to use 58 . Figure 44: Heat sink used for testing Figure 45: Heat sink shown with supports One of the problems that we encountered with such a large heat sink was the weight of the finished product. Our second constraint was the depth of the heat sink. but in our situation it was best to over estimate the need for thermal protection.25”x 2”x 1. One constraint was how wide the heat sinks could be by the amount of space we had on our board between components. Generally the more cooling fins that a heat sink has. For testing purposes. An actual picture of the heat sink used for testing can be seen in Figure 44 below. the better job it will do at keeping the components cool. The aluminum was donated to us by A & R Plastics Inc. and to design another that would be used as both a housing and a heat sink if the amplifier was put into production.375”. we decided that 15 minutes of playing time would be more than sufficient to test the amplifier and obtain our results. Secondly. This yielded two identical heat sinks with overall dimensions of 2. two heat sinks were fabricated out of a solid piece of aluminum. as well as their machine shop for fabrication of our heat sinks. The heat sink was made larger than necessary. which was limited by the depth of our board. we thought it would be best to leave it alone. It was decided to construct an adequate heat sink for our purposes of testing in lab. The heat sink could have been made smaller. We chose aluminum for the design of our heat sink because of its light weight and thermal properties. cooling fins were added to the design. All other devices were not as much of a concern in this stage of PCB design. and the casing surrounding the amplifier would double as a heat sink. Instead. 3. Figure 45 shows a heat sink mounted to the MOSFETs with supports in place to help reduce the load the MOSFETs would have to carry. After it was mounted to the board. which causes the most amount of switching. and so did the heat sinks. In addition to this casing being used as both a heat sink and an outer housing unit. In order to deal with the thermal protection of the MOSFET devices. high-power switching MOSFET devices were a major concern and had to be dealt with carefully. This means that the heat sinks can not be two large objects attached to the MOSFETs. Through our experience with other audio amplifiers we were able to determine their best location. any components including input and output terminals requiring special locations can be placed. Lastly. heat was an issue. the basic shape of the board can be determined. One must first analyze the components that will ultimately populate the board and their needs. the remainder of parts can be laid out using good engineering practices described in this section. Fins would be incorporated into the design for what would hopefully be fan cooled. large heat sinks would be required. the idea worked. the idea worked out quite well. We were able to play music. Secondly. Thirdly. the MOSFETs would be placed at the very edge of the board. In the event that our amplifier is to be sold in today’s market. We knew that under the high current and fast switching they would be subjected to. for approximately 15 minutes before the heat sinks started to get too hot. Often times certain components require special locations and must be considered before all others. 59 . This was the case in the design of our PCB as well. it would also serve as an EMI shield which was discussed in the Background section of this report. Although it may not look as professional as it should. The actual fabrication of this type of device was not made. In particular.6 Printed Circuit Board The design and layout of any printed circuit board is a very cognitive task. however it is important to point out the need for a housing in the event of a continuing MQP or for marketing purposes.Teflon screws to support the weight of the excessively large heat sink. By aligning the TO-220 packages along the edges of the PCB and facing heat sink tabs outward. We were able to conduct all of our testing with the heat sinks shown. we would be able to effectively build as large of a heat sink as necessary. the amplifier would have to be contained in a solid casing of some sort. On one hand. Adversely. 60 . much like our circuit for both simplicity and practicality. The layout of the final board design was the next step to take place. One side of the board was clearly designated as the signal processing portion whereas the other was reserved for the power output section. As mentioned previously. Therefore we found it best to divide the PCB into sections. many wide current paths. the flow of our signal path was strictly unidirectional if feedback were ignored.Figure 46: Placement of MOSFETs for Heat Sink Determining the fundamental shape of our board was one of the more elementary steps in laying out our design. the most basic and industry standard shape is still the rectangle. These two divisions are distinct from one another in their requirements so were best left separate. This would allow for as much surface area as required by heat sinks as well as minimizing wasted space. While many forms and sizes may have worked. Since our design followed a strict flow of information in one direction. the power output stage of the amplifier requires large ground planes. and spacing between thermally dangerous components. an elongated rectangle certainly seemed the most reasonable model. the signal-processing side is filled with mixed signals and hightransient voltage transmission lines. 61 . ground. The first and foremost was to allow high transient voltages their own paths and ground planes while keeping them short. or 2. we measured currents in excess of 10 Amps. Any high current path that is too narrow will not have negligible resistance. Failing to do so will certainly affect signal integrity as each trace acts as a transmitter and receiver. These traces should be kept as wide as possible to minimize the trace resistance. What this means is to avoid running other traces either over or under these paths in a multilevel board. and wherever possible. and speaker connections on the power output side of the board. we believe that efficiency and signal integrity can be maximized. In our design using a 4Ω load.1Ω trace would burn up to 10W of power.Figure 47: Two Separate Sections of Board Layout Good engineering practices should always be used when designing a printed circuit board. From a power loss perspective even a 0.5% of the total. This loss could greatly set back our efficiency goal. Another method of keeping these traces short was to place power. power planes should be used. There are several rules of thumb that we used. This is due to the fact that the traces are capacitively and inductively coupled. By following these layout rules. The second rule that we used was relative to any high current paths. It took some time to complete. After much debate as to how the board would be laid out.1 First PCB Once the design was finalized in the respect that we were using a MOSFET H-Bridge configuration that was controlled by a driver chip. several board designs were used to achieve our goal. 4. and also could have damaged the components we were trying to test. it was time to perform some testing. we knew that we would be drawing approximately 2.5 Amps of current. there were 3 wires attached to a single pin.5 Amps of current would be traveling. At first we started small. one would then have to heat up the pin a second or a third time to add the additional wiring. In many cases. and the bridge to ground. we decided to wire the power stage of our amplifier using primarily 22ga wire for most of the connections. The simplest way would have been to use a breadboard to wire the circuit. so our results would not have been as accurate as we would have hoped. This section of the report will explain how the project evolved and how we ended at out final result.4 Project Evolution In order for us to complete the project with a working amplifier. however breadboards contain capacitance and inductance between the traces. however 16ga wire was used to connect the power supply to the MOSFET bridge. Pulling such a large amount of current through the breadboard could have caused it to melt. In doing so. the previous wires that were already attached had the tendency to fall off because the solder was heating back into a liquid state. the bridge to the load. and eventually worked our way to a professional looking printed circuit board for the testing our amplifier. we decided to use a PC board that we would wire ourselves using a design layout that would minimize interference with transient currents as described in the PCB design section of our report. This made it difficult because after one wire was soldered in place. but you can see the end result depicted in Figure 48. and this reached the threshold of what we considered to be too much for a breadboard to handle. This is where the 2. 62 . Soldering the wires to all the components proved to be much more difficult than anticipated. and we wanted to ensure that the wire would be able to handle the large current draw. which would have been a safety concern in lab. Because of this. Also. 4. and at first it was difficult to use. We then sent out the board to be created using a company called Advanced Circuits. we tried our best to keep the board layout as neat as possible to simplify troubleshooting. When we started the board layout. the custom wound inductors were just being ordered. diodes. they are hanging off the edge of the board. were finalized. but for the time being.24 We looked into several vendors to create our board. we were able to make it work regardless. but we got used to it and it worked out very nicely. and also gave us some practice for the heat sinks that were created later in the project. trace inductance and capacitance even further. Another thing to point out is the large black block attached to the MOSFETs. The program that was chosen to create the board layout was Ultiboard 2001.Figure 48: Original PCB As you can see. This was a chunk of aluminum we cut to use as a heat sink. but through the use of banana connectors. however they were not only the cheapest.2 Second PCB After our original PC Board was working properly and all the capacitor values. so we had no idea they would be so large. Because of this. etc. we thought that having a professional PCB would make things neater and a lot easier to work with for further testing. we then decided to create a real PCB where we would get a more professional looking board that minimized transient currents. The huge coils that you can see at the top of the picture are our inductors used for the low-pass filter. but also had a free quote by uploading some of our files that 63 . resistor values. The aluminum served the purposes we needed it for. We knew we still had the signal processing to work on. Every flaw that the program found in our design was minor enough that the board could be produced immediately. and after that. 64 . However. and the product was paying off. making the solder contact only on one side of each pin. we were very happy with our product.even told us where we had flaws in our design. Most flaws were clearance issue such as a hole being too close to the edge of the board. To our surprise. making it very difficult to solder to A keep out area on the power plane was forgotten around the driver chip to make soldering easier The drill holes for the RJ45 jack were much too large. the price remained the same. the holes were larger than needed. A few of the diode and capacitor holes were slightly larger than necessary The power and ground pins for the voltage regulator were reversed. Also. Even where the BNC hole was too small. Fortunately however. This is because setting up the equipment to create your board takes the most time. we would have run into a much larger problem. It was very impressive looking. When our board arrived. but more importantly it was a very neat design with a lot of thought put into the board layout. We were expecting a turnaround time of a week or two. but since the board size was not etched in stone. we were still able to make it fit after some TLC. Had the situation been reversed. requiring surgery on our PCB Although most of the issues had to do with hole sizes. The flaws that we found in our first board were as follows: • • • • • • • • • The ground pins of the BNC connectors were not connected to our ground plane The signal pin of the BNC connector was slightly too large for the hole that was drilled for it A keep out area on the power plane for the banana jacks used for speaker connections was forgotten Mounting holes to elevate the board of the ground were forgotten Many soldering pads were too small. the material cost for the board itself and the solder used to coat it is insignificant. they just expanded the board for us where it needed it. nothing was catastrophic to the forward progress of our project. Our first professional looking PCB can be seen in Figure 49 and Figure 50 below. the turnaround time was only a few days. the first draft if you will of our project did have a few flaws. luckily in almost all cases. another observation that we made was that whether you bought 1 board or 4 boards. the MOSFETs were separated by pairs on each half of the board. The only other mistakes on our part was a via that somehow connected one of our traces to the 42 Volt power plane by accident. It was much easier to create this heat sink that it was for the first one because we now had some experience under our belt. Unfortunately we do not have a picture of this board fully populated. and add 4 more. there were no mistakes this time around. we realized that we needed to control all four MOSFETs individually. but it was well worth it. The good news about this board was that because it was our second iteration of the power stage. This was easily corrected by switching one of the leads for two resistors. Originally we thought that we could use two inputs for our driver chip. we were ready to send out for another professional PCB. but this did give us a chance to improve our fabrication skills. there were a couple in our new section for signal processing. Because of this. and our feedback loops had to be switched. This would be our third board to work with. We once again sent the board out to Advanced Circuits because we were pleased with the results from the first board. This was probably the most cosmetic damage that we had to put our board through. To make it look slightly more appealing. 4. a new heat sink had to be created.Figure 49: Second PCB Ground Plane (Top) Figure 50: Second PCB 42V Power Plane (Bottom) For this board. This meant that we had to cut a couple of the traces off the board. but after the board was already returned to us completed. This ate up about half of our budget. This time however the board was about 3 times the cost of what it was the first time because of the considerable size difference.3 Third PCB After making all the necessary corrections to our second PCB and adding all the components for our sigma delta signal processing. However. we hid one of the resistors 65 . Figure 51: Third PCB Ground Plane (Top) Figure 52: Third PCB 42V Power Plane (Bottom) The populated board that was used for testing can be seen in Figure 53 below. This was the board that we used for all of our testing on the amplifier. and also have fins on them to provide more surface area to the ambient air. a massive heat sink was created. so that as you looked at the top of the board.under the board. This is why the heat sinks are so much larger than the previous ones. causing the MOSFETs to switch much more often that if they were playing a sine wave. the hotter the MOSFETs will get. 66 . The board itself can bee seen in Figure 51 and Figure 52. you only saw 1 resistor at a 45 degree angle rather than 2 crossing resistors. The more switching that takes place. As you can see. which increases the thermal properties of the heat sink. We put a lot more time into this design because we knew that audio applications play at a wide range of frequencies. and the board made as small as possible. It is however a great place to pick up from if this project gets continued in the future. but now that the bugs are worked out of the amplifier. They were necessary for troubleshooting. 67 . we ran out of both money and time. but unfortunately. they just get in the way.4 Fourth PCB After correcting the mistakes that were found in our third PCB. The PCB is ready to be sent out with all the mistakes already corrected in the program. Also added to the board were twice as many bypass capacitors for the 42 Volt power source. It also was important to see how small we could get the amplifier in size without the BNC connectors on there. The board layout for our final PCB as well as the previous ones can be found in the appendix.Figure 53: Third PCB Fully Populated 4. We did this with the hopes that we might be able to send out one last board. we decided to create a fourth PCB with all the BNC connectors removed. For this task. we were able to determine both input and output power of our amplifier. This section will illustrate the tools and techniques used to determine efficiency as well as an explanation of our final results. With this device we were able to capture snap-shots of the output waveform as shown in Figure 54.1 Efficiency Testing The goal of this project was to design and build a Class-D amplifier that achieves an efficiency of 95%. However. We were somewhat limited by the accuracy of this device since it was accurate only to one-tenth of an ampere. There are several methods by which power can be calculated. Using the resources available we would need to determine input and output power. we would be able to easily monitor the input voltage directly on the board using an HP 34401A multimeter accurate to six significant figures. but the resources that were available to us were slightly limited. In order to determine that we met this specification it is first important to discuss the method of which data can be collected. Power = I * V V2 Power = R Since the BK Precision regulated power supply we were using gave a current reading as well as a voltage reading. 68 . we chose to use a Tektronix TDS 210 digital real-time oscilloscope. by utilizing the simple equations below. and explain to you the results we obtained. The output power was measured using only one device at a time. On the other hand. 5.5 Testing and Results In this section of the report. we chose to use the P = IV equation for input power. we will guide you through the process of how we tested various aspects of our amplifier. It was necessary to use three measurement devices in order to determine input and output power. the ratio of input and output powers was solved for and recorded as the percentage efficiency of the amplifier. Finally. voltage. Avg (VOUT ) = 2 ∑V n 2 OUTi n 2 VRMS = Avg (VOUT ) The equation for output power was simply PO = 2 VRMS . This relation is essential in determining the sampling frequency at which yields 69 .Figure 54: Oscilloscope Snapshot When connected to a computer. R The change in resistance due to temperature was apparently negligible because the load resistance measured to be the same at both ambient room temperature and at 140°F. or root-mean squared. Efficiency = POUT [%] PIN The efficiency in comparison to clock speed of the Sigma-Delta Modulation was our most critical measurement. data could be uploaded into a spreadsheet to find the RMS. This was solved using the following equation. 70 . At this condition.00% 0.75 1.00 0. For this case.00 1.00 4.00% 78. 1.00% 80.00% 96. This produces the least efficient case since the output never reaches the rails of the supply.50 2.25 3.00% 88.00 3.0Vin Figure 55: Efficiency vs. While no switching is taking place.6Vin 100% Clipped.00 2.00% 86.00% 84.50 3. Efficiency vs. switching is at a minimum. This proves that we do in fact meet our expected 95% efficiency.25 2.75 2.00% 94.25 Clock Speed [MHz] 0% Clipped.50 1.the highest efficiency.00% 92.25 1. Therefore switching occurs at each clock pulse in order to represent a median value. 3. By using a HP33120A to generate an array of clock waveforms we were able to graph the results at several frequencies ranging from 250 kHz to 4 MHz. Clock Speed Efficiency is shown here under three different input conditions in addition to clock speed. The final case utilized for these results uses a fully clipped input signal.75 3. The second case was taken with a 40% clipped input signal. Clock Speed 98. little or no switching takes place nearly 40% of the time.00% Efficiency 90. Nearly all switching loss is therefore avoided and maximum efficiency is obtained. Figure 55 below shows the results of these tests.50 0. the output is either high or low during each half cycle of input.25 0. thus the Sigma-Delta Modulation does not send a correcting signal. no error can be apparent with the output at the rail.75 4. 1.00% 82.4Vin 40% Clipped. The first condition uses an un-clipped sinusoidal input. Using a fully clipped input signal we were able to achieve a maximum of 97. For a closer look at the components involved see the section on Sigma-Delta.7 kHz / 2 Mhz ) Vripple = 0. using the correct value for the dead-zone resistor is important when optimizing efficiency and will be explained in the following section of this report. Finding the ideal resistor value is a multilevel process beginning with the calculation of the integrator time constant. Since the 42 Volt PowerNet standard states that all vehicles should run at a charging voltage of 48 Volt. τint. Our first calculations to find an accurate deadzone resistor are seen below. we decided to test our amplifier in that state. Vripple = Vin (1 − e − t / τ ) Vripple = 5V (1 − e −6. The following equations are given knowing the transfer function of a Miller integrator discussed in the Sigma-Delta section of this report. Lastly. Rdz. 5.05V 71 . the signal processing circuit must be properly calibrated. One of the first items that must be taken into account is the dead-zone resistor.There are other factors that affect efficiency. The larger efficiency is due to the increase in voltage and was noted to be due to the standard specifications.2 “Dead-Zone” In order to achieve a clean output. It determines the voltage that each comparator sees on its negative input.4% efficiency. τ int = Rint Cint τ int = (24kΩ)(1000 pF ) τ int = 150u sec The corresponding dead-zone voltage would then be easily calculated as the voltage that the output of the integrator would swing during this time. Therefore the dead-zone voltage is half this total swing.Figure 56: Ideal Integrator Output Figure 56 shows the ideal integrator output and how given the correct VDZ there should be no overlap of MOSFET switching and minimal crossover distortion.5Ω It is also important to mention how to calculate VDZ given a Vrail of 15V. 1 VDZ = Vripple = 0. VDZ = Vrail RDZ RDZ − R100 k 72 . and R100k.025V 2 The dead-zone resistor is therefore the value that completes the ratio: VDZ RDZ = Vrail RDZ − R100 k RDZ = 167. RDZ. The problem with crossover distortion is that this greatly affects performance at lower volume since the dead-zone is a large portion of a small input <100mV. Figure 57: Vdz = 7. outputs of the flip-flop will be too active.However when implemented in the circuit. With a dead-zone that is too small. The output of the tri-level sigma-delta modulation scheme should be two waveforms that should nearly overlap at low voltages to avoid crossover distortion and not result in clipping at the output. This distortion can be seen in Figure 58 and Figure 59. a value too great would result in cross-over distortion. this did not give us the results that we were looking to achieve. 73 .5mV (Too Small). When the input voltage is near zero. f = 1kHz Cross-over distortion is caused by too great a dead-zone voltage seen by the comparator negative input. This leads to a period when the outputs are both zero. This decreases the efficiency of the scheme greatly since it leads to the greatest amount of switching. the filtered output looses its sinusoidal shape and flat-lines causing cross-over distortion for a small time duration. On the other hand. Figure 58: Vdz = 150mV (Too Large). listening tests were a second option. The perfect dead-zone voltage was found by plugging and checking several resistor values in order to find where the crossover gap shrinks to zero and minimal overlap switching occurs. This is due to the fact that ⎛V ⎞ signal-to-noise ratio is calculated as 10 log⎜ SIGNAL ⎟ . Figure 60 and Figure 61 depict the ideal results given when using this value. We can say that there was a distinct difference in noise level between each of the deadzones depicted above.25 This noise would emphasize the need for a ⎜V ⎟ ⎝ NOISE ⎠ smaller dead-zone. Since crossover distortion is clearly a result of an inaccurately tuned dead-zone. Additionally. 10kHz The theory behind the dead-zone voltage states that the noise in the output is regulated by the amount of crossover distortion. one can state that output noise is proportional to dead-zone voltage. 1kHz Figure 59: Vdz = 150mV (Too Large). 74 . This voltage value was 50mV. a signal processing scheme equipped with a larger dead-zone was susceptible to a greater percentage of noise at low input voltage levels. Although we lacked the time to perform accurate signal-to-noise tests with several dead-zone voltages. acoustic clarity is the ability of our amplifier to play music with adequate speech intelligibility. of acoustic clarity. f = 1kHz Figure 61: Vdz = 50mV (Near-Ideal Value). The purpose of attenuating the output was to listen at a comfortable level while maintaining a 4Ω load. Tests were conducted with a variety of input music and test signals. We performed several listening tests using the amplifier and attenuated load/speaker combination. This would lead to overheating of the MOSFETs and ultimately cause the amplifier to run too hot. 75 . The following section continues discussion 5. The configuration we used for testing can be seen in Figure 62 as a resistive and loudspeaker load.Figure 60: Vdz = 50mV (Near-Ideal Value). overlapping high and low switching signals could be detrimental to efficiency. f = 10kHz The result of choosing the correct dead-zone voltage maximizes efficiency while providing satisfactory acoustic clarity.3 Acoustic Clarity By our own definition. While minimizing crossover distortion is important. Figure 62: Speaker Test Although listening tests were satisfactory. This noise had a constant magnitude regardless of input signal. On the other hand. noise should have been stopped from reaching the load. Texas Instruments LF356 operational amplifiers were used in place of more expensive types. After testing several 76 . so it was determined to be internally generated. anything below our sampling rate should also be compensated by the time it reached the output with negative feedback. it was best to leave any CD player or other device at full volume. In order to maximize the signal-to-noise ratio. In one respect. there was a slight “hiss” in the output. At low volume speech intelligibility was greatly degraded. In a final board design these components would be swapped with more precise and faster slewing chips. we displayed an FFT of the output. There are a few culprits that have been identifies as candidates for the hissing noise at our speaker. According to our system design. The first are improperly calibrated resistor networks used as voltage dividers using 5% resistors. In practice it is best to use special resistor network packages calibrated to less than a percent. any high-frequency (EMI) would be filtered by a two-pole Butterworth filter.4 Output Power Due to the fact that this MQP was about creating an audio amplifier. To view the noise. Secondly. we thought it was necessary to show that the project we constructed actually had the ability to amplify a signal. 5. 57 Input 1. we wanted a signal of equal magnitude to have the ability of playing through our amplifier without clipping. Gain = Output 40 = = 28. Figure 63: Input vs. the voltage rails that we are using are 42 Volt.4 Volts.4 Volts. To determine the gain of our amplifier. Other adjustments could have been made to achieve a 77 . which would result in a clipped output. Based on Figure 63. This gain of 30 that we obtained was determined using the specifications of a CD player maximum output value of 1. Output What you can see from the picture is an input sine wave at 5 Volts per division on the scope and an output sine wave at 25 Volts per division. What you can’t see is that the test input signal was an 800 Hz sine wave with amplitude of 1. you can simply divide the output power by the input power as shown. This output can be seen in Figure 63 below. This gain factor can be decreased at our discretion by adjusting the feedback discussed in the Sigma-Delta section of this report.different areas of the amplifier. As you may recall. we were able to capture an oscilloscope output of one of our tests. The output waveform was measured to have amplitude of 40 Volts. Because this was a maximum value. the gain of our amplifier is approximately 30.4 As you can see. the output is only 2 Volts from reaching the rails of our amplifier. notice that the output remains in phase with the input. and met our goal of creating a high powered amplifier. SNR = PSignal PNoise 78 . The idea is that you want the output power to be much greater than that of the noise power in order to have a clean sounding amplifier. To recap. If the noise power is small enough compared to the output power. we were able to compute the RMS power of our amplifier. one specification given on almost every amplifier is a signal-to-noise ratio. If the output was out of phase with the input. Using the same Microsoft Excel spreadsheet.greater gain if the input signal was attenuated. We also wanted to know how much power our amplifier was able to produce.4 Volts. the formula we used was: Power = V2 R Using the same input of an 800 Hz sine wave of amplitude 1.5 Signal to Noise Ratio When looking at industry standards. We were very pleased with the results. then the result would be rear speakers that were playing out of phase with the front speakers. 5. however we felt that the maximum value out of a portable CD player was adequate for our testing purposes. then it will not be audible to the human ear at the output. This specification indicates how much noise is created in the amplifier relative to the signal you are trying to pass through it. often times an amplifier is used to only power the front speakers in the automobile. resulting in poor sound quality and noise cancellation. The SNR more simply is the ratio of signal power to noise power. This formula can be seen below. To do this. This is important because in car audio applications. but it granted us great satisfaction in knowing that the amplifier we produced is capable of competing with other amplifiers on the market.26 Referring to Figure 63 once again. we were able to measure a power output of 400 Watts RMS when 42 Volt supply rails were used. Perhaps 400 Watts was slightly more power than necessary. we imported the data from the oscilloscope to our computer as mentioned in Efficiency section of this report. For our amplifier. Figure 64: FFT used to obtain SNR The oscilloscope that we used for testing was a Tektronix TDS-210. Everything else was considered to be noise in our system.4 Volts. To do this. That was done by observing the large magnitudes that occurred around 800 Hz where the spike was apparent. the total power in each was found. PdB = 10 log10 PWatts = 10 −12 PWatts 10 −12 PdB 10 × 10 79 .In order to compute the SNR. This was done by converting all of the data from decibels into watts of power. where we were able to use the data to compute the power of both the signal and noise. We then examined the output. The data was imported into Microsoft Excel. an FFT of the output must first be examined. as seen in Figure 64 below. With the signal and noise magnitudes separated. we had to first separate the signal power from the noise power. we used an 800 Hz sinusoidal input with amplitude of 1. The equations below show the correlation between decibels and watts of power. One of the features that made this scope easy to work with that it has an output that allowed us to import data into the computer. Hours were spent doing research and testing of why an amplifier is not capable of 100% efficiency. there are a few specifications that require special concern. The method by which efficiency would be maximized would be to first find the most ideal MOSFET switches. Before one can name these categories.All of the signal and noise powers were then summed separately. SNRdB = 10 log WSignal W Noise . These equations are found in Table 5. the SNR was easy to calculate at this point. Some of these suggestions are listed in the Recommendation section of this report. 5. Our amplifier is much less. Since ideal switches do not exist. there are several things that could be done to try and increase the SNR. or possibly locate the noise in our system. the Class-D design should be able to output as much power as it receives. 80 . the first objective was not as much of a major concern as the second one.6 Efficiency Loss The primary goals of this MQP were the design of a high-power ultra-efficient Class-D amplifier and the analysis of why 100% efficiency is not possible. Because the SNR is simply a ratio of the two powers. it is prudent to look at the equations that govern power loss in switches. Neither Class-A nor Class-AB boasts efficiencies above 50 or 80% respectively. With the information obtained from the FFT. While the design of the amplifier was instrumental in completing a successful project. we determined that our amplifier had a SNR of 43dB using the next equation.27 The theory behind this is illustrated in the What is Class-D section of this report. If more time were permitted. A closer look into these specifications was done in the Background section of this report. Typically in the market. In theory. Thanks to MOSFET switching devices. you will find amplifiers that range from 80dB – 120dB for a SNR. this technology is able to approach this echelon closer than any other previous design. and as a result there is an apparent “hissing” noise at the output. We needed a device with at least a 60 Volt break down voltage and a 50 Amp continuous current limit based on a 1Ω load. Methods by which these elements dissipate power are either conductively or in their AC characteristics. These two factors greatly affect efficiency and follow the following power loss curve as shown in Figure 65. This is discussed in the Background section on efficiency but is important to note that both RDS and QG should be minimized.L. After calculating the appropriate values for these components. Since we found that with higher break down voltage. = Vds * 2 Rds 2 ⎞ ⎤ ⎡ ⎤ Vds ⎟Vds ⎥ * ⎢ ⎥/2 ⎟ RLoad + 2 Rds ⎦ ⎠ ⎦ ⎣ 2 Efficiency = 100 − 100 * 2 Efficiency = 100 − 100 * 2 Ploss Ptotal ( Psw. = ⎢⎜ ⎜R ⎣⎝ Load + 2 Rds C.SwitchingPowerLoss (Gate − Source) = Qg * V gs * f clk = [Watts] 1 SwitchingPowerLoss ( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts ] 2 Conduction( DC ) Loss = VRds * I d / 2 = [Watts] ⎡⎛ 2 Rds C. we needed to send our specifications to a custom winding company for 81 . Other decreases in efficiency are due to the filter components. Losses from either the capacitors or inductors can be calculated using several known equations given throughout this section. g − s + PDC ) ⎛ Vrail ⎜ ⎜ 2* R + R ds load ⎝ ⎞ ⎟ * Rds ⎟ ⎠ 2 2(RLoad + 2 Rds ) Table 6: Power Loss and Efficiency Equations These important specifications are therefore RDS and QG. Figure 65: Power Loss Our decision to select the Fairchild FDP038AN06A0 PowerTrench MOSFET was based on finding the perfect match for our application.L. we chose a MOSFET with a break down voltage at our bare minimum of 60 Volts. RDS increased.d − s + Psw. A primary concern in our filter design was the inductors. Therefore.L.manufacture. In order to calculate the ESR for a given capacitor. 82 .13W (4 + 2(3. Ideally this value would be zero and therefore would have no AC resistance. and load values.1uF )(192kHz ) Figure 66 shows the ideal and actual ESR is not constant and changes greatly with frequency. the total conduction loss can be calculated from the MOSFET. one must start by finding its dissipation factor. this current would peak to 50 Amps at 50 Volts.8mΩ + 20mΩ ))2 Some additional power loss is due to the capacitors. Each inductor had to withstand the same amount of current as each MOSFET. = ⎢⎜ ⎥ ⎟ ⎜R ⎣⎝ Load + 2(RMOSGET + Rinductor ) ⎠ ⎦ ⎣ RLoad + 2(RMOSGET + Rinductor ) ⎦ C. Using a 1Ω resistive load. Now that all the conduction loss resistances are known.L. A perfect capacitor would be lossless and return each bit of energy it had stored. Conduction( DC ) Loss = Vdrop * I d = [Watts] ⎡⎛ ⎤ ⎡ ⎤ ⎞ 2(RMOSFET + Rinductor ) Vrail ⎟Vrail ⎥ * ⎢ C. inductor. impedance of a 0. Using a value of 1% and the following equations. we used capacitors with a dissipation factor of < 1% @ 20°C at 1 kHz.8mΩ + 20mΩ ) = 5. δ= Xc = ESR Xc 1 2πCf ESR = ESR = δ 2πCf .01 = 83mΩ 2π (0. However.01 µF capacitor. we can solve for the ESR at a switching frequency of 192 kHz. above average gauge wire had to be used. the ESR (Equivalent Series Resistance) rating of a capacitor is a particular evaluation of quality given to each series of manufactured devices. In our case. The windings were made with 10 gauge wire and RDC of less than 20mΩ. = (RLoad + 2(RMOSGET + Rinductor ))2 Vrail * 2(RMOSGET + Rinductor ) 2 = 42 2 * 2(3. the power dissipated in the capacitors can be found.01uF Capacitor Impedance28 Using the equations for current and ESR.9 A2 * 83mΩ)16 = 3.1uF ) * (84V ) * (192kHz ) I = 1 . I =C dV dt I = C * ∆V * f O I = (0.4W Figure 67 shows power loss versus dissipation factor. Ideal 0.6 A P = ( I 2 R)*# ofcaps = (12. This is very helpful when determining how much loss is acceptable when selecting capacitors. 83 .Figure 66: Actual vs. 000 400.200.000.000.400.000 800.000 Switching Frequency [Hz] Figure 68: Power Loss vs.000 1.000 2. See Figure 69.000 1. Power Loss vs.Figure 67: Power Loss vs. we have plotted the power loss versus switching frequency since we have a very dynamic range of switching frequencies that may be encountered during audio amplification. Switching Frequency 84 .000 1.000 1.000 600. Switching Frequency 40 35 30 Power Loss [Watts] 25 20 15 10 5 0 0 200.600.000 1. Dissipation Factor Additionally.800. 0% 30. In this case. The efficiency of a constantly switched output is very poor and decreases linearly due to the frequency that the MOSFETs switch.0% Efficiency 60.0% 70. The amount of switching that occurs corresponds to the size of the “dead zone. Conversely.0% 0.0% 40.8%. a small input signal creates the most uncertainty in the output and maximum amount of switching will occur. and filter losses in an amplifier that use Sigma-Delta Modulation.25 3.75 1.00 0. input signal size has an affect on the efficiency.50 0. conduction.Theoretical calculations are extremely difficult for MOSFET switching.50 3. On one extreme.75 2.25 1.00 1. Also.50 1. Efficiency vs.25 0. We decided to plot our actual efficiency results using three different input conditions on the same axis as the predicted results.25 Clock Speed [MHz] Constant Switching Clipped 800Hz Signal Figure 69: Efficiency vs.00 4.0% 80. The first case was an unclipped 800 Hz sine wave. This is due to the fact that the actual number of switches per cycle of an input signal is not known. In this case or any in between. if the input signal is large and the output is clipped. much too large an input will result in clipping and minimal switching.00 3. On the other hand.0% 50.75 3.25 2. the efficiency remains at 99. the number of switches per cycle is not known. Clock Speed 100.0% 0. we have plotted the “ideal” efficiency versus switching frequency in Figure 69 using the equations in Table 5.75 4.50 2.0% 10. The second signal 85 . the MOSFET devices need only to switch twice per cycle.” The “dead-zone” is described in its own section of this report.0% 20. In order to demonstrate this.00 2. Switching Speed The results are as predicted.0% 90. 3.75 3.00 2.50 3. 1.00% 30.6Vin Clipped 800Hz Signal 100% Clipped. This would suggest that much more loss is due to conduction than expected.00 0.00% Efficiency 60.00% 10.00% 0. that value would be 221mΩ solved for in the next few equations.0Vin Figure 70: Efficiency vs. or essentially a square wave. This is plotted in Figure 70. the last was a 100% clipped sine wave.50 0.75 1.was clipped 40% of the time. Finally. Efficiency = Requiv Requiv + RLOAD Requiv = 221mΩ 86 .50 1.00 4.00 1.00% 20.00% 0.00% 70. Clock Speed By analyzing the two simultaneously.00% 50. this would explain the warming of the MOSFET switches at high current.00 3. Clearly something is happening that prevents the measured efficiency from dropping below the theoretical efficiency.00% 80. Clock Speed 100.25 2.50 2. The fact that the output MOSFET switches are not being toggled during each clock tick like in some configurations is not shown here. The only real data that we can abstract is a difference of nearly 5% difference in efficiency between an ideally clipped and actually clipped output. 1. Efficiency vs.00% 40.25 3.4Vin Constant Switching 40% Clipped.75 4.75 2. In fact.25 Clock Speed [MHz] 0% Clipped.25 0.00% 90. we can see that the theoretical efficiency is lower than that obtained.25 1. If this 5% were to be explained by a direct series resistance. Because we had a fairly large budget. 32 Watts of power loss. 87 . we found the components that were most detrimental to our efficiency goals and purchased the best components we could find to reduce efficiency loss. wires without resistance. In summary. and perfect MOSFET switches can not be avoided. would suggest a maximum number of 3.5 million switches per second or 1. These values can be found using Figure 68 The factors mentioned in this section have played a major part of determining the efficiency of our amplifier design. the lack of lossless capacitors.Based on the fact that this amplifier was able to reproduce an unclipped sine wave at 92% efficiency.75 MHz at theoretical conditions. One thing to note is that every integrator added to the circuit creates another pole. the amplifier may be tested at these more extreme levels. This creates a cleaner output. The cleaner sounding output is made by the much higher switching speed of the amplifier. Lastly. crossover. Second. Second. external controls could be implemented into the amplifier. First. or other added features into the amplifier. There are several reasons for this. Therefore if quantization noise can be pushed into the megahertz band. For example a digital keypad could be part of the design where the user could control the volume.6 Recommendations Now that the project is completed. but as you might expect adds a great deal of complexity to the circuit. potentiometers could be used instead of resistors from the input signal to control the volume of the amplifier or to add a high or low-pass crossover. First. This means that the feedback taken from the load would go through several integrators instead of just one. we recognize that there are some things that could have been done differently. This section will focus on ideas that could be implemented into the amplifier to improve upon the existing design. If this was not such a stringent requirement. To balance this. By reducing the impedance of the load. filtering becomes simpler and noise in the audible band is negligible. Typically. an equal number of zeros must be added to keep the system stable. The benefits are numerous as the possibilities of signal processing with DSP are nearly limitless. DSP technology has been a fiercely growing application in audio. Our amplifier was designed to reproduce the full audible bandwidth of 20-20 kHz. a higher ordered Sigma-delta modulator could be used. Class-D amplifiers are not used for full-range audio applications. there is no reason to make the amplifier do more work than it has to. DSP processors are often equipped with multiple analog and digital inputs that may perform other tasks besides Sigma-Delta Modulation. If DSP is not the method of choice. a lower switching speed could be used to further push the efficiency limitations. is that the signal to noise ratio would be much higher. but if the application requires a small frequency bandwidth. Many home entertainment units and even car audio amplifiers now use this technology. The first recommendation if this project is continued is that a DSP chip should be used to control the signal processing. all the components in the amplifier were designed for a 50 Amps maximum current draw. then there are other options as well. With the use of a DSP chip. 88 . There are areas for improvement in all stages of the design. bass boost. resulting in a cleaner sounding output. While the LF356 model chip used in our circuit is widely accepted for many applications. Many parts were used because of their accessibility through the WPI ECE Shop with short notice. The reason for this is because the inductors that were purchased for the project were very costly. Larger bypass capacitors may reduce the noise due to instant current demands and they may also increase stability. Lastly. The first and most immediate impact would be to compare several different operational amplifiers. and higher slew rates. their nonmonetary value may make them worthwhile. it is possible to achieve a phase margin of greater than 45° at a 1Ω load. the risk of noise slipping through is greatly increased. At the very least. the system will become unstable.While the components in our amplifier were designed to be able to run at a 1Ω load. 89 . If information is lost in translation through these devices. By redesigning the filter. Additionally. less jitter. These op-amps would be more able to accurately reproduce high frequency noise which would allow for more noise to be filtered out. a future MQP group could improve our current signal processing circuit in a few ways. a different inductor value would have to have been chosen. While many of these upgrades would cost significantly more money. Capacitors were all special ordered but their values were determined by manufactures’ data sheets only. Many of these technologies boast low-voltage offset. instrumentation amplifiers are available that would replace the need for these resistor packages and op-amp. and in order to push the poles further from each other. It is imperative that these inductors be similarly rated for 50 Amps of current. Resistor packages are available that deviate less than 1% of the measured value and they could be used as input to the instrumentation amplifier or differential feedback attenuator. there are new technologies that deserve to be explored. These include both resistor and capacitor values and ratings. many basic components used in the signal processing portion of the amplifier could be replaced with more finely tuned values. If more time was allowed to be spent on the design of an EMI shield that would double as a heat sink for the amplifier. constructed. The goal was surpassed when the amplifier was tested under a 100% clipped input sine wave. With a dead-zone voltage too high. the amplifier must also maintain a constant power throughout the fluctuations in voltage that will occur in a real-life car application. Our amplifier was capable of driving a 4Ω speaker with a max power of 500 Watts and an RMS power of 400 Watts. it is believed that the amplifier that has been constructed could be marketable with a little more time. The dead-zone voltage that suited the amplifier's purposes the best was 50 mVolts. using a 42 Volt supply. we are pleased to announce that an efficiency of 92% was achieved using a purely sinusoidal input at 800 Hz once again with a 42 Volt supply. making the power to size ratio much higher than that of other amplifiers on the market. With that said. If you are skeptical about using a fully clipped input signal to achieve a maximum efficiency. 90 . At low volumes. the noise coming from the speaker was apparent but as the volume increased the noise became less and less noticeable. The amplifier acted just as intended and the output power did not change more than 3 Watts over the swing in voltage. acoustic clarity gets lost but efficiency goes up. In the audio world.5 MHz would yield the highest efficiency. the amplifier could be located anywhere in an automobile regardless of a vehicle’s central computer location. From the measurements taken of our amplifier.7 Conclusions This project was deemed a success. and tested that met all of the project goals. there is no point in making an amplifier unless the output is an amplified version of the input. The first project goal to mention is the fact that amplifier is capable of reaching 95% efficiency. This would also make the amplifier very marketable. with a really small dead-zone voltage. The amplifier was tested from 48 Volts all the way down to 30 Volts to observe the amplifier's response. The noise is largely due to the tradeoff that is made with the "dead-zone" voltage. The amplifier currently has a footprint size of only 29 square inches. An amplifier was designed. at 800 Hz. For the opposite case. it was determined that a clock speed of 1. Another project goal was to design the amplifier around the 42 PowerNet Standard. acoustic clarity improves but the efficiency suffers. Lastly. Minnesota: MNPERE.html#t7 5 http://www.pdf 10 http://www. p89. 26 Appendix Amplifier research 27 Boylestad. ch15. 1996.ti. Principles of Digital Audio. Pohlmann.com 25 Beranek. p1. New York: McGraw-Hill. 2003 Sedra & Smith.html 6 http://www. p76.html www.html 16 Pohlmann. 1 2 http://www. 19 Sedra & Smith.uk/pwm. 24 www.com/pages/information_center/hdtvfaq.pdf 11 Incropera & DeWitt .net/documents/audio/spdif. Katsuhiko. Interview.com/whats_new/30vauto_nph.edu/content/m10556/latest/> Incropera & DeWitt.com/usesb3. Leominster. Heat Transfer & Metal Properties. 17 See Appendix on Efficiency Calculations 18 Sedra & Smith. Nashelsky. Introduction to Heat Transfer 4th ed. 20 Haag. New Jersey: Prentice Hall. 2002. 1995. Power Electronics and Drives.htm 91 . Understanding Pole/Zero Plots on the Z-Plane.com/appsnotes/APR8-sigma-delta. 2003.8 References Beranek. Leo L. p2-9 15 http://www. pg.com/primers/files/DesignSem3. <http://cnx. Robichaud. p2. pg 253. Inc. 23 Beranek.co. 2002 Mohan. Microelectronic Circuits 4th ed.sci-worx. New York: Oxford University Press. Ned. Prentice Hall.com/html/products/xtant1. L. 3rd ed. New York: John Wiley & Sons. p53 12 Robichaud 13 http://www.tripath. 1992 Haag. 22 Ogata. Boylestad. K. New York: Acoustical Society of America. 2003 9 http://www. July 2003. Michael.com/docs/prod/productfolder.pdf 4 http://skyvision.diamondman. Acoustics.C.xtant. Jon.cfm 3 http://www.jhtml?genericPartNumber=PCM1738 8 Class D Audio Amplifier.com/emi-capacitors.epanorama.4pcb.com/downloads/an11.fairchildsemi.com/internet/bordnetzforum/bnvill.pdf 7 http://focus. 395. 23 Sept.htm 14 Mohan. WPI MQP.cpemma.web-ee. 21 Haag.1i. 28 http://newson-consulting.rice. 1998.numerix-dsp. p154. p539. Modern Control Engineering. Electronic Devices and Circuit Theory. 205 0.97 11.52 13.52 2.18 0.98 11.14 0.58 15.27 2.88 9.32 3.14% 97.47 1.47 2.61 7.65 13.7 24.20 1.60 8. Efficiency Efficiency Efficiency Efficiency Loss Vin=10V.21 8.32% 96.90E+06 4.39% MOSFET Efficiency Calculations 92 .02 2.72E+06 MOSFET Specifications G-S Switching Loss (Watts. Conduction Loss (Watts.60E+06 1.63 1.98 1.86% 0.38% 98.49 17.08% 95.17 22.83 5.40% 98.68 10.182 0.71 18.53 2.13 4.77 11.86 5.58% 97.205 0.37 4.51 2.99 10.34% 98.fclk=1 Loss Vin=10V.11 15.077 6.31% 96.05% 96.40 1. Conduction Loss (Watts. fclk=192kHz) 1Ohm 2Ohm 4Ohm 8Ohm D-S Switching D-S Switching D-S Switching D-S Switching Conduction Loss (Watts.042 0.69 4.20 20.63 1.27% 97.75 3.67 9.65% 98. at Vin Gate Charge (Qg) Pmax (Watts) (25degC) down) Vgs=10V) tON (nsec) tOFF (nsec) Max Switching Speed Fairchild Fairchild Fairchild IRF Fairchild Fairchild Fairchild Fairchild IRF IRF Fairchild IRF FDP038AN06A0 FDP050AN06A0 HUF76443P3 IRFP064V FDP10AN06A0 HUF76445P3 FDP13AN06A0 FDP14AN06LA0 IRFP064 IRFP054 FQP50N06L IRFZ44E 60 60 60 60 60 60 60 60 60 60 60 60 80 80 75 130 75 75 62 61 70 70 52 48 3.52 1.08% 97.047 0.68% 95.88% 97.31 8.333 0.8 5 8 5.70% 96.fclk=1 92kHz) 92kHz) 92kHz) 92kHz) Manufacturer Part # Fairchild Fairchild Fairchild IRF Fairchild Fairchild Fairchild Fairchild IRF IRF Fairchild IRF FDP038AN06A0 FDP050AN06A0 HUF76443P3 IRFP064V FDP10AN06A0 HUF76445P3 FDP13AN06A0 FDP14AN06LA0 IRFP064 IRFP054 FQP50N06L IRFZ44E 0.08 9.31E+06 2.76 1.85 19.06 98.28% 98.18 3. Vin=10V.17 98.37 0.24 2.58 18.87 0.15 0.25 0.29 0.56% 94.37 34.87% 95.60% 97.53% 96.10% 98.20E+06 2.18 98.16% 97.30 0.243 0.72% 96.12 37.56% 97.03% 98.40 4.40% 96.fclk=1 Loss Vin=10V.5 11 9 14 21 23 10 10 10 10 10 10 10 10 10 10 10 10 95 61 107 173.02 5.00 8.67% 97.57% 96.42 0.39 3.fclk=1 Loss Vin=10V.33E+06 2.90 9.238 0.17 1.11 98.54% 97.13 5.92% 97.054 0.78 7.58% 97.22% 97.96E+06 2.046 0.57 0.00E+06 4.5 13.40% 97.21 10.01 5.5 10.78 3.22 0.10 0.66 2.20% 97.60 1.24 16.3 28 124 22 24 126.20 0.96 4.36% 93.11% 97. Conduction Loss (Watts.01 4.52 2.86E+06 3.14% 96.80 4.32 23.17% 98.117 0.64% 98.15 0.25% 97.32% 97.49% 97.76% 0.48 2.71 1.7 106.10E+06 3.48 2.5 40 310 245 260 250 135 310 115 125 300 230 121 110 163 264 195 226 206 205 158 276 211 180 380 72 75 86 100 250 94 295 74 109 300 233 145 140 4.01% 97.62% 1.5 6.90 6.54 5.55 0.81% 97.42E+06 1.39E+06 2.07 2.Appendix Manufacturer Part # Vbrdss Rds Id (break (mOhm.19 20.57 2.94 2.90 9.38 0. 93 . c) Switching Power Loss (Gate-Source) – power loss due to the charging of the gate-source capacitance of the system in order to reach the gate-source voltage. In order to calculate DC loss. = ⎢⎜ ⎜R ⎣⎝ Load + 2 Rds C. we can begin with the equation P=I*V where V is the rail voltage and current is the drain-source current. and switching speed (fclk). we can divide by 2. This can be found by multiplying the gate charge (Qg).L. = Vds * 2 Rds 2 ⎞ ⎤ ⎡ ⎤ Vds ⎟Vds ⎥ * ⎢ ⎥/2 ⎟ RLoad + 2 Rds ⎦ ⎠ ⎦ ⎣ 2 2(RLoad + 2 Rds ) SwitchingPowerLoss(Gate − Source) = Qg * V gs * f clk = [Watts] 1 SwitchingPowerLoss( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts] 2 a) Maximum Switching Speed [Hz] – the fastest a device can switch on and off based on its rise time and fall time. The drain-source current is then the ratio of the rail RLoad + 2 Rds Vds . gate-source voltage (Vgs). RLoad + 2 Rds conduction loss equation can be found in the table above. we can calculate the maximum switching speed by adding the rise and fall times and dividing 1 by this number. p2-9 94 . b) Conduction Loss (DC) [Watts] – power loss due to current flowing from the drain to source of a MOSFET device. The simplified voltage over the total resistance of the MOSFETs and the load. Since we are only concerned with one of the MOSFETS.MOSFET Efficiency Equations Conduction( DC ) Loss = VRds * I d / 2 = [Watts] MaxSwitchingSpeed = 1 = [ Hz ] t rise + t fall ⎡⎛ 2 Rds C. .L. d) Switching Power Loss (Drain-Source) – power loss due to the charging of the drain-source capacitance of the system in order to reach the drain-source voltage. The voltage across each MOSFET is given by the ratio of its resistance relative to 2 Rds the resistance of the load. Equation was taken from Power Electronics and Drives. This equation assumes DC current or current that is steady. Since Hertz is simply the reciprocal of time in seconds. 2500 2000 Max Power [RMS Watts] 1500 1000 500 0 0 25 50 75 100 125 150 Footprint Size [Sq. In] Our Amplifier Competition 175 200 225 250 Competition Best Fit . 5000 2.600 0.5039 8.7300 15.1875 1.S.050 100 90 90 100 100 100 0.3125 2.300 0.7500 11.1 400 MA Audio HK-2000D 1500 MA Audio HK-4000D 3600 MA Audio SY7011DX 1500 MA Audio SY5011DX 1000 MA Audio H2KTP 2000 Memphis MC250D 250 Memphis MC500D 500 Memphis MC100D 1100 Memphis MC1500D 1500 Memphis MC2000D 2400 MTX Thunder251D 160 MTX Thunder311D 200 MTX Thunder421D 300 MTX Thunder801D 500 MTX Thunder1501D 1000 Orion 2500D 2500 Orion 1200D 1200 Orion 600D 600 Phoenix Gold R15.000 100 2.3750 Width (in) 21.1392 134.5000 10.5000 6.6000 186.0000 2.080 90 0.0680 184.7500 9.3500 106.6800 2.5000 6.500 95 1.3125 5.8500 13.0000 22.080 90 0.0000 110.2500 15.7500 20.055 98 0.0000 13.7500 Length (in) 9.2500 2.4000 11.000 0.5000 2.2000 2.000 1.050 90 90 90 100 100 100 80 80 80 80 80 80 90 100 85 .5000 9.3000 9.3500 2.0000 10.3750 149.3800 2.0000 12.1 650 Kicker KX1200.6375 248.000 90 1.000 100 1. Acoustics USX1000D 1250 Xtant X1001 1000 Xtant 1.6772 2.0000 15.7500 10.0000 110.300 0.2000 2.4400 138.3000 2.5673 120.8500 11.7000 5.0000 11.007 120 0.1000 2.3000 2.7500 17.050 0.2500 2.2500 2.7500 11.1 600 Kicker KX400.1000 8.5000 11.0700 13.2500 2.0000 17.000 0.000 96 0.0000 9.000 1.7395 128. Acoustics USX800D 600 U.1000 2.0000 7.0938 156.000 90 0.1250 13. Acoustics USX600D 375 U.5000 2.5500 285.1960 320.6000 6.080 90 0.0000 175.050 0.0000 10.5600 2.3750 11.0000 194.2000 18.4063 214.000 100 1.7813 128.2500 16.3000 11.015 0.6300 2.2500 15.5000 2.6640 194.7000 54.5000 8.0000 2.5981 80.5000 13.6250 12.500 80 0.0:1 2000 Rockford Fosgate Power 1001bd 1000 Rockford Fosgate Power 5001bd 500 Rockford Fosgate Power 1501bd 1500 Sony XM-D1000P5 900 Sony XM-D400PS 400 Soundstream EGA900D 900 Soundstream EGA1400D 1400 Soundstream EGA1700D 1700 U.007 120 0.S.3900 2.4000 12.3900 2.6772 2.3500 2.055 98 0.4000 19.2070 173.6875 14.1395 183.3333 10.1 1200 Kicker KX600.5000 177.7500 9.0000 77.0000 THD S/N Ratio (%) (dB) 1.200 98 0.1666 184.500 98 1.7500 10.5000 19.2500 2.2000 204.1000 2.6000 8.6500 112.500 2.7100 2.5000 2.2500 2.3500 172.0000 91.0000 11.1000 2.0000 11.8500 155.6772 2.1000 2.500 98 1.4600 53.0000 10.6000 87.6000 11.7395 168.4252 21.5039 11.6535 11.000 90 1.1000 2.5000 2.7500 14.750 80 0.7500 9.3800 2.5000 Area (LxW) 210.8750 10.5000 205.050 0.500 80 0.6535 12.500 96 1.7000 16.6797 114.3000 9.3800 2.7500 9.0000 17.2677 8.1000 2.2500 2.8750 9.3900 2.2900 25.7100 2.8600 16.3984 122.0XD 2200 Our Amp 400 Company Model Height (in) 2.2500 2.9375 11.9375 11.6250 29.D Car Audio Amplifier Dimensions Max Total Power (RMS Watts) Alpine MRD-M100 700 Alpine MRD-M500 400 Alpine MRD-M300 200 ArcAudio 1500D-XXK 1000 ArcAudio 1500D-R 1000 Audiobahn A18001DT 1800 Audiobahn A12001DT 1200 Audiobahn A8001DT 800 Autotek MX2000 1200 Autotek MX5000 2200 Boss R1400D 800 Boss R2200D 1400 Boss R3000D 2200 Crossfire VR-300D 300 Crossfire VR-600D 600 Crossfire VR-1000D 1000 Crossfire VR-2000D 2000 Eclipse DA7122 1000 Eclipse DA7232 2000 Kenwood KAC-X810D 800 Kicker SX1250.0000 2.2500 10.4375 14.5000 9.5000 2.5000 11.3398 37.4000 11.0000 9.5000 11.8750 10.050 100 0.0000 8.6000 15.8500 9.5000 2.0000 78.5600 2.8329 170.6875 138.0700 17.6575 2.500 95 1.750 80 0.6000 196.3000 2.6000 165.7650 170.6875 6.0000 11.000 1.000 96 1.3125 78.0700 13.8000 27.1250 9.7244 15.000 96 0.3906 166.6250 67.4000 13.5000 9.7500 9.9000 16.1875 15.1i 100 Zapco C2K-9.300 0.500 90 1.0000 2.0000 10.6563 88.5000 17.6575 2.1 1250 Kicker SX650.9375 8.Class .4375 160.7031 180.8500 11.600 0.3000 9.000 100 1.1000 123.0500 2.5000 10.1000 2.7500 13.2000 179.300 0.0000 199.1000 2.200 100 1.4016 8.8100 8.2000 2.3750 9.5000 6.6250 213.7500 11.7244 9.5000 14.7500 21.5000 14.S.5000 10.5000 10.000 100 1.0500 2.2500 2.080 90 0.0:1 600 Phoenix Gold R30.0000 8.6250 97.4000 16.0:1 1000 Phoenix Gold R8.9063 133.050 100 0.8500 9.9500 130.0000 122.7500 19.0000 22.1250 173.500 95 1.7244 9. . . Although slower than the LM106 and LM710 (200 ns response time vs 40 ns) the devices are also much less prone to spurious oscillations. the positive supply or the negative supply.0 General Description The LM111. Their output is compatible with RTL. LM211 and LM311 are voltage comparators that have input currents nearly a thousand times lower than devices like the LM106 or LM710. over temperature Offset current: 20 nA max.0V/µs to 18V/µs. they can drive lamps or relays.national. switching voltages up to 50V at currents as high as 50 mA. Output is turned off when current is pulled from Strobe Pin. DS005704-39 © 2001 National Semiconductor Corporation DS005704 www. LM211 or the LM311 can be isolated from system ground. Increasing Input Stage Current (Note 1) Detector for Magnetic Transducer DS005704-38 Note 1: Increases typical common mode slew from 7. They are also designed to operate over a wider range of supply voltages: from standard ± 15V op amp supplies down to the single 5V supply used for IC logic.LM111/LM211/LM311 Voltage Comparator January 2001 LM111/LM211/LM311 Voltage Comparator 1. The LM311 has a temperature range of 0˚C to +70˚C. Further. over temperature Differential input voltage range: ± 30V Power consumption: 135 mW at ± 15V 3. 2.0 Features n n n n n Operates from single 5V supply Input current: 150 nA max. The LM211 is identical to the LM111. DTL and TTL as well as MOS circuits. Offset balancing and strobe capability are provided and outputs can be wire OR’ed.0 Typical Applications Offset Balancing (Note 3) Strobing DS005704-36 DS005704-37 Note: Do Not Ground Strobe Pin. except that its performance is specified over a −25˚C to +85˚C temperature range instead of −55˚C to +125˚C. and the output can drive loads referred to ground. The LM111 has the same pin configuration as the LM106 and LM710.com . Both the inputs and the outputs of the LM111. Note 3: Pin connections shown on schematic diagram and typical applications are for H08 metal can package.0 Typical Applications (Note 3) (Continued) Relay Driver with Strobe Digital Transmission Isolator DS005704-40 DS005704-41 *Absorbs inductive kickback of relay and protects IC from severe voltage transients on V++ line. Strobing off Both Input and Output Stages (Note 2) DS005704-42 Note: Do Not Ground Strobe Pin. Note 2: Typical input current is 50 pA with inputs strobed off. Positive Peak Detector Zero Crossing Detector Driving MOS Logic DS005704-24 DS005704-23 *Solid tantalum www.national. Note: Do Not Ground Strobe Pin.LM111/LM211/LM311 3.com 2 . 0 0. The positive input voltage limit is 30V above the negative supply. unless otherwise stated. or 20˚C/W.LM111/LM211/LM311 4. 1. 3 www. please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.1 5. Note 11: Human body model. all temperature specifications are limited to −25˚C≤TA≤+85˚C. however. IOUT =50 mA TA =25˚C TA =25˚C VIN≥5 mV.1 0. while that of the LM211 is 110˚C. The negative input voltage limit is equal to the negative supply voltage or 30V below the positive supply.0 20 150 13.7 TA =25˚C TA =25˚C TA =25˚C TA =25˚C VIN≤−5 mV.national. ESD Rating (Note 11) 300V Electrical Characteristics (Note 6) for the LM111 and LM211 Parameter Input Offset Voltage (Note 7) Input Offset Current Input Bias Current Voltage Gain Response Time (Note 8) Saturation Voltage Strobe ON Current (Note 9) Output Leakage Current Input Offset Voltage (Note 7) Input Offset Current (Note 7) Input Bias Current Input Voltage Range Saturation Voltage Output Leakage Current Positive Supply Current Negative Supply Current V+ =15V.2 5. Note 8: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive.4 V −14.-14. it should be current driven at 3 to 5 mA.5 Max 3.5 kΩ in series with 100 pF.5 13. VOUT =35V TA =25˚C. LM111J and LM111J-8 military specifications. The offset voltage.0 5. V− =0 VIN≤−6 mV. V− =−15V.7 4. junction to ambient. devices in the H08 package must be derated based on a thermal resistance of 165˚C/W. Note 5: The maximum junction temperature of the LM111 is 150˚C.0 Absolute Maximum Ratings for the LM111/LM211(Note 10) If Military/Aerospace specified devices are required. With the LM211. Note 6: These specifications apply for VS = ± 15V and Ground pin at ground. RS≤50k Min Typ 0. junction to case. Pin 7 Pull-Up May Go To 5V V+≥4. these parameters define an error band and take into account the worst-case effects of voltage gain and RS. For operating at elevated temperatures. Note 9: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled.75 1. 10 sec) 260˚C Voltage at Strobe Pin V+−5V Soldering Information Dual-In-Line Package Soldering (10 seconds) 260˚C Small Outline Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. junction to ambient.0 µA mA mA 0. and −55˚C≤TA≤+125˚C. Note 10: Refer to RETS111X for the LM111H.5 6.0 60 200 200 0.com . Do not short the strobe pin to ground.0 10 100 Units mV nA nA V/mV ns V Note 4: This rating applies for ± 15 supplies. Total Supply Voltage (V84) Output to Negative Supply Voltage (V74) Ground to Negative Supply Voltage (V14) Differential Input Voltage Input Voltage (Note 4) Output Short Circuit Duration 36V 50V 30V ± 30V ± 15V 10 sec Operating Temperature Range LM111 −55˚C to 125˚C LM211 −25˚C to 85˚C Lead Temperature (Soldering. VOUT =35V TA =25˚C TA =25˚C 0. Note 7: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1 mA load. Thus. whichever is less.5V.0 mV nA nA V 2.23 0.8.1 4. offset current and bias current specifications apply for any supply voltage from a single 5V supply up to ± 15V supplies. IOUT≤8 mA VIN≥5 mV.0 10 mA nA 40 Conditions TA =25˚C. The thermal resistance of the dual-in-line package is 110˚C/W. ISTROBE =3 mA RS≤50 k 4. Operating Ratings indicate conditions for which the device is functional.75 1.national. Note 19: Human body model.5 13. offset current and bias current specifications apply for any supply voltage from a single 5V supply up to ± 15V supplies. it should be current driven at 3 to 5 mA.5 5. RS≤50k Min Typ 2. devices in the H08 package must be derated based on a thermal resistance of 165˚C/W. junction to case.4 mV nA nA V V 0. but do not guarantee specific performance limits.5 Max 7.LM111/LM211/LM311 5.1 7.0 5.5V. junction to ambient. V− =0 VIN≤−10 mV. The negative input voltage limit is equal to the negative supply voltage or 30V below the positive supply.0 mA mA −14. Do not short the strobe pin to ground.8.2 50 nA 2.com 4 . ISTROBE =3 mA V− = Pin 1 = −5V Input Offset Voltage (Note 16) Input Offset Current (Note 16) Input Bias Current Input Voltage Range Saturation Voltage Positive Supply Current Negative Supply Current V+≥4. IOUT =50 mA TA =25˚C TA =25˚C VIN≥10 mV.−14. Note 14: The maximum junction temperature of the LM311 is 110˚C. Note 15: These specifications apply for VS = ± 15V and Pin 1 at ground. www. 10 sec) 260˚C Voltage at Strobe Pin V+−5V Soldering Information Dual-In-Line Package Soldering (10 seconds) 260˚C Small Outline Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. these parameters define an error band and take into account the worst-case effects of voltage gain and RS. Thus. Note 18: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled. whichever is less.” Note 13: This rating applies for ± 15V supplies.1 4. The positive input voltage limit is 30V above the negative supply.23 RS≤50K 10 70 300 13.5 50 250 Units mV nA nA V/mV ns V Note 12: “Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.7 0.5 kΩ in series with 100 pF. Note 16: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with 1 mA load. and 0˚C < TA < +70˚C.0 Absolute Maximum Ratings for the LM311(Note 12) If Military/Aerospace specified devices are required. For operating at elevated temperature.0 mA 40 Conditions TA =25˚C. Total Supply Voltage (V84) Output to Negative Supply Voltage (V74) Ground to Negative Supply Voltage (V14) Differential Input Voltage Input Voltage (Note 13) Power Dissipation (Note 14) ESD Rating (Note 19) Output Short Circuit Duration 36V 40V 30V ± 30V ± 15V 500 mW 300V 10 sec Operating Temperature Range 0˚ to 70˚C Storage Temperature Range −65˚C to 150˚C Lead Temperature (soldering. Note 17: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive. junction to ambient. The thermal resistance of the dual-in-line package is 100˚C/W.0 6. unless otherwise specified. Electrical Characteristics (Note 15) for the LM311 Parameter Input Offset Voltage (Note 16) Input Offset Current(Note 16) Input Bias Current Voltage Gain Response Time (Note 17) Saturation Voltage Strobe ON Current (Note 18) Output Leakage Current TA =25˚C TA =25˚C TA =25˚C TA =25˚C VIN≤−10 mV.0 0.0 100 200 200 0. please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. The offset voltage. 1. VOUT =35V TA =25˚C. or 20˚C/W. IOUT≤8 mA TA =25˚C TA =25˚C 5. national.com .LM111/LM211/LM311 6.0 LM111/LM211 Typical Performance Characteristics Input Bias Current Input Bias Current DS005704-43 DS005704-44 Input Bias Current Input Bias Current DS005704-46 DS005704-45 Input Bias Current Input Bias Current DS005704-47 DS005704-48 5 www. 0 LM111/LM211 Typical Performance Characteristics Input Bias Current Input Overdrives Input Bias Current Input Overdrives (Continued) DS005704-49 DS005704-50 Input Bias Current Response Time for Various Input Overdrives DS005704-51 DS005704-52 Response Time for Various Input Overdrives Output Limiting Characteristics DS005704-54 DS005704-53 www.LM111/LM211/LM311 6.com 6 .national. com .0 LM111/LM211 Typical Performance Characteristics Supply Current Supply Current (Continued) DS005704-55 DS005704-56 Leakage Currents DS005704-57 7.national.0 LM311 Typical Performance Characteristics Input Bias Current Input Offset Current DS005704-58 DS005704-59 7 www.LM111/LM211/LM311 6. national.LM111/LM211/LM311 7.0 LM311 Typical Performance Characteristics Offset Error (Continued) Input Characteristics DS005704-60 DS005704-61 Common Mode Limits Transfer Function DS005704-62 DS005704-63 Response Time for Various Input Overdrives Response Time for Various Input Overdrives DS005704-64 DS005704-65 www.com 8 . national.com .0 LM311 Typical Performance Characteristics Output Saturation Voltage (Continued) Response Time for Various Input Overdrives DS005704-66 DS005704-67 Response Time for Various Input Overdrives Output Limiting Characteristics DS005704-69 DS005704-68 Supply Current Supply Current DS005704-70 DS005704-71 9 www.LM111/LM211/LM311 7. and that the output signal is routed well away from the inputs (pins 2 and 3) and also away from pins 5 and 6. the feedback from the output to the positive input will cause about 3 mV of hysteresis.) It is a standard procedure to use hysteresis (positive feedback) around a comparator. When comparator circuits use input resistors (eg. the printed-circuit layout should be engineered thoughtfully.01 µF capacitor C1 between pins 5 and 6 will minimize the susceptibility to AC coupling. The power supply bypass capacitors should be located within a couple inches of the LM111. pots. the trim-pot should be located. if RS =10 kΩ. etc. For example. Preferably there should be a groundplane under the LM111 circuitry. and should be essentially surrounded by ground foil on all sides. to prevent oscillation. but it is rather awkward. RS.0 LM311 Typical Performance Characteristics Leakage Currents (Continued) DS005704-72 8. they should be shorted together. . However. The foil connections for the inputs should be as small and compact as possible. to guard against capacitive coupling from any high-level signals (such as the output). If pins 5 and 6 are not used. If this capacitor cannot be used.1 µF disc capacitors). or if the signal source impedance is high (1 kΩ to 100 kΩ). they should be shorted together. If these pins are not connected to a trim-pot. their value and placement are particularly important. 3. If they are connected to a trim-pot. The trim pins (pins 5 and 6) act as unwanted auxiliary inputs. one side of a double-layer circuit card.01 µF capacitor should be installed. positive supply or negative supply foil) should extend between the output and the inputs. Since feedback to almost any pin of a comparator can result in oscillation. at most. and the 0. assuming that the power supplies have been bypassed (with 0. Certain sources will produce a cleaner comparator output waveform if a 100 pF to 1000 pF capacitor C2 is connected directly across the input pins. as shown in Figure 1 below. Carbon. a shielding printed-circuit foil may be advisable between pins 6 and 7.national. to act as a guard. it is usually advantageous to choose an RS' of substantially the same value. a few inches away from the LM111. See the notes in paragraph 7 below.LM111/LM211/LM311 7. the comparator may burst into oscillation near the crossing-point. as little as 5 inches of lead between the resistors and the input pins can result www. Inductive wirewound resistors are not suitable. in oscillations that are very hard to damp. Ground foil (or. a 0. the output response will normally be fast and stable. 2. and to avoid excessive noise on the output because the comparator is a good amplifier for its own noise. The same applies to capacitors. for example. 4. A smaller capacitor is used if pin 5 is used for positive feedback as in Figure 1. This is due to the high gain and wide bandwidth of comparators like the LM111. In other words there should be very little lead length or printed-circuit foil run between comparator and resistor to radiate or pick up signals. 1. In all cases the body of the resistor should be close to the device or socket. both for DC and for dynamic (AC) considerations. To avoid oscillation or instability in such a usage.1 CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS When a high-speed comparator such as the LM111 is used with fast input signals and low source impedances. In the circuit of Figure 2. (Some other comparators require the power-supply bypass to be located immediately adjacent to the comparator. such as 50 kΩ. If they are connected to a trim-pot. several precautions are recommended. tin-oxide. Twisting these input leads tightly is the only (second best) alternative to placing resistors close to the comparator.com 10 5. The circuit of Figure 3 could be used. summing resistors). if RS is larger than 100Ω.0 Application Hints 8. and metal-film resistors have all been used successfully in comparator input circuitry. 6. it would not be reasonable to simply increase the value of the positive feedback resistor above 510 kΩ. When the signal source is applied through a resistive network. However. when the input signal is a voltage ramp or a slow sine wave. This signal is centered around the nominal voltage at pin 5.com . the circuit of Figure 1 is ideal. 8. (with the exception that not all comparators have trim pins). so this feedback does not add to the VOS of the comparator. (Continued) When both inputs of the LM111 are connected to active signals.national. The positive feedback is to pin 5 (one of the offset adjustment pins).0 Application Hints 7. The positive-feedback signal across the 82Ω resistor swings 240 mV below the posi- tive supply.LM111/LM211/LM311 8. These application notes apply specifically to the LM111. or if a high-impedance signal is driving the positive input of the LM111 so that positive feedback would be disruptive. As much as 8 mV of VOS can be trimmed out. and are applicable to all high-speed comparators in general. LM311. using the 5 kΩ pot and 3 kΩ resistor as shown. DS005704-29 Pin connections shown are for LM111H in the H08 hermetic package FIGURE 1. It is sufficient to cause 1 to 2 mV hysteresis and sharp transitions with input triangle waves from a few Hz to hundreds of kHz. Conventional Positive Feedback 11 www. LM211. and LF111 families of comparators. Improved Positive Feedback DS005704-30 Pin connections shown are for LM111H in the H08 hermetic package FIGURE 2. com 12 . Positive Feedback with High Source Resistance 9.LM111/LM211/LM311 8.0 Application Hints (Continued) DS005704-31 FIGURE 3.0 Typical Applications (Pin numbers refer to H08 package) 100 kHz Free Running Multivibrator Zero Crossing Detector Driving MOS Switch DS005704-13 DS005704-14 *TTL or DTL fanout of two www.national. †May be added to control speed and reduce susceptibility to noise spikes.national. TTL Interface with High Level Logic DS005704-18 *Values shown are for a 0 to 30V logic swing and a 15V threshold.0 Typical Applications (Pin numbers refer to H08 package) (Continued) 10 Hz to 10 kHz Voltage Controlled Oscillator DS005704-15 *Adjust for symmetrical square wave time when VIN = 5 mV †Minimum capacitance 20 pF Maximum frequency 50 kHz Driving Ground-Referred Load Using Clamp Diodes to Improve Response DS005704-17 DS005704-16 *Input polarity is reversed when using pin 1 as output.com .LM111/LM211/LM311 9. 13 www. com 14 .0 Typical Applications Crystal Oscillator (Pin numbers refer to H08 package) (Continued) Comparator and Solenoid Driver DS005704-20 DS005704-19 Precision Squarer DS005704-21 *Solid tantalum †Adjust to set clamp level www.national.LM111/LM211/LM311 9. national.com .0 Typical Applications (Pin numbers refer to H08 package) (Continued) Low Voltage Adjustable Reference Supply DS005704-22 *Solid tantalum Positive Peak Detector Zero Crossing Detector Driving MOS Logic DS005704-24 DS005704-23 *Solid tantalum Negative Peak Detector DS005704-25 *Solid tantalum 15 www.LM111/LM211/LM311 9. com 16 .LM111/LM211/LM311 9. At comparison.national. Switching Power Amplifier DS005704-27 www. the photodiode has less than 5 mV across it. decreasing leakages by an order of magnitude.0 Typical Applications (Pin numbers refer to H08 package) (Continued) Precision Photodiode Comparator DS005704-26 *R2 sets the comparison level. national.com .LM111/LM211/LM311 9.0 Typical Applications (Pin numbers refer to H08 package) (Continued) Switching Power Amplifier DS005704-28 17 www. www.0 Schematic Diagram (Note 20) DS005704-5 Note 20: Pin connections shown on schematic diagram are for H08 package.national.com 18 .LM111/LM211/LM311 10. com . LM111WG/883 See NS Package Number W10A. M08A or N08E DS005704-35 Top View Order Number LM111J/883(Note 21) See NS Package Number J14A or N14A DS005704-33 Order Number LM111W/883(Note 21).LM111/LM211/LM311 11. LM111J-8/883(Note 21). WG10A Note 21: Also available per JM38510/10304 19 www. LM311MX or LM311N See NS Package Number J08A. LM111H/883(Note 21) . LM211H or LM311H See NS Package Number H08C Dual-In-Line Package Dual-In-Line Package DS005704-34 Top View Order Number LM111J-8.0 Connection Diagrams Metal Can Package DS005704-6 Note: Pin 4 connected to case Top View Order Number LM111H.national. LM311M. LM211H or LM311H NS Package Number H08C Cavity Dual-In-Line Package (J) Order Number LM111J-8.national.com 20 . LM111H/883. LM111J-8/883 NS Package Number J08A www.LM111/LM211/LM311 12.0 Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) Order Number LM111H. LM111/LM211/LM311 12.0 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Dual-In-Line Package (J) Order Number LM111J/883 NS Package Number J14A Dual-In-Line Package (M) Order Number LM311M.com . LM311MX NS Package Number M08A 21 www.national. com 22 . WG10A www.LM111/LM211/LM311 12. LM111WG/883 NS Package Number W10A.0 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Dual-In-Line Package (N) Order Number LM311N NS Package Number N08E Order Number LM111W/883.national. support@nsc. no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. (a) are intended for surgical implant into the body.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] National Semiconductor Japan Ltd. or to affect its safety or effectiveness. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc. can be reasonably expected to result in a significant injury to the user.LM111/LM211/LM311 Voltage Comparator Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.com www. . and whose failure to perform when properly used in accordance with instructions for use provided in the labeling.national. or (b) support or sustain life. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. Life support devices or systems are devices or systems which. As used herein: 1. . . . . . . . . FDP038AN06A0 / FDI038AN06A0 August 2002 FDP038AN06A0 / FDI038AN06A0 N-Channel PowerTrench® MOSFET 60V, 80A, 3.8mΩ Features • r DS(ON) = 3.5mΩ (Typ.), V GS = 10V, ID = 80A • Qg(tot) = 95nC (Typ.), VGS = 10V • Low Miller Charge • Low QRR Body Diode • UIS Capability (Single Pulse and Repetitive Pulse) • Qualified to AEC Q101 Formerly developmental type 82584 Applications • Motor / Body Load Control • ABS Systems • Powertrain Management • Injection Systems • DC-DC converters and Off-line UPS • Distributed Power Architectures and VRMs • Primary Switch for 12V and 24V systems DRAIN (FLANGE) SOURCE DRAIN SOURCE DRAIN GATE GATE D G DRAIN (FLANGE) TO-220AB FDP SERIES TO-262AB FDI SERIES S MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC < 151oC, VGS = 10V) Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 62oC/W) Pulsed E AS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 80 17 Figure 4 625 310 2.07 -55 to 175 A A A mJ W W/oC o Ratings 60 ±20 Units V V C Thermal Characteristics RθJC RθJA Thermal Resistance Junction to Case TO-220, TO-262 Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2) 0.48 62 o o C/W C/W This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. A1 FDP038AN06A0 / FDI038AN06A0 Package Marking and Ordering Information Device Marking FDP038AN06A0 FDI038AN06A0 Device FDP038AN06A0 FDI038AN06A0 Package TO-220AB TO-262AB Reel Size Tube Tube Tape Width N/A N/A Quantity 50 units 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics B VDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 50V VGS = 0V VGS = ±20V TC = 150oC 60 1 250 ±100 V µA nA On Characteristics VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA ID = 80A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 40A, VGS = 6V ID = 80A, VGS = 10V, TJ = 175oC 2 4 V Ω 0.0035 0.0038 0.0049 0.0074 0.0071 0.0078 Dynamic Characteristics CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain “Miller” Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 30V ID = 80A Ig = 1.0mA 6400 1123 367 95 12 30 18 24 124 15 pF pF pF nC nC nC nC nC Switching Characteristics (VGS = 10V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 30V, ID = 80A VGS = 10V, RGS = 2.4Ω 15 93 38 13 163 75 ns ns ns ns ns ns Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 80A ISD = 40A ISD = 75A, dISD/dt = 100A/µs ISD = 75A, dISD/dt = 100A/µs 1.25 1.0 38 39 V V ns nC Notes: 1: Starting TJ = 25°C, L = 0.255mH, IAS = 70A. 2: Pulse Width = 100s ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. A1 01 Figure 2.01 10-5 10-4 Figure 3.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-3 10-2 t.6 100 0.5 0.TC 150 1000 IDM. Normalized Maximum Transient Thermal Impedance 3000 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 100 175 .4 0.2 250 CURRENT LIMITED BY PACKAGE POWER DISSIPATION MULTIPLIER 1. Maximum Continuous Drain Current vs Case Temperature ZθJC.2 0.0 ID.FDP038AN06A0 / FDI038AN06A0 Typical Characteristics TC = 25°C unless otherwise noted 1.8 150 0. CASE TEMPERATURE Figure 1. PEAK CURRENT (A) 10 10-5 10-4 10-3 10-2 t. Peak Current Capability ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev.1 0. RECTANGULAR PULSE DURATION (s) 10-1 100 101 SINGLE PULSE 0.DESCENDING ORDER 0.2 50 0 0 25 50 75 100 125 150 175 TC . NORMALIZED THERMAL IMPEDANCE PDM 0. A1 . Normalized Power Dissipation vs Ambient Temperature 2 1 DUTY CYCLE .05 0. PULSE WIDTH (s) 10-1 100 101 Figure 4. DRAIN CURRENT (A) 200 0. CASE TEMPERATURE (o C) 0 25 50 75 100 125 (o C) 150 175 TC.02 0. 0 5.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0. DRAIN CURRENT (A) ID .3*RATED BVDSS . DRAIN CURRENT (A) 60 80 VGS = 10V. TIME IN AVALANCHE (ms) 100 0. Drain to Source On Resistance vs Drain Current Figure 10.01 0. DRAIN TO SOURCE VOLTAGE (V) DC If R = 0 tAV = (L)(I AS)/(1.5% MAX VGS = 6V 5 Figure 8. A1 .5 4 1.1 100 Figure 5.0 4. ID =80A 0. DRAIN CURRENT (A) 120 120 VGS = 6V VGS = 5V 80 80 TJ = 175 oC 40 TJ = 25o C TJ = -55 C o 40 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 TC = 25o C 1. Unclamped Inductive Switching Capability 160 VGS = 20V VGS = 10V 160 PULSE DURATION = 80µs DUTY CYCLE = 0. DRAIN TO SOURCE VOLTAGE (V) Figure 7.FDP038AN06A0 / FDI038AN06A0 Typical Characteristics TC = 25°C unless otherwise noted 2000 1000 100µs ID.0 1.5 4. Transfer Characteristics 6 DRAIN TO SOURCE ON RESISTANCE(mΩ) 2.5 0 3.VDD) +1] 1 0. Saturation Characteristics PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.1 1 10 tAV. JUNCTION TEMPERATURE (oC) 200 Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. GATE TO SOURCE VOLTAGE (V) 6 0 0.0 VGS = 10V 3 0 20 40 ID. AVALANCHE CURRENT (A) STARTING TJ = 25oC 10µs 100 STARTING TJ = 150oC 10 10 10ms 1 SINGLE PULSE TJ = MAX RATED TC = 25o C 1 10 VDS.0 VDS .5% MAX VDD = 15V ID.5 VGS . Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6.5 5.0 3.VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS .5 1. DRAIN CURRENT (A) 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) IAS.5 -80 -40 0 40 80 120 160 TJ. 1 0.0 1.FDP038AN06A0 / FDI038AN06A0 Typical Characteristics TC = 25°C unless otherwise noted 1. GATE CHARGE (nC) 75 100 2 VGS = 0V.4 0.9 -80 -40 0 40 80 120 160 200 TJ . GATE TO SOURCE VOLTAGE (V) VDD = 30V 8 CISS = CGS + CGD C. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS . Capacitance vs Drain to Source Voltage Figure 14.2 -80 -40 0 40 80 120 160 200 TJ.4 VGS = VDS. DRAIN TO SOURCE VOLTAGE (V) 0 Figure 13.2 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.8 0.0 0. f = 1MHz 100 0.6 1. Normalized Gate Threshold Voltage vs Junction Temperature 10000 Figure 12. JUNCTION TEMPERATURE (oC) 0.2 ID = 250µA 1. Gate Charge Waveforms for Constant Gate Current ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. I D = 250µA 1.1 1 10 60 VDS . CAPACITANCE (pF) COSS ≅ C DS + C GD 6 1000 CRSS = CGD 4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 40A 0 25 50 Qg . JUNCTION TEMPERATURE (o C) Figure 11. A1 . 01Ω 0 tAV Figure 15. Switching Time Waveforms ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. Unclamped Energy Waveforms VDS VDD L VGS VDS Qg(TOT) VGS VGS = 10V + VDD DUT Ig(REF) VGS = 2V 0 Qgs2 Qg(TH) Qgs Ig(REF) 0 Qgd Figure 17. Switching Time Test Circuit Figure 20. A1 . Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 90% 50% Figure 19. Gate Charge Test Circuit Figure 18. Unclamped Energy Test Circuit Figure 16.FDP038AN06A0 / FDI038AN06A0 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS + IAS 0. 7e-9 IS=1e-30 N=10 M=0.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0. CA S1A 12 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 GATE 1 RLGATE CIN 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE RBREAK 18 RVTEMP 19 VBAT + 22 7 SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED LDRAIN DPLCAP 5 DRAIN 2 RSLC2 5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 - ©2002 Fairchild Semiconductor Corporation + DBODY FDP038AN06A0 / FDI038AN06A0 Rev.MODEL MstroMOD NMOS (VTO=4.65e-3 TRS1=2.MODEL DbodyMOD D (IS=2.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 T_abs=25) .MODEL MweakMOD NMOS (VTO=2.9) .5e-3 TC2=1e-6) .51)/(1e-6*250).5 VOFF=-4) .MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5) .3 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 4.63e-9 RLgate 1 9 48. A1 . 1991.04 RS=1.1 VON=-1 VOFF=0.5) . written by William J. Frank Wheatley.8e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.MODEL RvthresMOD RES (TC1=-6.36 T_abs=25) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 69.MODEL MmedMOD NMOS (VTO=3.4e-1 TT=1e-9 XTI=3.ENDS Note: For further discussion of the PSPICE model.36 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.9e-6) .5) .00 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u T_abs=25) .10))} . IEEE Power Electronics Specialist Conference Records.MODEL RvtempMOD RES (TC1=-2.MODEL DbreakMOD D (RS=1.1 VON=-1.51)))*(PWR(V(5.3 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.MODEL DplcapMOD D (CJO=1.MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6) .5 VOFF=-1) .5e-5) .5e-9 Cin 6 8 6.5e-9 Cb 15 14 1.35e-9 M=5.51)/ABS(V(5.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.FDP038AN06A0 / FDI038AN06A0 PSPICE Electrical Model .MODEL RdrainMOD RES (TC1=4e-2 TC2=3e-4) .1 RLdrain 2 5 10 RLsource 3 7 46.4E-11 N=1.7e-3 TC2=-1. rev July 04.MODEL RbreakMOD RES (TC1=9e-4 TC2=-9e-7) . Hepp and C.6 RS=0.1 VON=0.47) .1 VON=-4 VOFF=-1.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.7e-3 TRS2=2e-7 + CJO=4.SUBCKT FDP038AN06A0 2 1 3 .5e-1 TRS1=1e-3 TRS2=-8. 2002 Ca 12 8 1. consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1e-4 Rgate 9 20 1. .rbreak n17 n18 = 1.1.n51)/(1e-9+abs(v(n5.kp=9.5e-3. tc1=-2.rs=1. w=1u res.model mstrongmod = (type=_n.roff=0.1 res. w=1u m.8e-3.1. l=1u.rvtemp n18 n19 = 1.1.n3 number m_temp=25 { var i iscl dp.n51))))*((abs(v(n5.is=1e-30.7e-9.tc2=-9e-7 res.m=0. tc1=9e-4. w=1u m..cjo=4.dbreak n5 n11 = model=dbreakmod dp.cin n6 n8 = 6.rlgate n1 n9 = 48.model s2amod = (ron=1e-5.dplcap n10 n5 = model=dplcapmod spe.3 GATE 1 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 RDRAIN EVTHRES + 19 8 6 MSTRO CIN 8 21 16 11 DBODY MWEAK MMED RLGATE EBREAK + 17 18 - LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 m.mmed n16 n6 n8 n8 = model=mmedmod.trs2=2e-7.mweak n16 n21 n8 n8 = model=mweakmod.0e-9 l.81e-9 l.5.4e-1. A1 .model dbodymod = (isl=2.is=1e-30.n50) = ((v(n5.n1. l=1u.egs n13 n8 n6 n8 = 1 spe.9) dp.5.model s1bmod = (ron=1e-5.72.is=1e-30.tc2=1e-6 res. tox=1) m.vto=4.ebreak n11 n7 n17 n18 = 69.mstrong n16 n6 n8 n8 = model=mstrongmod.5e-1. tc1=4e-2.tt=1e-9.03.model s1amod = (ron=1e-5.1e-9 DBREAK 50 - dp. temp=m_temp.eds n14 n8 n5 n8 = 1 spe... tc1=-6. temp=m_temp.model dplcapmod = (cjo=1..kp=0.rsource n8 n7 = 2.n1.tc2=-1.ca n12 n8 = 1. tox=1.voff=-1) RSLC2 c.esg n6 n10 n6 n8 = 1 spe.rlsource n3 n7 = 46.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.roff=0.5e-9 ISCL c.5) 2 10 sw_vcsp.7e-3.dbody n7 n5 = model=dbodymod dp.rslc2 n5 n50 = 1e3 res. tox=1) LDRAIN m.trs1=2.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51.m=5.rldrain n2 n5 = 10 res..n51)*1e6/250))** 10)) } ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev.kp=275.04.lsource n3 n7 = 4.FDP038AN06A0 / FDI038AN06A0 SABER Electrical Model rev July 4.rs=0.model s2bmod = (ron=1e-5.35e-9.. 2002 template FDP038AN06A0 n2.cb n15 n14 = 1.roff=0.model mweakmod = (type=_n.isl=10e-30.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.5e-9 c.nl=1.rslc1 n5 n51 = 1e-6.rdrain n50 n16 = 1e-4.voff=0.lgate n1 n9 = 4.3..47) m.4e-11.xti=3.65e-3.tc2=1e-5 res.n3 = m_temp electrical n2.rvthres n22 n8 = 1.voff=-4) RLDRAIN sw_vcsp.00.von=0.36 res.9e-6) dp.tc2=1e-6 sw_vcsp. tc1=5e-3.evthres n6 n21 n19 n8 = 1 spe.rgate n9 n20 = 1. tc1=1e-3.model dbreakmod = (rs=1.von=-1.vto=2..s2b n13 n15 n14 n13 = model=s2bmod v. l=1u.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.model mmedmod = (type=_n..voff=-1.5e-5 res.7e-3.von=-4. temp=m_temp.roff=0.von=-1.tc2=3e-4 res.1.63e-9 res.trs1=1e-3.5) RSLC1 51 sw_vcsp.trs2=-8.1) DPLCAP 5 DRAIN sw_vcsp.3 spe.vto=3.ldrain n2 n5 = 1.nl=10. 45e-3 CTHERM2 6 5 3e-2 CTHERM3 5 4 1. A1 .85e-2 ctherm.24e-3 rtherm.4e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.28e-2 rtherm.45e-3 ctherm.rtherm3 5 4 =2.ctherm2 6 5 =3e-2 ctherm.ctherm3 5 4 =1.rtherm2 6 5 =8.08e-3 rtherm.rtherm4 4 3 =1e-1 rtherm.4e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE ©2002 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev.85e-2 CTHERM6 2 TL 1e-1 RTHERM1 TH 6 3. tl { ctherm.rtherm6 2 tl=1.FDP038AN06A0 / FDI038AN06A0 PSPICE Thermal Model REV 23 July 4.1e-1 RTHERM6 2 TL 1.rtherm1 th 6 =3.rtherm5 3 2 =1.65e-2 ctherm.ctherm6 2 tl =1e-1 rtherm.ctherm5 3 2 =4.4e-2 ctherm.1e-1 rtherm.ctherm1 th 6 =6. 2002 FDP038AN06A0T CTHERM1 TH 6 6.28e-2 RTHERM4 4 3 1e-1 RTHERM5 3 2 1.08e-3 RTHERM3 5 4 2.4e-1 th JUNCTION RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP035AN06A0T template thermal_model th tl thermal_c th.ctherm4 4 3 =1.24e-3 RTHERM2 6 5 8. TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. NOR THE RIGHTS OF OTHERS. Specifications may change in any manner without notice. I1 . The datasheet is printed for reference information only. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. FUNCTION OR DESIGN.™ The Power Franchise™ Programmable Active Droop™ DISCLAIMER ImpliedDisconnect™ PACMAN™ POP™ ISOPLANAR™ Power247™ LittleFET™ PowerTrenchâ MicroFET™ QFET™ MicroPak™ QS™ MICROWIRE™ QT Optoelectronics™ MSX™ Quiet Series™ MSXPro™ RapidConfigure™ OCX™ RapidConnect™ OCXPro™ SILENT SWITCHERâ OPTOLOGICâ SMART START™ OPTOPLANAR™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFETâ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. This datasheet contains preliminary data. or (c) whose support device or system. reasonably expected to result in significant injury to the user. or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. Around the world. NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS. can be effectiveness. ACEx™ FACT™ ActiveArray™ FACT Quiet Series™ Bottomless™ FASTâ CoolFET™ FASTr™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ Across the board. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. A critical component is any component of a life 1. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. and supplementary data will be published at a later date. Life support devices or systems are devices or support device or system whose failure to perform can systems which. (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body. or (b) support or sustain life. includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate “hysteresis mode” switching. NO. For example. All Rights Reserved All other trademarks mentioned are the property of their respective owners. The HIP4081A can switch at frequencies up to 1MHz and is well suited to driving Voice Coil Motors. 2003. the HIP4080A. follow proper IC Handling Procedures. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion. High Frequency Full Bridge FET Driver The HIP4081A is a high frequency.6 80V/2. and two HIP4081As can be used to drive high performance stepper motors. Features • Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations • Bootstrap Supply Max Voltage to 95VDC • Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns • User-Programmable Dead Time • On-Chip Charge-Pump and Bootstrap Upper Bias Supplies • DIS (Disable) Overrides Input Control • Input Logic Thresholds Compatible with 5V to 15V Logic Levels • Very Low Power Consumption • Undervoltage Protection Applications • Medium/Large Voice Coil Motors • Full Bridge Power Supplies • Switching Power Amplifiers • High Performance Motor Controls • Noise Cancellation Systems Ordering Information PART NUMBER HIP4081AIP HIP4081AIB TEMP RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld PDIP 20 Ld SOIC (W) PKG.® HIP4081A Data Sheet February 2003 FN3659. and power supplies. SOIC) TOP VIEW BHB BHI DIS VSS BLI ALI AHI HDEL LDEL 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 BHO BHS BLO BLS VDD VCC ALS ALO AHS AHO AHB 10 1 CAUTION: These devices are sensitive to electrostatic discharge. precise control of the driven load. A similar part. E20.3 M20. The HIP4081A can drive every possible switch combination except those which would cause a shoot-through condition. resulting in rapid. medium voltage Full Bridge N-Channel FET driver IC. Pinout HIP4081A (PDIP.3 • Battery Powered Vehicles • Peripherals • U. since the short minimum “on-time” can provide fine micro-stepping capability.S. the HIP4081A can drive medium voltage brush motors. available in 20 lead plastic SOIC and DIP packages. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. . The Application Note for the HIP4081A is the AN9405.5A Peak. high-frequency switching power amplifiers. Copyright © Intersil Americas Inc.P. HIP4081A Application Block Diagram 80V 12V BHO BHS BHI BLI HIP4081A ALI AHI ALO AHS AHO BLO LOAD GND GND Functional Block Diagram (1/2 HIP4081A) AHB 10 HIGH VOLTAGE BUS ≤ 80VDC UNDERVOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER 11 AHO CBS AHS 12 VDD 16 AHI 7 TURN-ON DELAY DBS DIS 3 15 VCC TO VDD (PIN 16) DRIVER ALI 6 TURN-ON DELAY 13 ALO CBF +12VDC BIAS SUPPLY ALS 14 HDEL LDEL VSS 8 9 4 2 . HIP4081A Typical Application (PWM Mode Switching) 80V 1 BHB HIP4081/HIP4081A 12V DIS PWM INPUT 2 BHI 3 DIS 4 VSS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11 12V LOAD GND TO OPTIONAL CURRENT CONTROLLER + 6V GND 3 . . . . . . . . . .1 1. . .5 0. . . Thermal Information Thermal Resistance (Typical. . . . .VAHS. . . . . BHS . . . . -1.5V to +15V Voltage on ALS. . . . . .1 V V A 4 . .4 V GATE DRIVER OUTPUT PINS: ALO. . BLS . . . . . . .2 4. .7 0.5 1 -50 0. . . .8 -65 +10 V V mV µA µA TURN-ON DELAY PINS: LDEL AND HDEL LDEL.4 1.6 14. . BHS +15V Input Current. . IALO = IBLO = 0 f = 500kHz. . . -65oC to 150oC Operating Max. . Note 1) θJA (oC/W) SOIC Package. . . .5 0. . BHI. . . . . . . . . RHDEL = RLDEL = 100K and TA = 25oC. . . .5 mA mA µA mA µA mA µA V INPUT PINS: ALI. . . . . . . . Full Operating Conditions VIL VIH Full Operating Conditions Full Operating Conditions 2.0 14. .6 1. .5 12. . . . . . . No Load 8. . BHB +0. .0V (Transient) to +2. .7 0. . . BHS +5V to VAHS. . . . . . . . NOTE: 1. VAHS. . . . . . Electrical Specifications VDD = VCC = VAHB = VBHB = 12V. . . . . BHB . . . . -0.0V (Transient) to 70V (-55oC to 125oC) Voltage on ALS. . .7 -135 -10 0. . . . . . . . . . . . . . . . . VAHS. . . . . unless otherwise specified. .5 1. . .5 15.95 2. -5mA to 0mA Phase Slew Rate . . . . .0 -75 +1 2. 300oC (For SOIC . . BHB Quiescent Current Qpump Output Current AHB. . . . θJA is measured with the component mounted on an evaluation PC board in free air. . . . . . . . -2. . . BHB Leakage Current AHB-AHS. . This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.5 9. . . . .5 15. . . BHS -0. . . BLS -0. +9.5 10.2 0.1 3. . . . BLO. .5 0. . . . . . . BHB-BHS Qpump Output Voltage IDD IDDO ICC ICCO IAHB. . .8 5. . . . . . .8 1. . . . . . . -6. BHB Operating Current AHS. . . IBHBO IHLK VAHB-VAHS VBHB-VBHS All inputs = 0V Outputs switching f = 500kHz All Inputs = 0V. . IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V f = 500kHz. . Full Operating Conditions VIN = 5V. BHS -0.1 1. . . . . .85 0. . .3V to VCC +0. VDD and VCC .9 10 14. . . . . .5 1. . BLS . . . . .8 0. . . -6. . . VDD and VCC . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. 85 DIP Package . No Load All Inputs = 0V. . .6 11.5 10 2. . .5 8. HDEL and LDEL . .3V to VAHS.3 4. . .0V (Transient) Voltage on AHB. . .0 1. AND DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current IIL IIH VIN = 0V. . .0V (Transient) to 80V (25oC to 125oC) Voltage on AHS. Unless Otherwise Specified TJ = 25 C o TJS = -40oC TO 125oC MAX MIN MAX UNITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current VDD Operating Current VCC Quiescent Current VCC Operating Current AHB. . IBHB IAHBO. . VSS = VALS = VBLS = VAHS = VBHS = 0V. . . . . . . .HIP4081A Absolute Maximum Ratings Supply Voltage. . . . . . .0V to +1.3V Voltage on AHO. BHO . .8 -60 0. -0. . No Load VBHS = VAHS = 80V. . . . . . BHS. . . BHS +VDD Voltage on ALO. . . BHB . Junction Temperature .3V to VAHB. . . . . . BLI.5 14. . . 20V/ns NOTE: All Voltages relative to VSS. . . . . . . . .0 7. .3V to 16V Logic I/O Voltages . AHB. .3V Input Current. . . .9 5. . AND BHO Low Level Output Voltage High Level Output Voltage Peak Pullup Current VOL VCC-VOH IO + IOUT = 100mA IOUT = -100mA VOUT = 0V 0.3V to VDD +0. . . . . . . . . .25 -30 1. . . . . . . . .-500µA to -50µA Operating Ambient Temperature Range . BLO. . . .1 5. . . . 75 Storage Temperature Range. VAHB = VBHB = 93V IAHB = IAHB = 0. . .0V Voltage on AHB. . . . . . . . . . .5 10. 125oC Lead Temperature (Soldering 10s)) . HDEL Voltage VHDEL. . BHS . . HDEL and LDEL . VLDEL IHDEL = ILDEL = -100µA 4. . . . . .Lead Tips Only Operating Conditions Supply Voltage.3V Voltage on AHS. AHO. . . . AHI. .5 20 3 -10 1.0 -11 1. . . . .5 -130 -1 35 -100 1. .VALS.02 12. . 1 7. TJ = 25oC TJS = -40oC TO 125oC MAX 60 70 70 90 25 25 75 85 70 550 620 MIN 50 40 40 30 200 MAX 80 90 90 110 35 35 95 105 90 600 690 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER Lower Turn-off Propagation Delay (ALI-ALO. BHI-BHO) Rise Time Fall Time Turn-on Input Pulse Width Turn-off Input Pulse Width Turn-on Output Pulse Width Turn-off Output Pulse Width Disable Turn-off Propagation Delay (DIS .4 8. Unless Otherwise Specified (Continued) TJ = 25oC PARAMETER Peak Pulldown Current Undervoltage.5 0. BLI-BLO) Upper Turn-off Propagation Delay (AHI-AHO.3 8.4 MAX 3.HIP4081A Electrical Specifications VDD = VCC = VAHB = VBHB = 12V.7 UNITS A V V V Switching Specifications VDD = VCC = VAHB = VBHB = 12V.Lower Outputs) Disable Turn-off Propagation Delay (DIS . VSS = VALS = VBLS = VAHS = VBHS = 0V. RHDEL = RLDEL = 100K and TA = 25oC.9 0.3 0.6 9. BLI X 1 0 0 X NOTE: AHI. BHI X X 1 0 X U/V X 0 0 0 1 DIS 1 0 0 0 X ALO.25 TYP 2.2 MAX 3.0 7. BHI-BHO) Lower Turn-on Propagation Delay (ALI-ALO. BHO 0 0 1 0 0 X signifies that input can be either a “1” or “0”.Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS .5 9. Hysteresis SYMBOL IO UV+ UVHYS TEST CONDITIONS VO UT = 12V MIN 1. CL = 1000pF. Rising Threshold Undervoltage. Falling Threshold Undervoltage.4 8. RHDEL = RLDEL = 10K. 5 .ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS .65 TJS = -40oC TO 125oC MIN 1. BLO 0 1 0 0 0 OUTPUT AHO.7 8.6 0.0 0.3 9.AHO and BHO) SYMBOL TLPHL THPHL TLPLH THPLH TR TF TPWIN-ON TPWIN-OFF TPWOUT-ON TPWOUT-OFF TDISLOW TDISHIGH TDLPLH TREF-PW TUEN TEST CONDITIONS MIN - TYP 30 35 45 60 10 10 45 55 40 410 450 RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K - RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K 50 40 40 30 240 - TRUTH TABLE INPUT ALI. VSS = VALS = VBLS = VAHS = VBHS = 0V.8 8. BLI-BLO) Upper Turn-on Propagation Delay (AHI-AHO. see Truth Table. Connect to gate of A Low-side power MOSFET. so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. Connect to source of A High-side power MOSFET. HDEL reference voltage is approximately 5. A High-side Input. Connect to source of A Low-side power MOSFET. ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). High-side turn-on DELay. Connect negative side of bootstrap capacitor to this pin. DISable input. When DIS is taken low the outputs are controlled by the other inputs. If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers. see Truth Table. Connect to source of B High-side power MOSFET. B Low-side Input. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). The low-side drivers turn-off with no adjustable delay. Connect to gate of B High-side power MOSFET. Logic level input that controls ALO driver (Pin 13). Internal circuitry clamps the bootstrap supply to approximately 12. with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Chip negative supply. with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. generally will be ground. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. A Low-side Output. Logic level input that controls BHO driver (Pin 20). Must be same potential as VDD (Pin 16). External bootstrap diode and capacitor are required. Connect to anodes of two bootstrap diodes. Positive supply to gate drivers. DIS (Pin 3) high level input overrides BHI high level input. Logic level input that controls BLO driver (Pin 18). Logic level input that controls AHO driver (Pin 11). Connect to gate of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. Positive supply to lower gate drivers. DIS (Pin 3) high level input overrides ALI high level input. LDEL reference voltage is approximately 5. B Low-side Output. so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers.HIP4081A Pin Descriptions PIN NUMBER 1 SYMBOL BHB DESCRIPTION B High-side Bootstrap supply.8V. A High-side Source connection. DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). A Low-side Source connection. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers.1V. De-couple this pin to VSS (Pin 4). Connect to source of B Low-side power MOSFET. Logic level input that when taken high sets all four outputs low. If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers. B High-side Output. B High-side Source connection. A Low-side Input.8V. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). DIS high overrides all other inputs. Low-side turn-on DELay. A High-side Bootstrap supply. The high-side drivers turn-off with no adjustable delay. External bootstrap diode and capacitor are required. B Low-side Source connection. Internal circuitry clamps the bootstrap supply to approximately 12. Must be same potential as VCC (Pin 15).1V. A High-side Output. Connect to gate of B Low-side power MOSFET. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 2 BHI 3 DIS 4 5 VSS BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB 11 12 13 14 15 16 17 18 19 20 AHO AHS ALO ALS VCC VDD BLS BLO BHS BHO 6 . Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through. B High-side Input. 90%) FIGURE 1.HIP4081A Timing Diagrams X = A OR B.90%) TF (10% . BISTATE MODE TDLPLH U/V OR DIS TREF-PW TDIS XLI XHI XLO XHO TUEN FIGURE 3.90%) (10% . INDEPENDENT MODE U/V = DIS = 0 XLI XHI = HI OR NOT CONNECTED XLO XHO (10% .90%) FIGURE 2. A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL U/V = DIS = 0 THPHL XLI XHI XLO XHO THPLH TLPLH TR (10% . DISABLE FUNCTION 7 . RHDEL = RLDEL = 100K and TA = 25oC.5 IDD SUPPLY CURRENT (mA) 12. BLI. IDDO.5 8. BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE 8 .HIP4081A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V.0 75oC 25oC 20.0 0 oC -40oC 15. VSS = VALS = VBLS = VAHS = VBHS = 0V. IBHB.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 4. ALI.0 0 100 200 300 400 500 600 700 800 900 1000 0.0 2.0 10. Unless Otherwise Specified 11. B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF) 2.5 0 200 600 800 400 SWITCHING FREQUENCY (kHz) 1000 -120 -50 -25 0 25 50 75 JUNCTION TEMPERATURE (oC) 100 125 FIGURE 8. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE 30. ICCO. NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE -90 LOW LEVEL INPUT CURRENT (µA) 2 -100 1.0 ICC SUPPLY CURRENT (mA) 4.0 125oC 25.0 FLOATING SUPPLY BIAS CURRENT (mA) FIGURE 5.0 2. NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) 5.0 9. NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FIGURE 9.0 10. SIDE A.0 1.0 3.5 FLOATING SUPPLY BIAS CURRENT (mA) FIGURE 7.0 6 8 10 12 VDD SUPPLY VOLTAGE (V) 14 IDD SUPPLY CURRENT (mA) 10.0 10.0 8.0 6.5 1 -110 0.0 5.0 8.0 0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) FIGURE 6.5 9.0 14. IAHB.0 4. AHI. 0 -40 100 120 30 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE (oC) FIGURE 10. TUEN. BHB . AHB .0 70 13.0 60 12.AHS. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE 9 . VSS = VALS = VBLS = VAHS = VBHS = 0V. DISABLE TO UPPER ENABLE.0 40 10. Unless Otherwise Specified 15. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE 80 PROPAGATION DELAY (ns) 500 PROPAGATION DELAY (ns) 70 60 475 50 450 40 425 -50 -25 0 25 50 75 100 (oC) 125 150 30 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE FIGURE 12.BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE 525 FIGURE 11.HIP4081A Typical Performance Curves NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) VDD = VCC = VAHB = VBHB = 12V.0 50 11. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE FIGURE 15.0 80 PROPAGATION DELAY (ns) -20 0 20 40 60 80 o 14. PROPAGATION DELAY vs TEMPERATURE 450 FIGURE 13. RHDEL = RLDEL = 10K and TA = 25oC. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE 80 70 REFRESH PULSE WIDTH (ns) 425 PROPAGATION DELAY (ns) -25 0 25 50 75 o 60 400 50 40 375 30 350 -50 100 125 150 20 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE ( C) FIGURE 14. 5 10.5 9. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE 80 FIGURE 17. RHDEL = RLDEL = 10K and TA = 25oC. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE 13.HIP4081A Typical Performance Curves 80 VDD = VCC = VAHB = VBHB = 12V.5 10.5 FIGURE 19.5 8. VSS = VALS = VBLS = VAHS = VBHS = 0V.5 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 8. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 21.5 11. GATE DRIVE RISE TIME TR vs TEMPERATURE 10 .5 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) FIGURE 20. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE 13.5 GATE DRIVE FALL TIME (ns) TURN-ON RISE TIME (ns) 12.5 11.5 12. Unless Otherwise Specified (Continued) 80 70 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) -40 -20 0 20 40 60 80 o 70 60 60 50 50 40 40 30 30 20 100 120 JUNCTION TEMPERATURE ( C) 20 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) FIGURE 16.5 9. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE 80 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 70 70 60 60 50 50 40 40 30 30 20 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC) 20 FIGURE 18. HIP4081A Typical Performance Curves 6.0 1250 1000 VOL (mV) 750 -40oC 500 0 oC 25oC 250 75oC 125oC 0 10 12 BIAS SUPPLY VOLTAGE (V) 14 GATE DRIVE SINK CURRENT (A) 6 7 8 9 10 11 12 13 VDD .0 HDEL. Unless Otherwise Specified 1500 1250 5. VAHB . VBHB (V) 14 15 16 FIGURE 24. VCC.5 VCC . PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE 11 . RHDEL = RLDEL = 100K and TA = 25oC. HIGH LEVEL OUTPUT VOLTAGE VCC .5 2. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100mA FIGURE 25.0 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 0 10 FIGURE 22.5 0. VSS = VALS = VBLS = VAHS = VBHS = 0V.VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA 3. LDEL INPUT VOLTAGE (V) VDD = VCC = VAHB = VBHB = 12V.VOH (mV) 1000 5.5 3.0 1.5 1. VLDEL.0 0.0 2.0 750 -40oC 500 0oC 25oC 250 75oC 125oC 12 BIAS SUPPLY VOLTAGE (V) 14 4. VHDEL VOLTAGE vs TEMPERATURE 1500 FIGURE 23.5 4. 5 0.6 60 UV8.2 0. VCC.4 30 8. UNDERVOLTAGE LOCKOUT vs TEMPERATURE FIGURE 30. RHDEL = RLDEL = 100K and TA = 25oC.0 UV+ BIAS SUPPLY VOLTAGE.0 1.2 50 25 0 25 50 100 125 150 TEMPERATURE ( C) 0 10 50 100 150 200 HDEL/LDEL RESISTANCE (kΩ) 250 FIGURE 29. Unless Otherwise Specified (Continued) 500 200 100 50 20 10 5 2 1 0.000pF 3. VSS = VALS = VBLS = VAHS = VBHS = 0V.5 1. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 1000 500 LEVEL-SHIFT CURRENT (µA) 200 100 50 20 10 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 28. VAHB.0 6 7 8 9 10 11 12 13 14 15 16 VDD.000pF 100pF FIGURE 26. MINIMUM DEAD-TIME vs DEL RESISTANCE 12 . VBHB (V) LOW VOLTAGE BIAS CURRENT (mA) VDD = VCC = VAHB = VBHB = 12V.0 0. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY VOLTAGE GATE DRIVE SINK CURRENT (A) FIGURE 27.000pF 1.0 2.5 2. VDD (V) 120 8.HIP4081A Typical Performance Curves 3.8 DEAD-TIME (ns) 75 o 150 90 8.5 0.1 1 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) 10. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE 9.5 3. HIP4081A EVALUATION PC BOARD SCHEMATIC . R30. R31. C1. CY. NOT SUPPLIED. 2. PIN 14 = +12V. COMPONENTS L1. L2. CX. C2.JMPR4. DEVICE CD4069UB PIN 7 = COM. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 .IN2 IN1 +12V Q1 R29 JMPR5 CONTROL LOGIC SECTION + C6 DRIVER SECTION CR2 HIP4080A/81A U1 C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 4 V SS 5 OUT/BLI 6 IN+/ALI 7 IN-/AHI 8 HDEL 9 LDEL R33 10 JMPR4 3 IN-/AHI 2 CW CD4069UB 1 2 CW 1 R34 3 CR1 C3 CX C5 CY 10 AHB BLS 17 16 V DD POWER SECTION B+ 2 C8 R21 1 3 1 Q3 2 1 U2 CD4069UB 2 JMPR1 OUT/BLI R22 3 L1 AO +12V Q2 R23 1 3 Q4 R24 1 3 2 2 C1 L2 BO C2 13 13 5 11 ENABLE IN I R32 U2 CD4069UB U2 CD4069UB 12 JMPR2 IN+/ALI 6 JMPR3 HEN/BHI VCC 15 ALS 14 ALO 13 AHS 12 AHO 11 HIP4081A HIP4081A U2 R30 R31 COM 3 U2 4 O ALS BLS NOTES: CD4069UB 9 U2 8 O 1. CD4069UB FIGURE 31. GND +12V JMPR5 R29 R27 R28 R26 C7 C6 R32 L1 IN1 I O IN2 JMPR1 JMPR2 JMPR3 JMPR4 L2 U2 HIP4080/81 HDEL C5 CX ALS CR1 R33 R34 R30 CY BLS FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN R31 14 B+ COM C8 CR2 Q1 U1 DIS C4 BHO BLO BLS Q2 1 R21 Q4 1 R22 R24 1 Q3 1 + + HIP4081A HIP4081A ALS ALO AHO R23 O LDEL C3 HIP4081A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 1 2 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E E20.3 (JEDEC MS-001-AD ISSUE D) 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.980 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 1.060 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.55 0.204 24.89 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 26.9 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 -C- A2 B B1 C D D1 E E1 e eA eB L N eA eC C e C A B S eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 20 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 20 2.93 15 HIP4081A Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 H 0.25(0.010) M B M M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 L SEATING PLANE A1 B h x 45o -A- D -C- A C D α µ A1 0.10(0.004) C E e H h L N e B 0.25(0.010) M C A M B S 0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers December 2001 LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers General Description These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. n Logarithmic amplifiers n Photocell amplifiers n Sample and Hold circuits Common Features n Low input bias current: 30pA n Low Input Offset Current: 3pA n High input impedance: 1012Ω n Low input noise current: n High common-mode rejection ratio: n Large dc voltage gain: 106 dB 100 dB Features Advantages n Replace expensive hybrid and module FET op amps n Rugged JFETs allow blow-out free handling compared with MOSFET input devices n Excellent for low noise applications using either high or low source impedance — very low 1/f corner n Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers n New output stage allows use of large capacitive loads (5,000 pF) without stability problems n Internal compensation and large differential input voltage capability Uncommon Features LF155/ LF355 j Extremely LF156/ LF256/ LF356 1.5 LF257/ LF357 (AV =5) 1.5 Units 4 µs fast settling time to 0.01% j Fast slew 5 2.5 20 12 5 12 50 20 12 V/µs MHz rate j Wide gain Applications n n n n Precision high speed integrators Fast D/A and A/D converters High impedance buffers Wideband, low noise, low drift amplifiers bandwidth j Low input noise voltage Simplified Schematic 00564601 *3pF in LF357 series. BI-FET™, BI-FET II™ are trademarks of National Semiconductor Corporation. © 2001 National Semiconductor Corporation DS005646 www.national.com LF155/LF156/LF256/LF257/LF355/LF356/LF357 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for availability and specifications. LF155/6 Supply Voltage Differential Input Voltage Input Voltage Range (Note 2) Output Short Circuit Duration TJMAX H-Package N-Package M-Package Power Dissipation at TA = 25˚C (Notes 1, 8) H-Package (Still Air) H-Package (400 LF/Min Air Flow) N-Package M-Package Thermal Resistance (Typical) θJA H-Package (Still Air) H-Package (400 LF/Min Air Flow) N-Package M-Package (Typical) θJC H-Package Storage Temperature Range Soldering Information (Lead Temp.) Metal Can Package Soldering (10 sec.) Dual-In-Line Package Soldering (10 sec.) Small Outline Package Vapor Phase (60 sec.) Infrared (15 sec.) 215˚C 220˚C 215˚C 220˚C 260˚C 260˚C 260˚C 300˚C 300˚C 300˚C 23˚C/W −65˚C to +150˚C 23˚C/W −65˚C to +150˚C 23˚C/W −65˚C to +150˚C 160˚C/W 65˚C/W 160˚C/W 65˚C/W 130˚C/W 195˚C/W 160˚C/W 65˚C/W 130˚C/W 195˚C/W 560 mW 1200 mW 400 mW 1000 mW 670 mW 380 mW 400 mW 1000 mW 670 mW 380 mW 150˚C 115˚C 100˚C 100˚C 115˚C 100˚C 100˚C LF256/7/LF356B LF355/6/7 ± 22V ± 40V ± 20V Continuous ± 22V ± 40V ± 20V Continuous ± 18V ± 30V ± 16V Continuous See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. ESD tolerance (100 pF discharged through 1.5kΩ) 1000V 1000V 1000V DC Electrical Characteristics (Note 3) Symbol VOS ∆VOS/∆T ∆TC/∆VOS IOS Parameter Input Offset Voltage Average TC of Input Offset Voltage Change in Average TC with VOS Adjust Input Offset Current Conditions Min RS =50Ω, TA =25˚C Over Temperature RS =50Ω RS =50Ω, (Note 4) TJ =25˚C, (Notes 3, 5) TJ≤THIGH 5 0.5 3 20 20 LF155/6 Typ 3 Max Min 5 7 5 0.5 3 20 1 LF256/7 LF356B Typ 3 Max Min 5 6.5 5 0.5 3 50 2 LF355/6/7 Typ 3 Max 10 13 mV mV µV/˚C µV/˚C per mV pA nA Units www.national.com 2 LF155/LF156/LF256/LF257/LF355/LF356/LF357 DC Electrical Characteristics (Note 3) Symbol IB RIN AVOL Parameter Input Bias Current Input Resistance Large Signal Voltage Gain Output Voltage Swing Input Common-Mode Voltage Range Common-Mode Rejection Ratio Supply Voltage Rejection Ratio (Note 6) (Continued) LF256/7 LF356B Max Min 100 50 10 50 25 12 Conditions Min TJ =25˚C, (Notes 3, 5) TJ≤THIGH TJ =25˚C VS = ± 15V, TA =25˚C VO = ± 10V, RL =2k Over Temperature LF155/6 Typ 30 LF355/6/7 Max Min 100 5 Typ 30 10 25 15 12 Units pA nA Ω V/mV V/mV Typ 30 10 12 Max 200 8 200 50 25 200 200 VO VCM CMRR PSRR VS = ± 15V, RL =10k VS = ± 15V, RL =2k VS = ± 15V ± 12 ± 10 ± 11 85 85 ± 13 ± 12 +15.1 −12 100 100 ± 12 ± 10 ± 11 85 85 ± 13 ± 12 ± 15.1 −12 100 100 ± 12 ± 10 +10 80 80 ± 13 ± 12 +15.1 −12 100 100 V V V V dB dB DC Electrical Characteristics TA = TJ = 25˚C, VS = ± 15V Parameter Supply Current LF155 Typ 2 Max 4 LF355 Typ 2 Max 4 LF156/256/257/356B Typ 5 Max 7 LF356 Typ 5 Max 10 LF357 Typ 5 Max 10 Units mA AC Electrical Characteristics TA = TJ = 25˚C, VS = ± 15V LF155/355 Symbol SR Parameter Slew Rate Conditions Typ LF155/6: AV =1, LF357: AV =5 GBW ts en Gain Bandwidth Product Settling Time to 0.01% Equivalent Input Noise Voltage (Note 7) RS =100Ω f=100 Hz f=1000 Hz in Equivalent Input Current Noise Input Capacitance f=100 Hz f=1000 Hz 25 20 0.01 0.01 3 15 12 0.01 0.01 3 15 12 0.01 0.01 3 pF 2.5 4 5 1.5 5 LF156/256/ 356B Min 7.5 LF156/256/356/ LF356B Typ 12 50 20 1.5 LF257/357 Units Typ V/µs V/µs MHz µs CIN Notes for Electrical Characteristics Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD =(TJMAX−TA)/θJA or the 25˚C PdMAX, whichever is less. Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 3: Unless otherwise stated, these test conditions apply: 3 www.national.com the input bias currents measured are correlated to junction temperature. in accordance with common practice. TJ.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Notes for Electrical Characteristics LF155/156 Supply Voltage.com 4 . Pd.01% of its final value from the time a 10V step input is applied to the inverter. Note 8: Max. for a unity gain inverter connection using 2 kΩ resistors for the LF155/6. AV = −5. Power Dissipation may cause the part to operate outside guaranteed limits. Operating the part near the Max. Power Dissipation is defined by the package characteristics. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment.5µV/˚C typically) for each mV of adjustment from its original unadjusted value. IB and IOS are measured at VCM = 0. Typical DC Performance Characteristics specified. TJ = TA + θJA Pd where θJA is the thermal resistance from junction to ambient. Note 7: Settling time is defined here. Due to limited production test time. Note 5: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature. the feedback resistor from output to input is 2kΩ and the output step is 10V (See Settling Time Test Circuit). Input Bias Current Curves are for LF155 and LF156 unless otherwise Input Bias Current 00564637 00564638 Input Bias Current Voltage Swing 00564639 00564640 www.national. For the LF357. VS TA THIGH (Continued) LF256/257 LF356B LF355/6/7 VS = ± 15V 0˚C ≤ TA ≤ +70˚C +70˚C ± 15V ≤ VS ≤ ± 20V −55˚C ≤ TA ≤ +125˚C +125˚C ± 15V ≤ VS ≤ ± 20V −25˚C ≤ TA ≤ +85˚C +85˚C ± 15V ≤ VS ± 20V 0˚C ≤ TA ≤ +70˚C +70˚C and VOS. Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0. Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation. Use of a heat sink is recommended if input bias current is to be kept to a minimum. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0. com .LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical DC Performance Characteristics specified.national. (Continued) Supply Current Curves are for LF155 and LF156 unless otherwise Supply Current 00564641 00564642 Negative Current Limit Positive Current Limit 00564643 00564644 Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit 00564645 00564646 5 www. LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical DC Performance Characteristics specified. (Continued) Open Loop Voltage Gain Curves are for LF155 and LF156 unless otherwise Output Voltage Swing 00564647 00564648 Typical AC Performance Characteristics Gain Bandwidth Gain Bandwidth 00564649 00564650 Normalized Slew Rate Output Impedance 00564651 00564652 www.com 6 .national. AV = +1 00564605 00564653 LF156 Small Signal Pulse Response.com . AV = +1 Inverter Settling Time 00564609 00564655 7 www. AV = +1 LF155 Large Signal Pulse Response.national. AV = +1 00564606 00564608 LF156 Large Signal Puls Response.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical AC Performance Characteristics Output Impedance (Continued) LF155 Small Signal Pulse Response. national.com 8 .LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical AC Performance Characteristics Inverter Settling Time (Continued) Open Loop Frequency Response 00564656 00564657 Bode Plot Bode Plot 00564658 00564659 Bode Plot Common-Mode Rejection Ratio 00564660 00564661 www. national.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical AC Performance Characteristics Power Supply Rejection Ratio (Continued) Power Supply Rejection Ratio 00564662 00564663 Undistorted Output Voltage Swing Equivalent Input Noise Voltage 00564664 00564665 Equivalent Input Noise Voltage (Expanded Scale) 00564666 9 www.com . LF356MX.national. Connection Diagrams (Top Views) Dual-In-Line Package (M and N) Metal Can Package (H) 00564614 Order Number LF155H. or LF357H See NS Package Number H08C *Available per JM38510/11401 or JM38510/11402 00564629 Order Number LF356M. potentially causing a www. LF156H.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Detailed Schematic 00564613 *C = 3pF in LF357 series. LF356BH. Therefore large differential input voltages can easily be accommodated without a large increase in input current. LF355N. neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. However. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Exceeding the negative common-mode limit on either input will force the output to a high state.com 10 . LF256H. or LF356N See NS Package Number M08A or N08E Application Hints These are op amps with JFET input devices. LF356H. LF257H. The maximum differential input voltage is independent of the supply voltages. As with most amplifiers. Exceeding the positive common-mode limit on a single input will not change the phase of the output however. in a supply current monitor and/or limiter. 0. CL(MAX) . In fact.national. the output of the amplifier will be forced to a high state. care should be taken with lead dress. The positive supply can therefore be used as a reference on an input as. power bandwidth is: 500kHz. 00564667 • • • VOS is adjusted with a 25k potentiometer The potentiometer wiper is connected to V+ For potentiometers with temperature coefficient of 100 ppm/˚C or less the additional drift with adjust is ≈ 0. if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. A Large Power BW Amplifier 00564615 For distortion ≤ 1% and a 20 Vp-p VOUT swing. Overshoot ≤ 20% Settling time (ts) .com . In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. component placement and supply decoupling in order to ensure stability. For example. 11 www. A feedback pole is created when the feedback around any amplifier is resistive. for example. The drain currents for the amplifiers are therefore essentially independent of supply voltage. All of the bias currents in these amplifiers are set by FET current sources. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. if both inputs exceed the limit. these amplifiers have the ability to drive large capacitive loads and still maintain stability. the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range.) Driving Capacitive Loads • 00564668 * LF155/6 R = 5k LF357 R = 1. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is negligible effect on stability margin.5µV/ ˚C/mV of adjustment Typical overall drift: 5µV/˚C ± (0. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.25k Due to a unique output stage design. These amplifiers will operate with the common-mode input voltage equal to the positive supply. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. 5µs LF357.01µF. However. resistors from the output to an input should be placed with the body close to the input to minimize “pickup” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Application Hints (Continued) Typical Circuit Connections VOS Adjustment reversal of phase to the output.5µV/˚C/mV of adj. com 12 . VOUT (from Settling Time Circuit) LF355 LF357 00564617 00564619 LF356 00564618 www.national.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications Settling Time Test Circuit 00564616 • • • • Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = −5 FET used to isolate the probe capacitance Output = 10V step AV = −5 for LF357 Large Signal Inverter Output. 002%/˚C All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Use LF155 for j Low IB j Low drift j Low supply current Fast Logarithmic Converter 00564621 • • • • • Dynamic range: 100µA ≤ Ii ≤ 1mA (5 decades).com . R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0. |VO| = 1V/decade Transient response: 3µs for ∆Ii = 1 decade C1.national. C2. R2.3%/˚C 13 www.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) Low Drift Adjustable Voltage Reference 00564620 • • • • • ∆ VOUT/∆T = ± 0. com 14 .040 −9.920 +0. R3: 0.920 B1 B2 B3 B4 B5 B6 B7 B8 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Comments Positive Full-Scale (+) Zero-Scale (−) Zero-Scale Negative Full-Scale www. R2 should be matched within ± 0.040 −0.national. R2.1% resistors Use LF155 for j Common-mode range to supply range j Low IB j Low VOS j Low Supply Current 8-Bit D/A Converter with Symmetrical Offset Binary Operation 00564632 • • R1.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) Precision Current Monitor 00564631 • • • VO = 5 R1/R2 (V/mA of IS) R1.05% Full-scale response time: 3µs EO +9. LF156 and LF357 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole. Low Drift Amplifier 00564670 • Parasitic input capacitance C1 .com . (3pF for LF155.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) Wide BW Low Noise. To compensate add C2 such that: R2 C2 .national.150mA (will drive RL≥ 100Ω) • No additional phase shift added by the current amplifier 15 www. R1 C1. Boosting the LF156 with a Current Amplifier 00564673 • IOUT(MAX). LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) 3 Decades VCO 00564624 R1, R4 matched. Linearity 0.1% over 2 decades. Isolating Large Capacitive Loads 00564622 • • • Overshoot 6% ts 10µs When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX): www.national.com 16 LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) Low Drift Peak Detector 00564623 • • • • By adding D1 and Rf, VD1 =0 during hold mode. Leakage of D2 provided by feedback path through Rf. Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp. Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be << 1⁄2πRfCD2 where CD2 is the shunt capacitance of D2. Non-Inverting Unity Gain Operation for LF157 00564675 Inverting Unity Gain for LF157 00564625 17 www.national.com LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) High Impedance, Low Drift Instrumentation Amplifier 00564626 • • System VOS adjusted via A2 VOS adjust Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift www.national.com 18 com . A2) have feedback loops individually closed with stable responses (overshoot negligible) Acquisition time TA.national. A1 and A2 19 www. estimated by: • • • LF156 develops full Sr output capability for VIN ≥ 1V Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) Fast Sample and Hold 00564633 • • Both amplifiers (A1. No VOS adjust required for A2.LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) High Accuracy Sample and Hold 00564627 • • • • • By closing the loop through A2. CC: additional compensation Use LF156 for j Fast settling time j Low VOS High Q Band Pass Filter 00564628 • • • By adding positive feedback (R2) Q increases to 40 fBP = 100 kHz • • Clean layout recommended Response to a 1Vp-p tone burst: 300µs www.national. because of the added propagation delay in the feedback loop (A2) the overshoot is not negligible. TA can be estimated by same considerations as previously but.com 20 . the VOUT accuracy will be determined uniquely by A1. Overall system slower than fast sample and hold R1. LF155/LF156/LF256/LF257/LF355/LF356/LF357 Typical Applications (Continued) High Q Notch Filter 00564634 • • • • 2R1 = R = 10MΩ 2C = C1 = 300pF Capacitors should be matched to obtain high Q fNOTCH = 120 Hz.com . notch = −55 dB. Q > 100 Use LF155 for j Low IB j Low supply current 21 www.national. LF155/LF156/LF256/LF257/LF355/LF356/LF357 Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) Order Number LF155H. LF356H or LF357H NS Package Number H08C Small Outline Package (M) Order Number LF356M or LF356MX NS Package Number M08A www. LF257H.national.com 22 . LF256H. LF156H. LF356BH. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap. or to affect its safety or effectiveness.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. (a) are intended for surgical implant into the body. and whose failure to perform when properly used in accordance with instructions for use provided in the labeling. no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www. can be reasonably expected to result in a significant injury to the user.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe. or (b) support or sustain life.support@nsc. .LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number LF356N NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.national. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system.com National does not assume any responsibility for use of any circuitry described. As used herein: 1.com National Semiconductor Japan Ltd. National Semiconductor Corporation Americas Email: support@nsc. Life support devices or systems are devices or systems which.support@nsc. SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003 D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption. D. and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated On products compliant to MIL-PRF-38535. DB. . FK PACKAGE (TOP VIEW) 1D 1CLR NC VCC 2CLR 1CLK NC 1PRE NC 1Q 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 2D NC 2CLK NC 2PRE NC – No internal connection ORDERING INFORMATION TA PDIP – N SOIC – D –40°C to 85°C SOP – NS SSOP – DB TSSOP – PW CDIP – J –55°C to 125°C CFP – W LCCC – FK PACKAGE† Tube of 25 Tube of 50 Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC74N SN74HC74D SN74HC74DR SN74HC74DT SN74HC74NSR SN74HC74DBR SN74HC74PW SN74HC74PWR SN74HC74PWT SNJ54HC74J SNJ54HC74W SNJ54HC74FK SNJ54HC74J SNJ54HC74W HC74 HC74 HC74 HC74 TOP-SIDE MARKING SN74HC74N SNJ54HC74FK † Package drawings. TEXAS 75265 1Q GND NC 2Q 2Q 1 . Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. standard packing quantities. all parameters are tested unless otherwise noted. OR PW PACKAGE (TOP VIEW) description/ordering information The ’HC74 devices contain two independent D-type positive-edge-triggered flip-flops. . 40-µA Max ICC Typical tpd = 15 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max SN54HC74 . . . . Please be aware that an important notice concerning availability. Copyright  2003. and PCB design guidelines are available at www. data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. On all other products. regardless of the levels of the other inputs. Products conform to specifications per the terms of Texas Instruments standard warranty. . J OR W PACKAGE SN74HC74 . 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54HC74 . NS. Following the hold-time interval. thermal data.ti.com/sc/package. Production processing does not necessarily include testing of all parameters. data at the D input can be changed without affecting the levels at the outputs.SN54HC74. PRODUCTION DATA information is current as of publication date. When PRE and CLR are inactive (high). N. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs. POST OFFICE BOX 655303 • DALLAS. standard warranty. symbolization. production processing does not necessarily include testing of all parameters. . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . The package thermal impedance is calculated in accordance with JESD 51-7. . . . . 2. .5 V to 7 V Input clamp current. . . . . . . . . . . . . . . . . . . . . . IO (VO = 0 to VCC) . . 80°C/W NS package . . . . . . . VCC . . . . . IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . θJA (see Note 2): D package . . . . . . . . . . IIK (VI < 0 or VI > VCC) (see Note 1) . These are stress ratings only. . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. . . . . . . . . . . . . . . . . . NOTES: 1. . . . . . . . . . . . . logic diagram (positive logic) PRE CLK C C C C Q TG C C D TG TG TG Q C CLR C C C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range. . . . . . . . . . it does not persist when PRE or CLR returns to its inactive (high) level. . . . . . . . . . .SN54HC74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEXAS 75265 . . . . . . . . . . . . . . . . . Tstg . . . . . . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. . . . . . . . . . . . . . . . . . . . . . . . . that is. . . 96°C/W N package . . 2 POST OFFICE BOX 655303 • DALLAS. . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current. . . . . . . . . . . . . . . . SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003 FUNCTION TABLE INPUTS PRE L H L H H CLR H L L H H CLK X X X ↑ ↑ D X X X H L OUTPUTS Q H L H† H L Q L H H† L H H H L X Q0 Q0 † This configuration is nonstable. . . . ±50 mA Package thermal impedance. ±20 mA Continuous output current. . . . . . and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. . . . . . . . . . . . . . . . –0. . . . . The input and output voltage ratings may be exceeded if the input and output current ratings are observed. . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . 2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0.5 1.15 4.84 5.1 0.4 5.8 VCC VCC 1000 500 0 0 NOM 5 MAX 6 SN74HC74 MIN 2 1.9 4.1 0.9 3.999 4.5 V 6V 4.5 V 6V 2V 4.SN54HC74.9 4.1 0.5 3.1 0.2 0.35 1.26 0.8 VCC VCC 1000 500 ns V V V V NOM 5 MAX 6 UNIT V VCC = 6 V 400 400 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.998 4.35 1. literature number SCBA004.2 0. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 2V IOH = –20 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 0.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.15 4.001 0.9 3.7 5.8 0.1 0.4 0.17 0.499 5.001 0.4 5.5 V 6V 4.98 5.9 4.3 5.1 0. Implications of Slow or Floating CMOS Inputs.15 ±0.002 0. IO = 0 4.4 ±1000 80 10 MAX SN74HC74 MIN 1.34 0.5 1.48 TA = 25°C TYP MAX 1.1 0.5 V VCC = 4.33 0. TEXAS 75265 3 .4 5.5 3.5 V VCC = 6 V 0 0 2 1. SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003 recommended operating conditions (see Note 3) SN54HC74 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4. Refer to the TI application report.1 0.5 V VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 2 V VCC = 4.1 0.1 0.26 ±100 4 10 SN54HC74 MIN 1.33 ±1000 40 10 nA µA pF V V MAX UNIT POST OFFICE BOX 655303 • DALLAS.9 3. 5 V 6V 2V tt Q or Q 4.SN54HC74. CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V th Hold time. SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC 2V fclock Clock frequency 4.2 21 25 0 125 25 21 100 20 17 125 25 21 30 6 5 0 0 0 ns ns ns SN74HC74 MIN MAX 5 25 29 MHz UNIT switching characteristics over recommended operating free-air temperature range.5 V 6V 2V 4.5 V 6V 2V 4. data after CLK↑ ↑ 4.5 V 6V 2V PRE or CLR tpd d CLK Q or Q Q or Q 4. TEXAS 75265 .5 V 6V 2V 4.2 21 25 345 69 59 250 50 42 110 22 19 MAX SN74HC74 MIN 5 25 29 290 58 49 220 44 37 95 19 16 ns ns MHz MAX UNIT operating characteristics. TA = 25°C PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS No load TYP 35 UNIT pF 4 POST OFFICE BOX 655303 • DALLAS.5 V 6V TA = 25°C MIN TYP MAX 6 31 36 10 50 60 70 20 15 70 20 15 28 8 6 230 46 39 175 35 30 75 15 13 SN54HC74 MIN 4.5 V 6V 2V PRE or CLR low tw Pulse duration CLK high or low 4.5 V 6V 0 100 20 17 80 16 14 100 20 17 25 5 4 0 0 0 TA = 25°C MIN MAX 6 31 36 0 150 30 25 120 24 20 150 30 25 40 8 7 0 0 0 SN54HC74 MIN MAX 4.5 V 6V 2V Data tsu Setup time before CLK↑ ↑ PRE or CLR inactive 4. tf = 6 ns. E. Figure 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz. ZO = 50 Ω. TEXAS 75265 5 . C. fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. D. SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pF (see Note A) Low-Level Pulse 50% High-Level Pulse VCC 50% tw VCC 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS VCC 0V tsu Data Input 50% 10% 90% th 90% VCC 50% 10% 0 V tf Out-of-Phase Output In-Phase Output tPLH 50% 10% tPHL 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr tPHL 90% VOH 50% 10% VOL tf VOH VOL VCC 50% 50% 0V 50% 0V LOAD CIRCUIT Reference Input 50% Input tr VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B.SN54HC74. Phase relationships between waveforms were chosen arbitrarily. For clock inputs. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS. tr = 6 ns. tPLH and tPHL are the same as tpd. . MECHANICAL DATA MCFP002A – JANUARY 1995 – REVISED FEBRUARY 2002 W (R-GDFP-F14) CERAMIC DUAL FLATPACK Base and Seating Plane 0.20) 0.335 (8.60) 0.27) 0.10) 0.004 (0.250 (6. E.015 (0.250 (6.35) 4040180-2 / C 02/02 NOTES: A.11) MAX 1 14 0.14) 0.13) MIN 4 Places 7 0.235 (5. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB POST OFFICE BOX 655303 • DALLAS.019 (0.14) 0.008 (0.03) 0.14) 0.390 (9.66) 0.38) 0.360 (9.026 (0.48) 0. B.080 (2.14) 0. This package can be hermetically sealed with a ceramic lid using glass frit.045 (1. Index point is provided on cap for terminal identification only.97) 0.360 (9.045 (1.91) 0. All linear dimensions are in inches (millimeters).260 (6.51) 0.280 (7. D. TEXAS 75265 1 . C.050 (1.005 (0.35) 8 0. This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid.76) 0.495 (12. All linear dimensions are in inches (millimeters).962 (24.660 (16.22) 0.045 (1.89) 0.99) MAX 0.761 (19.14) 0.03) 0.27) 0.358 (9.458 (11.59) MIN 0.307 (7.51) 0.22) 0.020 (0.58) 0.035 (0. D.0) 19 20 21 B SQ 22 A SQ 23 24 25 26 27 28 1 2 3 4 0.045 (1.560 (14.028 (0. TEXAS 75265 1 . OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20 A MIN 0.063 (27.51) 0.25) 0.40) 0.43) 1. B.58) 0.MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 18 17 16 15 14 13 12 NO.560 (14.32) 0.14) 0.055 (1.09) 0.640 (16.010 (0.035 (0.080 (2.850 (21.80) 0.26) 0.938 (23. The terminals are gold plated.047 (26.6) B MAX 0.8) 1.14) 0.050 (1. E.045 (1.31) 0.69) 0.63) 0.63) 0.71) 0.141 (28.064 (1.25) 0.89) 4040140 / D 10/96 NOTES: A.458 (11.165 (29.442 (11.342 (8.010 (0.23) 0. This drawing is subject to change without notice.63) 0. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS.020 (0. C.6) 1.022 (0.78) 0.83) 1.09) 0.495 (12.858 (21.358 (9.54) 0.739 (18.406 (10. 25) NOM Gauge Plane 0.850 (21.940 (23.51) MIN 0.69) 0.021 (0. D.25) M 0. either half or full width.010 (0.015 (0.18) MIN 0.015 (0.920 (23. C.38) 0.78) 0.070 (1.745 (18.26) 0.10) C MS-100 VARIATION AA BB AC AD 1 0.92) MAX 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A.010 (0. The 20 pin end lead shoulder width is a vendor option. All linear dimensions are in inches (millimeters).745 (18.100 (2. Falls within JEDEC MS-001. This drawing is subject to change without notice.775 (19.92) 16 0.92) 0.14) 0.53) 0.59) 20 1.08) MAX Seating Plane 0.240 (6.54) 0.775 (19.62) 0.125 (3.92) 18 0.300 (7.38) 0.030 (0. TEXAS 75265 1 .200 (5.060 (26.60) 0.325 (8.37) 0.14) D 8 0.020 (0.045 (1.88) A MIN 0. except 18 and 20 pin minimum body lrngth (Dim A). B.260 (6.69) 0.430 (10.045 (1. POST OFFICE BOX 655303 • DALLAS.76) D 0.MECHANICAL MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002 N (R-PDIP-T**) 16 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE PINS ** DIM A 16 9 A MAX 14 0. 010 (0.55) 16 0.75) MAX 0.157 (4.244 (6.010 (0.25) Seating Plane 0.050 (1.228 (5.35) 0.40) 0.004 (0.008 (0.006 (0.80) 0.00) 0.020 (0.51) 0.81) 0. D.27) 8 5 0.394 (10.20) NOM Gage Plane 1 A 4 0°– 8° 0.80) 4040047/E 09/01 NOTES: A.344 (8.00) 0.014 (0.25) 0.25) PLASTIC SMALL-OUTLINE PACKAGE 0. B.00) 0.044 (1.12) 0.337 (8. This drawing is subject to change without notice.10) 0.15).197 (5.386 (9. not to exceed 0.069 (1. All linear dimensions are in inches (millimeters). TEXAS 75265 1 . Body dimensions do not include mold flash or protrusion. C.010 (0.10) PINS ** DIM A MAX A MIN 8 0.150 (3.189 (4. Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS.016 (0.20) 0.80) 14 0.75) 0.004 (0.MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) 8 PINS SHOWN 0. . 00 8.50 10.09 5.30 4040065 /E 12/01 NOTES: A.90 9.50 7. Body dimensions do not include mold flash or protrusion not to exceed 0.90 6. This drawing is subject to change without notice.90 5.90 9. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS.38 0.22 15 0. C.MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN 0.15.90 A MIN 5.00 MAX 0.60 5.25 0.50 6.05 MIN 0.15 M PLASTIC SMALL-OUTLINE 0.90 12. TEXAS 75265 1 .95 0.90 7.50 10.50 8.65 28 0.25 0.20 7.10 PINS ** DIM A MAX 14 16 20 24 28 30 38 6. All linear dimensions are in millimeters.50 12.55 Seating Plane 2. B. D.40 Gage Plane 1 A 14 0°– 8° 0. This drawing is subject to change without notice.30 0. B.15 0.10 5.60 6.65 14 8 0.40 7. Body dimensions do not include mold flash or protrusion not to exceed 0.MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.10 PINS ** DIM A MAX 8 14 16 20 24 28 3.60 7.20 MAX 0.15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS.90 6.10 5.10 6. D.90 4. All linear dimensions are in millimeters. C.50 Seating Plane 1.90 4.80 A MIN 2.70 9.19 0.50 4.75 0.60 4040064/F 01/97 NOTES: A.20 Gage Plane 0. TEXAS 75265 1 .30 6.90 9.05 0.10 M 0.25 1 A 7 0°– 8° 0.15 NOM 4. or other TI intellectual property right relating to any combination.ti.com/video www. TI is not responsible or liable for any such statements. or a license from TI under the patents or other intellectual property of TI.com/wireless .com/security www.ti. Texas Instruments Incorporated www.ti.com dsp. customers should provide adequate design and operating safeguards.ti. or process in which TI products or services are used. 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