chapter7-ex.fm Page 1 Wednesday, October 29, 2003 11:52 PM 1 Chapter 7 Problem Set Chapter 7 PROBLEMS 1. [M, None, 7.4] Figure 1 shows a practical implementation of a pulse register. Clock Clk is ideal with 50% duty cycle. V DD Q X Q D Clk d Clk Figure 0.1 Pulse register. Data : VDD = 2.5V, tp,inv = 200ps, node capacitances are CClkd = 10fF, Cx = 10fF, both true and complementary outputs node capacitances are 20fF. a. Draw the waveforms at nodes Clk, Clkd, X and Q for two clock cycles, with D = 0 in one cycle and D = 1 in the other. b. What is the approximate value of setup and hold times for this circuit? c. c)If the probability that D will change its logic value in one clock cycle is α, with equal probability of being 0 or 1, what is the power consumption of this circuit? (exclude the power consumption in the clock line) fclk = 100 MHz. NMOS: VTn = 0. γ = 0V1/2 . a.chapter7-ex.fm Page 2 Wednesday. You may ignore the body effect in this question. and all of the PMOS transistors are of the same size. 2003 11:52 PM 2 2. Chapter 7 Problem Set [M.5V. VDSAT = 0. CKI 3. None. The other transistor parameters are as given in Chapter 3. If all the NMOS transistors are of the same size. 7.4] Figure 2 shows a register that attempts to statistically reduce power consumption using a data-transition look-ahead technique. two times wider than the NMOS. October 29. VDD = 2.6V. The W/L ratios of other transistors are shown in figure. λ = 0.4V. None. Determine the W/L ratio of transistor M1 such that VM+ = 3VTn. [E. Briefly describe the operation of the circuit. roughly determine the input switching probability under which this flip-flop reduces power. kn’ = 115µA/V2. CKI Q D DI CKIB CKIB Data-Transition Look-Ahead Pulse Generator XNOR CKIB Clk Figure 0.6] Shown in Figure 3 is a novel design of a Schmitt trigger. compared to an equivalent flip-flop without data-transition look-ahead circuitry.2 Pulse register. b. 7. The transistors have VT_=0. . λ = 0. M1 has (W/L)1=1. [M.4V.2nd Ed PMOS: VTp = -0.2V M2 Vin M1 X M3 Vout Figure 0. kn’=120 µA/V2 and kp= 40 µA/V2. VDD = 1.chapter7-ex. a. 2003 11:52 PM Digital Integrated Circuits . 7. Find the value of (W/L)3 such that when Vin decreases from VDD to 0 the output will switch at Vin = 0.. The inverter is ideal. October 29. None. If you don’t trust your value from b.4 Schmitt trigger.4V. VDSAT = -1V. γ = -0V1/2 3 VDD 2. 4.6] Consider the circuit in Figure 4.4V.5 M4 M2 VDD 1 VX ? 10 Vout Vin M3 M1 Figure 0.fm Page 3 Wednesday. c. you may use (W/L)2=5. As VIN goes from 0 to VDD and back to 0 explain the sequence of events which makes this circuit operate as a Schmitt Trigger. with VM=VDD/2 and infinite slope. Find the value of (W/L)2 such that when VIN increases from 0 to VDD the output will switch at Vin = 0.3 Schmitt trigger. b. kp’ = -30µA/V2. Ignore all other parasitic effects in the transistors.8V. the resistances of the MOS transistors. None. VDD = -VSS == 5V.4µA Y Z Figure 0. Assume that the amplifier is ideal.6V (ideal diode). with symmetric supplies (Voutmax = VDD. [E.5 Astable multivibrator. The inverter switch point is set at 1.5V. 2003 11:52 PM 4 5.2µA A C0 = 1pF X 2. C = 1nF.3V I0 = 4. 6. and all internal capacitors can be ignored. Draw the signal waveforms for this circuit at nodes X.6] An oscillator is shown in Figure 6. Chapter 7 Problem Set [M. 3. Y. diode voltage VD = 0.5V C1 = 1pF B I1 = 1. October 29. What is the oscillation frequency of the multivibrator? R1 R2 D1 D2 VC C R3 V out R4 Figure 0. R3 = R4 = 4kΩ.25V. A. and B. You may assume that the delay of the inverters.6 Oscillator. None. Voutmin = -VSS) R1 = 1kΩ. Calculate and draw voltage waveforms at the capacitor VC and at the output Vout.chapter7-ex. R2 = 3kΩ. Determine the oscillation frequency. respectively. Assume that nodes Y and Z are initially at 0V and 2. Vout (t = 0-) = -VSS. . 7. Z. 7.6] Figure 5 shows an astable multivibrator.fm Page 4 Wednesday. pulse width for monostable. Draw the waveforms at nodes X.6] Consider the oscillator in Figure 7. Y. None. Calculate the key timing parameter for this circuit (propagation delay for bistable. Assume that the “n” switches turn “on” for voltages above VDD/2. Assume that the current sources stop when the node voltage charges to either VDD or ground. c.= 1V.chapter7-ex. . Y. and the “p” switches turn “on” for voltages below VDD/2. b. X R A Figure 0. October 29.7 Oscillator. a. Find the oscillation period for VDD = 3V. [M. V DD 50µA p n 50µA Figure 0. Find the oscillation period. and Z for two periods. bistable. 7. 5 [E. 7. You can assume that gate delays are negligible compared to the delay of the RC network. or astable? b. c. a.fm Page 5 Wednesday. None. Identify whether the circuit is monostable.2nd Ed 7. 2003 11:52 PM Digital Integrated Circuits . V DD 50 µA p 20fF n 50 µA V DD 50µA p 20fF n 50µA X Y Z 20fF 8. and A. Draw the waveforms at nodes X. and time period for astable) in terms of R and C. VM.8 Y C A circuit composed of Schmitt triggers. Mark all important voltage levels.6] The circuit in Figure 8 operates at a supply voltage of 3V and uses two Schmitt triggers with the following threshold voltages: VM+ = 2V.