Capacitorless LDO voltage regulators

1880IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 9, SEPTEMBER 2012 Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators Gianluca Giustolisi, Member, IEEE, Gaetano Palumbo, Fellow, IEEE, and Ester Spitale Abstract—This paper presents a general methodology for compensating LDO regulators which exploits a current amplifier to effectively multiply the Miller capacitor. After a general theoretical analysis that takes into account both the external and internal loop stability, it is examined the feasibility of applying this kind of compensation in different LDO applications, showing the role of the design parameters and proposing a specific design procedure for each practical cases which differ in terms of load capacitance and the adoption of a decoupling voltage buffer. Simulations and experimental results which validate the methodology are also included. Index Terms—CMOS analog integrated circuits, frequency compensation, low drop-out voltage regulators. I. INTRODUCTION I N THE LAST ten years, power management in integrated circuits (ICs) has been gaining more and more attention thanks to the growing demand for portable battery-powered electronic devices such as cellular phones, pagers, camera recorders, laptops, and PDAs. In such a scenario, where the power consumption reduction is a mandatory target, the low drop-out linear voltage regulator (LDO) has become one of the most important building blocks as it can provide regulated and accurate supply voltages [1], [2]. Linear regulators, and in particular LDOs, are based on a feedback topology which is made up of a voltage reference, an error amplifier a power device and a feedback resistive network. The feedback topology requires frequency compensation to achieve closed-loop stability and, although its small signal equivalent circuit is conceptually similar to a two-stage amplifier, it is harder to be compensated. This is due to the large values of the capacitances involved and to the wide output current range which causes the poles to span over several decades [3]–[8]. The literature has proposed several compensation techniques which concern and apply to two main classes of LDOs: the high capacitive load (HL) and the low capacitive load (LL) class. The HL class includes those LDOs designed to provide current to external (off-chip) circuitry [1], [2], [9]–[12]. In this case, a large capacitive load (in the micro-farad range) is put at the output node in order to both compensate the circuit and to reManuscript received July 29, 2011; revised November 09, 2011; accepted December 19, 2011. Date of publication May 25, 2012; date of current version August 24, 2012. This paper was recommended by Associate Editor Jipeng Li. The authors are with the Dipartimento di Ingegneria Elettrica Elettronica e Informatica, Facoltà di Ingegneria, Università degli Studi di Catania, Catania, Italy. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2012.2185306 duce the LDO overshoots during transient load or supply variations. However, the compensation remains a delicate task because of the large gate capacitance of power transistor which, setting an internal low-frequency second pole, degrades both the loop-gain bandwidth and the slew rate performance of the circuit. It is general practice to make use of the output capacitor equivalent series resistance (ESR) to compensate the second pole but the approach has several drawbacks (i.e., the ESR of a capacitor is not properly specified in many cases and varies with temperature; the use of area-efficient ceramic capacitors with very low ESR is not allowed and large ESR can significantly increase transient voltage spikes) [10], [13]. Hence, alternative compensation techniques with low or zero ESR are advisable. The LL class includes those LDOs designed to provide current to internal (on-chip) circuitry [9], [14]–[19]. These LDOs have a relatively small output capacitive load (in the range of hundreds pico-farad up to few nano-farad) and compensation is demanded to Miller-based compensation approaches. However, such approaches present the drawback of requiring very large on-chip capacitors which may lead to a prohibitive area occupation and degrade the slew-rate performance of the circuit. Recently, the scientific community has been interested in Miller-based compensation techniques which exploit capacitive multiplication through current amplifiers (CAs). The approach seems to be promising in both the two LDO classes. In the LL class, the capacitive multiplication allows to integrate the same equivalent capacitor reducing the area occupation. In the HL class, the approach improves the transient response since the miller effect allows to boost up the second-pole and, consequently, to increase the open-loop unity-gain frequency. However, despite its advantages, Miller compensation through current amplifiers gives rise to complex-conjugate poles in the open-loop transfer function which may cause instability, as in the simpler case of a two-stage amplifier [20]–[23]. Hence, compensation must be accomplished prudently. Some recent works have reported low drop-out voltage regulators compensated with current amplifiers (CA-LDOs) which are very different from each other in terms of topology and applications [24]–[31]. Despite their dissimilarities, these CA-LDOs can be classified in terms of HL and LL circuits. Besides, a second useful classification can be made depending on the presence or the absence of a voltage buffer between the error amplifier and the power transistor.1 This classification differentiates between voltage-buffered LDOs (VB) and 1The role of the voltage buffer is to decouple the high capacitive node at the power transistor gate from the high impedance node at the output of the error amplifier. This increases speed (in terms of slew-rate and bandwidth) and helps stability. However, this solution has the drawback of decreasing the power transistor overdrive. 1549-8328/$31.00 © 2012 IEEE we introduce the general model of a CA-LDO and conduct the theoretical stability analysis. the open-loop small-signal circuit for evaluating the loop-gain is shown in Fig. The current generator. . the compensation network is shown in Fig.e... [26]. (a) LDO basic structure. unless for the LLVB case. and model the error amplifier and its equivalent output load. CA [23]–[26]. ). In this case. the VB is not used and the compensation is more complicated. conclusions are given in Section VIII. 1(b). may model either an external capacitor or the load offered by the interconnection lines in SoC applications ( 0. The external loop is due to the feedback of the output voltage through and . a standard Miller capacitor. Specifically.e. LDO basic structure. and ) may be neglected2 and models the small VB input capacitance. and is made up of a compensation capacitor. have different small-signal equivalent model and. ) while comprises the power MOS 2We assume that the resistance offered by the VB output node is sufficiently small to nullify the frequency contribution of the power MOS parasitic capacitances. provide a robust compensation strategy and design criteria which demonstrate the advantage of the proposed approach in LDO design for the three analyzed cases (HLVB. we propose three LDO voltage regulator topologies and. may be required to obtain proper compensation. Finally. A. the VB limits the overdrive voltage of the power device which requires more silicon area to provide the same load current. The compensation is achieved by amplifying with the Current Amplifier (CA). Therefore. In the case we do not use a VB and the error amplifier is directly connected to the power device. The current amplifier is represented by its input resistance and the current-controlled current source . models only the possible standard Miller compensation capacitor (i. Sections III. VB. V and VI investigate in detail the four different cases providing transistor level implementations and simulation results. no-buffered LDOs (NB). .GIUSTOLISI et al. applying this general model to all the cases summarized in Table I. The load capacitance. and model the second stage (i. . Finally. hence. ) and comprises both the VB gain and the power device transconductance (i. (b) compensation network. 2. represents the load whose current is supplied by the power transistor. elements . CA-LDO small-signal schematic. 2.e. It is worth noting that the value assumed by some model parameters depends on the presence or the absence of the voltage buffer. is inserted before the power transistor to decouple the high capacitive load seen at the gate of [1]. Fig. . Open-Loop Gain Modeling The generic regulator of Fig. 1 has two loops. . II. Moreover. Hence. A partition of the output voltage. The worst-case for stability occurs when the regulator is used in unity-gain configuration.: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS 1881 TABLE I CA-LDO CLASSIFICATION Fig. In this paper we develop a general and systematic model of the frequency response of CA-LDOs which takes into account the changes in the transfer function due to load current variations. in our modeling. 1. Finally. in the case we use a VB to decouple the EA from the power device. In addition. that is with and .e. as reported in Table I.. A design example with measurement results is reported in Section VII. is fed back through and to the non-inverting input of the error amplifier (EA) and compared to the reference voltage. the power stage and the possible voltage buffer) and the overall output load. . Elements . models the overall capacitor connected between the output node of the EA and the drain of the power device. may be required to properly compensate the circuit. HLNB and LLNB)..e. as we shall discuss in Section II. . In Section II. the power MOS parasitic capacitances (i. The internal loop is due to the compensation network. On the contrary. [24]. In the same figure. we carry out the necessary conditions for guaranteeing a minimum acceptable degree of stability over the whole load current range. A standard Miller capacitor. we may distinguish four types of CA-LDOs which. IV. their contribution must be included. Quite often a voltage buffer. in some configurations. The VB (whose gain is ) allows to relax the EA specifications and facilitates the compensation. If this is not the case. . require different compensation procedure. [2]. . . CA-LDO MODELING The schematic of a generic CA-LDO is shown in Fig. amplified by through the current amplifier. Finally.1–1 nF). . is mainly due to the gate-source and the gate-bulk capacitances of the power MOS (i.. especially in low-voltage design. Then. 1. the overall phase margin. This principle is very often applied in the design of multistage feedback amplifiers because it is simple from an engineering viewpoint and leads to robust implementations [21]. the EA output resistance.). takes the form (5) (9) The stability of the overall amplifier is certainly guaranteed and . The complete open-loop transfer function of the regulator modeled in Fig. the power MOS capacitances. etc. etc.. small factor). 9.) do not change significantly (no more than a factor of 2) and some others remain constant (i. . we can neglect the two zeros. In three-stage amplifiers a convenient choice is setting which guarantees a maximally flat response in the closed-loop gain of the internal loop and an overall phase margin of about 65 [21].e. SEPTEMBER 2012 gate-drain capacitance and the possible standard Miller compensation capacitor (i. which represents the gain-bandwidth product of the internal loop.1882 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. NO. [33].e. can be ensured by properly checking the stability of each single loop [23]. . . )..e. the current mirrors’ gain. as for (7). as shown in the Appendix A. Once the stability of the internal loop is guaranteed (i. [36]. [23]. Following these considerations. approximates the transition frequency of the internal loop and therefore (2d) (7) (2e) (4a) the phase-margin of the internal loop. is being the dc gain. . In particular. under the assumption that the internal loop has an acceptable degree of stability with small factor. The second-order polynomial in the denominator of (3) represents the closed-loop transfer function of the internal loop whose open-loop transfer function. setting ). 59. for a pure two-pole system. .e. for the poles of the closed-loop transfer function related to the internal loop are real [21].. specifically.. evaluated in terms of return ratio [23]. Assuming with a dominant pole. As far as is concerned. Finally. and the overall gain-bandwidth product. it is defined as the ratio between the second pole and the gain-bandwidth product and is related to the stability of the internal loop [21].. we can approximate (1) as [21] (3) where B. Specifically. In particular. we may define (4b) (8) (4c) but refers to the external (or which has a meaning similar to overall) loop. Stability Analysis The stability of systems that include more than one feedback loop. is approximately given by (1) where (2a) (2b) (2f) In order to guarantee stability. This large variation causes also if 3A more accurate expression that bounds and in [34] where. 2. extends over its operating range both and change within several orders of magnitude. VOL. we have together may be found . These latter quantities are related to and through (6a) (6b) (2c) and are not It is worth noting that the details of necessary as we are interested in their product. after few manipulation. on the ratio between the equivalent second pole of the external loop. the equivalent second pole depends on the closed loop transfer function of the internal loop and is approximately equal to . [23]. the internal loop may be responsible for two complex-conjugate poles [21].. The compensation of voltage regulators is more complex than three-stage amplifiers since we must take into account the large variation of the load current which may span within several orders of magnitude (e.g. As the load current. both the external and internal loops must be properly compensated. .e. [35]. If . [23]. Consequently. the internal loop is sufficiently stable and exhibits a phase margin with a small peak in the frequency domain (i. Moreover. the overall stability depends on the external loop and. [32]. Some other design parameters (i. If the phase margin is and the frequency response is maximally flat. the dominant pole of the internal loop and the second pole of the internal loop. the approach we adopt requires first ensuring the adequate stability of the inner loop so that we can proceed to the external one [21]. the gain-bandwidth product.3 being If . [23]. from to ). External and Internal Loop Stability (12) at the corresponding value of In the HLVB CA-LDO we neglect the power device parasitic capacitors (i. 3. the behavior of both and with has to be analyzed. that is . . and solving find the minimum of Fig. where the approximation holds for high .4 It is worth noting that and are both linearly related to the load capacitance . (11) we A. which is the same. . 3 are (15) The plot of versus is sketched in Fig. otherwise. Of course.1883 GIUSTOLISI et al. ) and are capable to work with a maximum load current of 100 mA and with a minimum drop-out voltage of 200 mV. In general. Stability parameters. since no standard Miller capacitor is required . if . then the minimum of can be assumed at the edge of the operating range. Note that also changes with the load current by several orders of magnitude. reaches its minimum at low load currents (low ) and remains constant at high load currents (high ). In the first region the load current lies in the operating range while in the second region a very small stand-by current. HIGH-LOAD VOLTAGE-BUFFERED (HLVB) CA-LDO (10) The HLVB CA-LDO is a voltage regulator with an off-chip output capacitor in the micro-farad range and a decoupling voltage buffer placed between the the error amplifier and the power device. On the contrary. it is easy to demonstrate that the output resistance of the power stage does not affect the stability since and are independent of . (12) and for .. however. 2. Hence. that is.: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS to change severely and so do both and thus making the compensation a delicate task. keeping both and higher than minimum targets. Stability of internal and external loops will now be analyzed in the four topologies identified in Section I. that is. relationships (10) and (11) turn into (13) (14) Fig. curs below (above) the operating range of . is forced through the power device. and . voltage regulators are designed to work in operating mode and in stand-by mode. The stand-by current can be equal or even much lower than the minimum load current. 4 (solid line) where a parabolic behavior is apparent in the range of interest. the minimum is reached (13) reveal that at infinite load current. a high stability degree would be desirable in the whole interval . Obviously. However. Therefore.e. observing that and coefficients in (2) are proportional to . we shall provide the proper compensation network capable of guarantee and . If the two regions are well separated. Capacitor stands for the input impedance of the voltage buffer and. is constant for low load currents and reaches its minimum at high load currents. that is. shifted to the left or to the right depending on the value of the load capacitor. [26]. 3 shows the trend of and as a function of for a generic CA-LDO that can be modeled as in Fig.35CMOS technology ( . . Let us study as a function of . . versus transconductance . setting makes the external loop stable for every value of or. . The voltage buffer helps stability and improves speed performance. and ) as their contributions are strongly reduced by the low output resistance offered by the voltage buffer. For each case. we can ensure the stability in the whole output current range or in the desired range of interest. it may be sufficient to guarantee stability just in the operating range and in stand-by mode where . The big capacitive load is used for stability reason and for reducing the undesired transient under/overshoots. 3 is not valid for . III. Hence. and . Note also that if the minimum of a generic parameter oc. solving (14) for yields (16) 4The plot of in Fig. if the operating region includes also the stand-by region. In this case. . All the implemented LDOs have been designed in a standard 0. that is. Substituting (2) into (8) and equating we find that presents a minimum for Substituting (2) into (4c). for every value of the load current. the curves in Fig. HLVB CA-LDO: circuit implementation. the minimum VB bias 5The adaptive biasing of the VB lowers its voltage gain down to high output currents. Bias current has been set to 2 leading to and . to decreases with and its minimum value is obtained when the load current is maximum (i. . we notice that both a high current gain. Transistors with the constant current source constitute the VB with adaptive biasing so to increase speed during fast load transients without affecting the current consumption at low loads. as sketched in Fig. ) moves to the internal node while the second pole experiences the pole-splitting effect. Third. using a lower external load capacitance may cause instability as (18) may no longer hold. and .. The VB input capacitance. such as the one in [37]. may be found from (4a) and (4b). Second. has been set to 20 ( . being the transconductance of the differential-pair transistors. we observe that is linearly related to and that it does not depend on the load capacitance. 4 (dotted line). if the regulator Fig. and the equivalent second pole. In the patterned region the circuit does not to satisfy the stability requirements. Observe that. Position of (solid line) and (dotted line) curves with respect . is given by the transconductance of . . we observe that the two poles are well separated and that the dominant pole is placed at the external node. The latter is shared with the EA and set also . has been designed for a given . Imposing . From (16) and (18) some considerations can now be drawn. As far as is concerned. 59. Specifically. the dominant pole (which depends on the equivalent compensation capacitor. is approximatively 500 fF. ). The overall CA gain is while its input conductance. ) and can be set as low as possible to reduce the power consumption. for high load currents. strongly help to relax constraint (18). If (16) and (18) are satisfied. the bias current of the CA may be further reduced using the structure discussed in Section IV for the HLNB case or using more efficient structures. for the HLVB CA-LDO. 4. Hence. The EA is a single-stage class-A folded-mirror operational transconductance amplifier (OTA) made up of transistors . substituting (16) in (18). provided that relationship (18) is guaranteed. Finally.. LDO Design The proposed circuit implementation of a HLVB CA-LDO is shown in Fig. .1884 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. 5. we find for the CA input (18) where we assumed . and substituting in (18). at . First. they turn into and . Transistor aspect ratios are reported in Table II. The CA is made up of current mirrors .e. 9. . ). NO. keeping low the input impedance of the voltage buffer helps in obtaining a reasonable value of . the presence of the VB limits the power supply to no less than 2. .5 V. The CA current gain. . .5 Obviously. Fourth. B. relationship (16) provides for the compensation capacitance. if necessary. at high load currents.e. we obtain for the CA input conductance. evaluating (13) for leads . which is satisfied setting . or a low VB input impedance. SEPTEMBER 2012 Fig. and . 5. the dominant pole. of gain . imposing conductance . the lower the capacitor that has to be integrated. at low load currents. it is clear that the higher the current gain. the stand-by region coincides with the lower bound of the operating region (i. . Hence. . of gain . VOL. Substituting (2) in (4c) yields for (17) Therefore. On the other hand. which is true for high . amplified by the Miller effect. Once the circuit is compensated. The regulator has been designed to work with a maximum load current of 100 mA and with a minimum external output capacitor of 1 . . which is true for satisfying (16). Imposing . Hence. stability is guaranteed in the whole range of load currents. thus yielding (19a) (19b) For low load currents (so that ) the two poles are approximated by and while. Substituting (2) in (8) yields for (22) 6All Monte Carlo simulation results have been carried out using 100 runs and considering both inter-die and intra-die variations. Open-loop gain and phase of the HLVB CA-LDO for different load . capacitors and are due to the power MOS parasitic capacitances ( . Hence we shall always be in the situation where . going from 1 mA . . as sketched in Fig. As expected. considering that is several orders of magnitude higher than the other involved capacitances. our LDO can operate correctly outside the interval where holds. (b) drop-out condition: . Monte Carlo simulations show a minimum phase margin of . we may approximate (10) and (11) into (20) (21) . The minand occurs at 1. HIGH-LOAD NO-BUFFERED (HLNB) CA-LDO The HLNB CA-LDO is a voltage regulator with an off-chip output capacitor in the micro-farad range and with no voltage buffer between the error amplifier and the power transistor. 8.5 mA) and in correspondence of the minimum value of . for (stand-by region) and for (operating region). In this point. . Fig. . Circuit Simulations Simulations are performed on the circuit in Fig. current. The nominal phase margin versus the load current is shown in Fig. 9 (solid line). Monte Carlo simulations report A. the minimum phase margin occurs at medium load current (about 1. 6 for different load currents. External and Internal Loop Stability Referring to the small-signal model in Fig. 5 where the bias current sources have replaced by their transistor-level implementation.1885 GIUSTOLISI et al. . 6. Considering both load regulation and under/overshoots. would Relationship (20) shows that. C. Fig. setting lead to an unreasonable value of which poses a serious drawback for the integration. 8 displays the transient response of the output voltage for load current going from 1 mA to 100 mA (at time ) and back to 1 mA (at time ). HLVB CA-LDO: transient response for to 100 mA and vice versa. . respectively. has been set to 4 has been chosen equal to 10 and the stand-by current. the maximum difference with respect to the desired is less than 0. The curves refer to the circuit connected in unity-gain feedback while experiencing a drop-out voltage of 200 mV. Fig. 7. The absence of the voltage buffer allows reducing the supply voltage but makes the compensation more critical due to the high capacitive value seen at the EA output node.5 imum value of 57 is achieved in correspondence with mA of load current. due to the parabolic behavior of . . 2. IV. current. a settling time of and for the low-to-high and the high-to-low cases. The rise/fall time of the current step is 1 .: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS TABLE II HLVB CA-LDO TRANSISTORS ASPECT RATIOS Fig. Phase margin of the HLVB CA-LDO versus the load current. (a) Buffer configuration: . 7. . Hence. . that is. The loop gain of the HLVB CA-LDO is shown in Fig. Finally. Drop-out condition: . .5%. However. ). the offset of the circuit was carried out through Monte Carlo simulations6 and a standard deviation of 21 mV over the entire load current range is apparent. area and power consumption). hence. imposing . we get for allows us to draw some considerations. to allow the OTA to operate in class-AB and overcome its inherent slew-rate limitations. we set the same CA gain of the HLVB CA-LDO. the dominant pole. that is and thus causing an overall current gain . At low or high load currents the two poles approximate as in the HLVB case. helps in reducing both the the compensation capacitor. they behave in a similar fashion. and the input conductance of the current amplifier. and used the approximation . Hence. First. set well above any reasonable value of . Due to the large capacitive load seen at the power MOS gate. the operating region (bounded by and ) cannot be set too wide as the ratio would lead to an unreasonable value of . 5 while transistors perform the adaptive bias stage for class-AB operation. of gain . as shown in Fig. using the same class-A OTA of Fig. Moreover. Specifically. . Third. NO. [39]. respectively. and the equivalent second pole. . As far as is concerned. from (27). in this CA-LDO. (that is. Referring to Fig. VOL. we guarantee the internal loop stability and find for the CA input conductance (26) where we assumed . for the HLNB CA-LDO. Transistor aspect ratios are reported in Table III. and . . it may be found in terms of . of gain . to permit low-voltage operation . substituting (22) into (29) (23) which represents the constraint for the compensation capacitor. As far as the stand-by region is concerned. 10 where elements inside the dotted boxes are included and the standard Miller capacitor (drawn in dashed line) is not present. current mirrors and make use of transistors and . Position of (solid line) and (dotted line) curves with respect . Substituting (2) in (4c) yields for (25) Therefore. where the approximation holds for Therefore. stability is guaranteed in the operating region range of load currents. Bias currents and have been set to 1 leading to and . Relationship (23) and (26) shall be used for designing the compensation network. The corresponding transconductance at results while at it increases up to . However. 10. . it is apparent that a high current gain. due to the large value of . Once the circuit is compensated. 9. Second. . With reference to the stand-by current. The latter is shared with the EA and set also . The minimum power supply is 1. we used the adaptive bias stage reported in [38]. In order to make an effective comparison. from Fig. 59. 5 would pose serious speed limitations in terms of slew-rate. which is true for high load currents. . The power MOS parasitic capacitances are and . The regulator has been designed to work with an operating load current ranging from to . the compensation capacitor is related to the square root of and using a higher external load capacitance may cause instability as (27) may no longer hold. further simplifying them into (27) (28) and solving for yields (30) which enables to choose the proper stand-by current of the power transistor. B. Transistors together with the bias current are used to set properly the required input CA admittance. (13) reduces to (24) which. are given by (19) where the internal capacitor is . The CA is made up of current mirrors .1886 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS.2 V. In the patterned region the circuit does not to satisfy the stability requirements. it is clear that a high current gain is essential to reduce the required . (28). The load capacitor has been set to 1 . If (23) and (26) are satisfied. . being the transconductance of the differential-pair transistors. 9. transistors constitute the same OTA core of Fig. imposing . LDO Design The proposed circuit implementation of a HLNB CA-LDO is shown in Fig. 9 we observe that it should be set as low as possible so to assure that the corresponding lies in the stand-by region defined by . 9 (dotted line). SEPTEMBER 2012 Fig. We have assumed a regulated output voltage equal to the reference voltage of 1 V. From (23). the minimum value for the phase margin occurs in the forbidden range (i.e. . The curves refer to the circuit connected in unity-gain feedback while experiencing a drop-out voltage of 200 mV. Circuit implementation of HLNB and LLNB CA-LDOs. The of load current. Because of inter/intra-die variations. 13 displays the transient response of the output voltage for load current going from 1 mA to 100 mA (at time ) and back to 1 mA (at time ) at (drop-out condition) and (power MOS in saturation region). Monte Fig. . Fig. The undershoots and overshoots are less than 2. Phase margin of the HLNB CA-LDO versus the load current. has been chosen equal to 10 . we got . 12. Above 500 minimum value is 33 and occurs at 100 the phase margin is greater than 45 . . In the LLNB CA-LDO elements inside the dotted boxes are removed and capacitor 1887 is TABLE III HLNB CA-LDO TRANSISTORS ASPECT RATIOS Setting and using (23). As designed. from (30). removed. 12. 10. respectively. where it drops down to at . 11 for different load currents. ). Fig. 11. Setting in (26). In the HLNB CA-LDO elements inside the dotted boxes are present while capacitor is present. thus guaranteeing an acceptable degree of stability. the stand-by current. Open-loop gain and phase of the HLNB CA-LDO in buffer configura.: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS Fig. the average phase margin is about 65 with a standard deviation of 11 . The rise/fall time of the current step is 1 . Circuit Simulations Simulations are performed on the circuit in Fig. C. Drop-out condition: . we obtained to which was implemented using the common gate stage with the extra current . The nominal phase margin versus the load current is shown in Fig. Finally. at the minimum operating load current.GIUSTOLISI et al. As expected. Carlo simulations report a settling time of and for the low-to-high and the high-to-low cases.5% and 3%. tion for different load current. This large value is mainly due to the . respectively. The loop gain of the HLNB CA-LDO is shown in Fig. . 10 where the bias current sources have replaced by their transistor-level implementation. Monte Carlo simulations report a standard deviation dc offset of 60 mV over the entire load current range. where we assumed . as shown in Fig. ). LOW-LOAD NO-BUFFERED (LLNB) CA-LDO (37) The LLNB CA-LDO is a voltage regulator with a low capacitive load in the order of thousands of picofarad and with no voltage buffer between the error amplifier and the power transistor. Position of (solid line) and (dotted line) curves with respect . the dominant pole is always placed at the internal node of the circuit while the second pole experiences the polesplitting effect. 14 (solid line). In the LLNB CA-LDO. SEPTEMBER 2012 More specifically. Substituting (2) in (8) yields for (35) Fig. which simplifies into (34) Fig. Hence. its minimum point is given by (11). that is For high load currents the dominant pole remains unchanged while the second pole turns into (33) (42) (41b) . In the patterned regions the circuit does not to satisfy the stability requirements. Hence. Buffer configuration: going from 1 mA . for the LLNB CA-LDO. This leads to a precise relationship between capacitors and . capacitor accounts for the gate-to-ground power MOS parasitic capacitances (i.e. (i.. 14. we find that load currents. the minimum value of occurs for . . to obtain proper compensation in terms of . 13. 10. 14 (dotted line). ) while capacitor represents the overall gate-to-drain capacitive contribution. For low load currents the two poles simplifies into (41a) typically locates at medium Examining (31). HLNB CA-LDO: transient response for to 100 mA and vice versa. it is sufficient to set . (38) being a scaling factor satisfying (39) Once the circuit is compensated. The absence of the voltage buffer allows reducing the supply voltage but makes the compensation critical due to the high capacitive value seen at the EA output node. 2. External and Internal Loop Stability Referring to the small-signal model in Fig. different statistical behavior of the NMOS and the PMOS transistors which realize the two current sources. Therefore. Fig. as sketched in Fig. (33) obliges adding a standard Miller capacitor to properly compensate the internal loop as on its own is barely sufficient. Following the details in Appendix B. This voltage regulator is functional for powering low-voltage on-chip circuitry in mixed signal applications or in SoC environments. As far as is concerned. It is apparent that. Consequently. (12) and (13) reduce to (31) (32) (40a) (40b) where and . is even smaller than any minimum the minimum point. value of .1888 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. The low capacitive load models the interconnection power supply lines that extend over the chip or a part of it.. 59. VOL.e. 9. NO. due to the small value of (on-chip load). the internal loop is compensated by setting in (32). we obtain the design equations (36) V. under the reasonable assumption that . the dominant pole and the equivalent second pole result A. as for the other CA-LDOs. . The phase . C. The average phase margin is about 90 with a standard deviation of 6. since it may also take the input conductance to infinity. respectively. the EA makes use of the adaptive bias stage reported in [38]. due to the low capacitive load. have the same aspect ratios of the corresponding transistors in the HLNB voltage regulator and are reported in Table III. Monte Carlo simulations reveal a gain margin of 27 4. respectively. if the regulator has been designed for a given . 17 displays the transient response of the output voltage for load current going from 1 mA to 100 mA (at time ) and back to 1 mA (at time ) at (drop-out condition) and (power MOS in saturation region).2 V. The power MOS parasitic capacitances are and . 10 where elements inside the dotted boxes are to be removed and the standard Miller capacitor (drawn in dashed line) is present. that is and thus causing an overall current gain . . Circuit Simulations Simulations are performed on the circuit in Fig. the minimum Fig. which was not considered in our analysis. The minimum power supply is 1. We have assumed a regulated output voltage equal to the reference voltage of 1 V. that is. (b) The maximum Gain margin occurs margin has no direct relation with is at its minimum value. at medium load current. 16(b) shows the nominal gain margin of the voltage regulator just to show that the maximum value occurs at medium load current . Fig. 1889 Fig. this would mean either increasing or decreasing and once again a new trade-off between area (in terms of compensation capacitors).5 dB. fine adjustment can be accomplished by trial-and-error in order to further reduce the compensation capacitors and the area occupation. that is . leading to and . The curves refer to the circuit connected in unity-gain feedback while experiencing a drop-out voltage of 200 mV. it must be chosen judiciously and a trade-off between area (in terms of compensation capacitors) and power dissipation (in terms of current required for generating ) is apparent. Note that the minimum phase margin is higher than that forecasted by the theory because of the LHP zero in (2c). Also in this case. we find that hence we choose . Phase and Gain margin of the LLNB CA-LDO versus the load current. (a) The minimum phase margin occurs at minimum load current. from (39). 15 for different load currents. the undershoots and overshoots are about 12% and 16%. [39] to drive the power MOS gate properly. These simulated values of phase and gain margin reveal that the circuit has a high degree of stability and that our equations overestimate the necessary compensation capacitors. First. Hence. The input CA admittance. Applying (36)–(38) we get . the scaling factor may be increased by increasing the right-hand side of (39). shared with the EA. However. Fig. is set by the transconductance of . Bias currents and have been set to 1 and 10 .6 . when is at its minimum value. Fourth. However. 16. a higher capacitive load may cause instability. that is. also in this case. Aspect ratios of and are 6/1 and 24/1. Open-loop gain and phase of the LLNB CA-LDO in buffer configura. from the analysis of . In order to make an effective comparison. The loop gain of the LLNB CA-LDO is shown in Fig. Third. Transistors and the power transistor. As expected. and . a high scaling factor is advisable as it plays a significant role in reducing both the compensation capacitors and . The CA is made up of current mirrors . tion ( B. of gain .GIUSTOLISI et al. of gain . power dissipation (in terms of the stand-by current required for generating ) and speed (in terms of ) is apparent. The regulator has been designed to provide a maximum load current of 100 mA with an equivalent capacitive load of 100 pF. respectively. Second. The nominal phase margin versus the load current is shown in Fig. 16(a). LDO Design The proposed circuit implementation of a LLNB CA-LDO is shown in Fig. 10 where the bias current sources have replaced by their transistor-level implementation. . a high current gain helps in reducing the required . Setting and . 15. . if required. The rise/fall time of the current step is 1 . In this point. ) for different load current. and . we set the same CA gain of the other CA-LDOs.: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS From (36)–(39) some considerations can be drawn. when phase margin occurs at the minimum load current. These values . The circuit is stable and fast but. the small signal model in Fig. we obtain the value which nullifies the potential benefits of the of 45 pF for current-amplifier approach. in case of low capacitive load. has been set . Buffer configuration: going from 1 mA . . Positive and negative overshoots stay below 70 mV while the settling time. not shown in this discussion). 20 displays the measured transient response of the output voltage for the load current going from 1 mA to 50 mA and back again to 1 mA with a rise/fall-time of about 1 . VOL.e.1890 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. . . 18. 10 following the design criteria in Section V and using the standard 0. in the LLVB CA-LDO. From (43). for a given value of (set by the con. . Compensation capacitors have been and . 59.5 . 18. while the stand-by current. As expected. A. NO. The circuit is suitable for SoC operation and has been designed to provide up to 50 mA of load current with a supply voltage of 1. assuming a capacitive load of 100 pF and the reasonable value of 20 pF for . [28] and can be further reduced by adopting one of the techniques proposed in [16]. 19 shows the measured load regulation at for three different values of power supply. The stability has been imposed setting and to 15 . . The power MOS transistor has been designed with an aspect ratio of 50000/0. As an example. asitic capacitances. The chip photo of the LLNB CA-LDO is shown in Fig.. CASE STUDY As a further validation of the proposed methodology. Finally. (45) reveals leads to a prohibitive value of that the benefit of reducing through a high current gain is completely lost by a severe augment in . provided that there are no requirements for low voltage power supply. (i. 2 is inaccurate to describe the circuit behavior and must be completed considering the pole associated to the output resistance of the voltage buffer. the main contribution to area occupation is due to the power MOS and the two compensation capacitors.4 . making straint small through a high value of . a voltage buffer is not recommended. Including the above-mentioned term. 7In the example we assumed . The chip area is about 0. LOW-LOAD VOLTAGE-BUFFERED (LLVB) CA-LDO The LLVB CA-LDO is a voltage regulator with a low capacitive load in the order of thousands of picofarad which makes use of a voltage buffer between the error amplifier and the power device. Bias currents and have been set to 1. . because of inter/intra-die variations. SEPTEMBER 2012 Fig. are in line with similar works [15]. VI. we find that the minimum of results (43) where we introduced (44) accounts for the gate-to-ground power MOS parand where ). Fig. 17. The maximum expected on-chip load capacitor is 1 nF [31]. Monte Carlo simulations report a settling time of and for the low-to-high and the high-to-low cases. we integrated the LLNB CA-LDO in Fig. [18]. respectively.7 As a consequence. 9. In fact. From another point of view.2 V and a drop-out of 200 mV.35CMOS technology used for simulations. equating we obtain the value of the required standard Miller capacitor (45) Relationship (45) poses a serious limitation to the LLVB topology. takes about 4 . leads to a small (approximatively ) which. Just to have an idea set to of the benefits of the capacitive multiplication through current amplifiers. External and Internal Loop Stability In this case. The overall current gain has been set to with and . we note that a pure standard Miller compensation approach would require more than 300 pF. .6. LLNB CA-LDO: transient response for to 100 mA and vice versa. In few words. VII. Fig. Chip photo of the LLNB CA-LDO voltage regulator. the advantage of the current amplification is absent and the circuit is better stabilized with a standard Miller compensation only. in turn. Monte Carlo simulations report a standard deviation dc offset of 11 mV over the entire load current range. . Fig. . FINAL REMARKS AND CONCLUSIONS Fig. its contribution is not critical to stability and may be neglected in the design phase. The approach has been developed for all the possible cases reported in Table I and. From Table IV. However. 16 and discussed in Section V-C). internal loop stability requires a further standard Miller compensation capacitor. [40]. 20. VIII. (2c). the voltage buffer removed. 21. A lower implies a better slewing performance. in Table V we reported the worst placement of the two zeros with respect to the for the three LDO VRs designed in the paper. On the contrary. a voltage buffer has been demonstrated to worsen stability since it imposes the use of a large standard Miller compensation capacitor which nullifies the potential benefits of the current-amplifier approach. To prove the validity of the approximation. Measurement results of . As far as the LHP zero is concerned. Fig. we neglected the two zeros in (2b). hence. Phase margin versus the load current for different ESR values. In regulators with high (external) capacitive load where a voltage buffer between the error amplifier and the power device is used. (b) HLNB. for three of them. back to 1 mA ( for going from 1 mA to 50 mA and ). which present a definitely lower capacitive load. The figure of merit (46) used which is an extension of the in [14]. . if low-voltage operation is required and. it is apparent that the proposed LDO has the best which is from 4 to 9 times lower than that of other designs.: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS 1891 Fig. LDO voltage regulator topologies have been proposed. In this paper. The advantage of current amplification still holds when the power device is driven directly by the error amplifier. The last row of the table refers to the LLNB CA-LDO discussed in Section VII. we have presented a robust compensation technique for LDO regulators which make use of Miller compensation with current amplifiers in order to reduce the compensation capacitor. the compensation technique is particular advantageous over the whole load current range and does not relies on the ESR to compensate the regulator (see Appendix C). 19. APPENDIX A EFFECT OF THE ZEROS In deriving our theory.GIUSTOLISI et al. the maximum capacitive capasipation efficiency bility and the area occupation in terms of compensation capacitor . TABLE IV PERFORMANCE COMPARISON BETWEEN RECENT WORKS ON SOC LDOS Internal capacitive load (SoC) Estimated load capacitor 10 pF Table IV provides comparison between performance of the proposed LDO regulator and other published designs that are targeted for SoC power management. Similarly. it affect the phase margin in the LLNB case only (as shown in Fig. that since the RHP zero depends on . in the LLNB CA-LDO a minimum bias current is required to flow in the power MOS to prevent possible instability. Note however. It is apparent that the RHP zero does not affect the stability being always well beyond the of the circuit. the compensation benefits can be still achieved but in a restricted load current operating range. (a) HLVB. In on-chip regulators. Load regulation of LLNB CA-LDO at different supply voltages. is adopted here to evaluate the speed in terms of settling time in different designs with respect to the dis. 2008. APPENDIX C EFFECT OF THE ESR ON HL VOLTAGE REGULATORS which. In both cases. “25 mA LDO with 63 dB PSRR at 30 MHz for WiMAX. [8] S. D. Oct. [7] X. “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. [9] K. Palumbo. J. 2002. vol. 250–254. II. pp. vol. “An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement. pp. “A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application. “Reverse nested Miller compensation using current buffers in a three-stage LDO. pp.-H. Circuits Syst. Circuits Syst. “Performance evaluation of CMOS low drop-out voltage regulators. Palumbo and S. 1265–1272. Lett. “A fast-transient low-dropout regulator with load-tracking impedance adjustment and loop-gain boosting technique. no. 2006. 21. H. Sep. 57. Zhan and W. C. N. 2008. pp. 4. 40. “A robust frequency compensation scheme for LDO regulators. pp. Mok. 6. 757–761. II. 3. Allen. “Output-capacitor-free adaptively biased lowdropout regulator for system-on-chips.. P. Dokania and G. Sun.” IEEE J. VOL. Silva-Martínez. and T. 9. Lin. pp. “A compensation strategy for two-stage CMOS Opamps based on current buffer. T. K.” IEE Electron. Man. [3] C. pp. Solid-State Circuits. vol. 1041–1050. 853–857. 38. 2005. pp. the denominator in (38) must be positive as well. vol. 59. Circuits Syst. Jan. Parsons. Y. few words should be spent on the effect of the ESR on the stability. T. pp. May 2010. 4. Allen. Z. Boston. Y. 52. . II. 22.” in Proc. Borkar. Lett. 5–10. Circuits Syst.” IEEE J.” IEEE Trans. TABLE V WORST PLACEMENT OF THE ZEROS REFERENCES APPENDIX B COMPENSATION OF THE LLNB CA-LDO in Equating we get in (35) and collecting the terms (47) where (48) Relationship (47) is a quadratic equation whose solution is (49) Setting (50) we find for (51) and. I. Circuits Syst. Guo. N. Substituting (51) in (33) and solving for we get the second design equation in (37). N. II. Hazucha. IEEE ICECS 2002. IEEE ISCAS 2007. Ho and P. the same ESR. vol. 1691–1702. C. 2010. 9. vol. Finally. Jul. and Y. “Development of single-transistor-control LDO based on flipped voltage follower for SoC. May 2002. vol. Rincon-Mora and P. Silva-Martínez. Sep. 5. 2003. M. Furth. A. Tantawy and E. for the two HL voltage references. 2010. [20] G. 2010. Zhao. and K. 10. it is apparent that the presence of the ESR is not critical to the circuit stability. no. no. we observe that the presence of [1] G. 1. M. A. Apr..” IEEE Trans. 46.” IEEE Trans. Xie. Lai. Circuits Syst. and M. chip-area-efficient output-capac[19] J. Leung and P. [2] G. “A low voltage low quiescent current low drop out regulator. K. [18] C. 38. II. K. Jun. J.” IEEE Trans. Chang. and J. pp.-C. 2. Rincon-Mora and P. Oct. 33. 1300–1302. [14] P. Jun. “A 3-A CMOS low-dropout regulator with adaptive Miller compensation. 9. [15] T. Circuits Syst. that is (52) leads to the constraint in (39). I.” IEEE Trans. 6. vol. Circuits Signal Process. Rincòn-Mora. J.. Shen. 1392–1401.” in Proc. 51. pp.” Analog Integr.” IEEE Trans. “Area-efficient linear regulator with ultra-fast load regulation. Guo and K. Leung. Karnik. 15. Sep. 1998. vol. pp. [21] G. IEEE MWSCAS 2004. [11] H. “A 6itorless LDO in 90-nm CMOS technology. and P. N. pp. Rashid. Z. and S. Circuits Syst. pp. 2002. no. 257–262.” IET Electron. Solid-State Circuits. Guo. 57. 1997. 55. Y. Garimella. 49. On the contrary. Wang. NO. Leung. [10] C. 825–828. no. 57. K. [12] L. 45. Brauer. no. 933–940.” IEEE Trans. no. vol. 44. 2005. 1080–1081. no. vol. X. 1998. K. 2007. pp. vol. vol. Mok. no. Ki. 10. “A frequency compensation scheme for LDO voltage regulators. and K. 563–567. T. vol. 2004. 5. 3828–3831. [16] E. we easily obtain the first design equation in (36). W.” IEEE Trans. Yeung. solved for The two HL voltage regulators have been designed without considering any LHP zero caused by the ESR of the load capacitor. pp. 2010. Wu. no.-H. T. pp. vol. pp. Leung. K. Feedback Amplifiers (Theory and Design). Obviously. does not alter the phase margin of the HLNB VR significantly. P. Mok. 80–84. N. vol. II. Circuits Syst.” IEEE J. Finan. no.” IEEE Trans. Jun. “Cancellation of load regulation in low drop-out regulators. vol. A. Mar. Leung. Zhang. Or and K. Leung. However. vol. MA: Kluwer Academic. Mok. Y. SEPTEMBER 2012 the ESR increases the phase margin. 5. [5] R. [13] P.” IEEE Trans. Chava and J. [4] R. Y. Palmisano and G. Feb.1892 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. 703–708. Apr. I. [17] A. pp. Jul. no. substituting (48) in (50) and solving for we get the third design equation in (38). 2004. since the load capacitor is an external component. T. Circuits Syst. Chan. no. “Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators. vol.-Y. no. [6] H. To this aim. A. since must be positive. Yan. E. no. Solid-State Circuits. For the HLVB case. pp. 2010. 1896–1905. “Optimized frequency shaping circuit topologies for LDOs. K. Chava and J. 141–144. 57. B. E. no. K. we simulated the phase margin behavior with respect to the load current for the ESR ranging from 0 to 1 and reported the results in Fig. 45. Pennisi.” IEEE J. 1. Bloechel. “Design of high-performance voltage regulators based on frequency-dependent feedback factor.” in Proc. N. Solid-State Circuits. 1017–1028. considering that . Lee. I. Oct. 9. 55. Leung. His research interests include analysis. Giustolisi and G. 520–529. 709–737. pp.” in Proc. May 2005. II. Nov. in 1999. She received the Laurea degree (cum laude) in electronic engineering and the Ph. Al-Shyoukh. Carvajal. D. 2. Gaetano Palumbo was born in Catania. 227–233. Since 2000 he is a full Professor in the same department. From 2006 to 2007. Nov. 40. and R. 53–80. IEEE ISCAS 2008. 9. The research of her Ph. May 2008.” Analog Integr.” IEEE Trans. vol. Feb. [31] G. Spain. K. WA. Spitale. Palumbo. Pennisi.” IEEE J. Lau. pp. In all these fields he is developing some the research activities in collaboration with STMicroelectronics of Catania. 42. pp. May 2011. [29] G. no. Italy.” ETRI J. and P. Pennisi. Ester Spitale was born in Catania. low-voltage circuits. Marano. and S. 192–198. [25] W. no. 2007. 4. 116–119. G. Sánchez-Sinencio. Sep. and S. 2685–2688. 1879–1890. now DIEEI (Dipartimento di Ingegneria Elettrica Elettronica e Informatica). G. 49. and K. Seattle. II.” IEEE J. he is Associate Professor at Dipartimento di Ingegneria Elettrica Elettronica e Informatica(DIEEI).” IEEE Trans. 26–32. Palumbo. D. Solid-State Circuits. and a textbook on electronic device in 2005. 54. has concerned linear regulators. Circuits Syst. 2007. pp. [34] G. no. 2002. 12. and M. Palumbo. and E. 2001. [32] P. K. “Analytical comparison of frequency compensation techniques in three-stage amplifiers. Then. G. J. 1995. respectively. “An approach to test the open-loop parameters of feedback amplifiers. and S. López-Martín. 70–75. From June 1999 to the end of 2001 and from 2004 to 2005 he served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I for the topic Analog Circuits and Filters and Digital Circuits and Systems. current-mode approach. and S.” in Proc. pp. Jun. 2007.. J. Carvajal. 38. 9.. Giustolisi.” in Proc. G. he served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II. 755–759. vol. Feedback Amplifiers: Theory and Design. 2681–2684. pp.” Int. vol.. Mok. 3. Pennisi. Currently.-H. vol. J. University of Catania. 2010. 67. ECL and SCL Digital Circuits). Giustolisi. Pennisi. vol. P. vol. Solid-State Circuits. Milliken. II. and high-performance building blocks focused on achieving optimum speed within the constraint of low power operation. Appl. 8. 805–817. A.. pp. J. Hurst and S. Italy. “Comparison of the frequency compensation techniques for CMOS two-stage Miller OTAs. Giustolisi. Since 2011 he has been a member of the Board of Governors of the IEEE CAS Society. “A low-voltage CMOS lowdropout regulator with novel capacitor-multiplier frequency compensation. “Determination of stability using return ratios in balanced fully differential feedback circuits. Y. “A simplified method of feedback amplifier analysis. 2000. Rosenstark. “Dual-loop feedback for fast low dropout regulators. Palumbo. Circuits Syst.” IEEE J. “Full on-chip CMOS low-dropout voltage regulator. in 1964. In 2003 he received the Darlington Award. vol. vol. Mok. pp. 2008. Sep. [30] G. pp. Man. Palumbo. and E. electronics for digital systems and basic electronics. in 1980. subsequently becoming Associate Professor in 1998. pp. [36] A. degree in electrical engineering from University of Catania. 2. Shen. degree from the University of Catania in 1993. 1.GIUSTOLISI et al. and R. G. Grasso. J. Yan. Aug. Catania. Pennisi. degree in electrical engineering from the University of Catania.D.D.. no. pp. Aug. 2008. vol. T. Yue. 5. J. and R. “Active capacitor multiplier in miller-compensated circuits. no. “Low-voltage LDO compensation strategy based on current amplifiers. Jan.. pp. Educ. . P. in 1995 and 1999. vol. 36. 11. Mar. Italy. in 1971. Perez. in 2004 and 2009. “Analytical comparison of reversed nested Miller frequency compensation techniques. pp. E-17. G. 55. 1068–1077.” IEEE Trans. adiabatic circuits. “Design methodology of Miller frequency compensation with current buffer/amplifier. no. T. vol. and E. 54. Palumbo. Solid-State Circuits. no. 1893 Gianluca Giustolisi was born in Catania. [27] S. 1974.D.. Grasso. pp. 3. N. K. Aloisi. Palumbo. Solid-State Circuits. vol. His primary research interest has been analog circuits with particular emphasis on feedback circuits. 1099–1103.: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS [22] A. 658–664. Palumbo was the co-author of three books: CMOS Current Amplifiers. IEEE ECCTD 2007. Silva-Martínez. In 2005 he was one of the 12 panelists in the scientific-disciplinare area 09—industrial and information engineering of the CIVR (Committee for Evaluation of Italian Research). Circuits Syst. “Low-voltage super class AB CMOS OTA cells with very high slew rate and power efficiency. Since 2008 he has been serving as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I. pp. G.” IEEE Trans. G. Palumbo. 231–239. He received the Laurea degree in Electrical Engineering in 1988 and the Ph. 42. 35. Spitale.” in Proc. Rincon-Mora. no. 2008. Seville. G. 2007. D. “A low-dropout regulator for SoC with Q-reduction. all by Kluwer Academic Publishers. Chen. [26] M. [33] S. K. no. pp. Circuits Syst. Lewis. Ramírez-Angulo. vol. “Analysis and comparison of class AB current mirror OTAs. IEEE ISCAS 2008. Grasso. and S. Circ. which has the aim to evaluate the Italian research in the above area for the period 2001–2003. [24] G. Leung. In 1994 he joined the DEES (Dipartimento Elettrico Elettronico e Sistemistico). 2001 and 2005. pp. 42. his research has also embraced digital circuits with emphasis on bipolar and MOS current-mode digital circuits. no. with particular emphasis on compensation techniques in SoC low-voltage applications. 32. Jan. Italy. respectively. Since 1993 he conducts courses on electronic devices. 1732–1742. respectively. [35] A. “A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation. G. Mok. Sep. I. vol. no. Theor. Circuits Signal Process. He is the author of over 350 scientific papers on referred international journals (150) and in conferences. [39] M. “A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement. modeling and design of analog integrated circuits and systems with particular emphasis on non-linear and low-voltage applications. at University of Catania as a researcher. Aug. D. [40] T. 4. T. Italy. 1265–1269. Appl. Ki. dealing with power conversion devices and industrial products. S. He received the Laurea degree (cum laude) in electronic engineering and the Ph. “LDO compensation strategy based on current buffer/amplifiers. and is co-author of several patents. 2008. H. Chan. respectively.D. L. Palumbo.” IEEE Trans. 2. [28] R. Baswa. pp. Dec. [23] W. vol.” IEEE J. Zhao. Lee. no. Spitale. compensation techniques. pp. She is currently working at STMicroelectronics as an analog IC designer. I. IEEE PESC 2001.” Int.” IEEE Trans. Dec. “A 50-mA 1-nF low-voltage low-dropout voltage regulator for SoC applications. and Model and Design of Bipolar and MOS Current-Mode Logic (CML. 2007. Y. Prof. and E. [38] A. [37] Z. no. W. Circuits Syst. developed at the Dipartimento di Ingegneria Elettrica Elettronica e Informatica(DIEEI) of the University of Catania. 1. vol. Catania. Circ Theor. 2010.” IET Circuits Devices Syst.