B.tech Project Guidelines and Schedule

1. I.GUIDELINES FOR CONDUCT OF B TECH FINAL YEAR PROJECTS 2014-15 1. Procedure for the Preparation of Project Description Document (PDD): 2. 3. 4. 5. 6. 1 a. Each faculty member should give five to six projects (problem definitions) along with description in the form of a project description document (PDD) by 11th AUG 2014 to the project coordinator. The format for the same is available with the departments. b. The project coordinator should conduct a PRC meeting to evaluate the PDDs submitted by the faculty on 14th AUG 2014. c. The suggestions made by the PRC to be intimated to the faculty and the corrected PDDs to be collected before 18th AUG2014. d. A single spiral bound booklet to be prepared containing all the PDDs given by all the faculty members and copies of the same may be maintained in the department. e. A soft copy (in pdf format) containing all the PDDs to be prepared and sent to all the students through email by 2nd Dec 2014. f. The soft copy to be also made available in the college portal by 02 nd Dec 2014. The project schedules containing the duration and deadlines for all the project related activities to be intimated to the students by 02nd Dec 2014. Procedure for Formation of Project Batches: a. Project batches should not contain more than three students. The project batches made according to section wise. b. Department-wise merit list containing top 34%, middle 33%, and bottom 33% of the students in the department to be prepared and intimated to the students by 31st JULY 2014. c. Each student from the top 34% should be allowed to select one student from middle 33% and another from bottom 33% as project batch members. d. Formation of batches to be completed by 14th AUG 2014. Procedure for Allocation of Projects and Project Guides to Students: a. Allocation of projects to be done based on the merit list by conducting counseling sessions on or before 19th Dec 2014. b. During the counseling session, top 34% students along with their batch members to be called in the order of merit and to be made to select the project from the list of projects given in the PDD. c. The students should select a project that is not already allotted to a previous batch in the order of merit. d. The project guide for the students should be the faculty member, who has proposed the project. Procedure for Formation of Project Evaluation Committee (PEC) a. The committee to be formed with the following members: i. Head of the Department ii. Project coordinator iii. Two senior faculty members of the department iv. One additional senior faculty member from other department if warranted v. Internal and external guides Procedure for Submission and Evaluation of Project Abstracts: a. Project abstracts in the prescribed format attested by the project guide to be submitted by all the project batches by 27 th Dec 2014 to the project coordinator. b. The project coordinator should conduct a PEC (Project Evaluation Committee) to assess the quality of abstracts. c. Quality assessment of abstracts and rejection or acceptance to be declared by 31st Dec 2014. d. Students whose abstracts are selected should start the project work from 02nd Jan 2015. e. Students whose abstracts are rejected should resubmit their abstract with corrections suggested by the faculty by 31st Dec 2014. f. If the abstracts are rejected after resubmission, students are not allowed to do the project for this academic year. 7. Procedure for Establishment of Project Laboratories: a. The PDDs given by all the faculty members to be consolidated on the basis of hardware and software requirements. b. A list of various hardware and software requirements to be prepared based on the consolidation made. c. A project laboratory satisfying the listed hardware and software requirements to be established by 15th Dec 2014. 8. Technology training to be conducted for the students in platform areas during literature survey phase. 9. Students are not to be allowed to take up any projects outside the college. 10.Students are allowed to do only experimental projects and no study projects are allowed. 11.Each student has to pay Rs.5000 towards the project expenses on or before 22nd Dec 2014. 12.Students having more than 15 backlogs are not to be made eligible for doing project work. 13.Procedure for Conducting Domain Knowledge and Platform Knowledge Test: a. Students to be tested in domain area after literature survey phase and platform area after design and analysis phase during project work. b. The project guides should prepare a descriptive question paper containing 5 questions in the domain area of the project each carrying two marks for each project they are guiding. c. Similarly, 5 questions to be prepared in the platform area of the project. d. Common question paper for two different projects may be prepared if the domain and platform areas of both the projects are same. e. Each test to be conducted and evaluated for 10 marks. f. Students to be allowed to proceed to the next phase only if they secure qualifying score (at least 60%) in each test. g. Project guides should intimate the syllabus for the domain knowledge and platform knowledge tests to their students well in advance. 14.Procedure for Conducting Project Written Examination: a. A project written examination to be conducted at the end of the semester for all the students who successfully complete the all the phases of the project. b. The examination should contain 40 multiple choice/fill-in-the-blank questions prepared by project guides for each project they are guiding. c. The questions to be given from domain and platform areas of the project and may include questions on design, analysis, and testing phases of the project. d. The examination should be conducted and evaluated for 40 marks. 15.All the student presentations of projects and viva voce examinations will be video shot and copy of it will be given to the candidates in the form of a CD. 16.Procedure for Project Seminar Presentations: a. All the project seminar presentations must be made by the students by preparing a PowerPoint presentation over a LCD projector. b. Before the presentation the students should get the approval for proceeding with the seminar from the project guide. c. All the students in the project batch must be present and participate in the seminar. d. Seminar presentations to be evaluated by PEC for 15 marks. 2 3 2014 6 Allocation of Projects 19th Dec. 2015 (10 Marks) 1 Day 12th Jan. Project Report Submission (40 Marks) e. 2015 3 Weeks 6th Feb. Review of Project Manuscripts and Intimation of Corrections d. 2015 (15 Marks) 1 Day 16th Jan. Submission of Manuscript Copy of the Project b. Viva Voce Examination (video shoot) (30 Marks) 4 1 Day 1 Day . Presentation of project work (video shoot) (40 Marks) f. 2015 Implementation Phase 3 Weeks 2nd Mar. 2014 9 Commencement of Project Work 2nd Jan. 2015 (10 Marks) 1 Day 7th Feb. Project written examination (40 MCQ/FIB) (40 Marks) c.III. 2014 4 Preparation and Display of PDDs 2nd Dec. PROJECT SCHEDULE FOR B TECH FINAL YEAR – 2014-15 S.No Duratio n Activity Deadline 1 Display of Project Schedules 28th July 2014 2 Preparation and Display of Merit Lists 31st July 2014 3 Formation of Project Batches 14th Aug. 2014 5 Establishment of Project Laboratories 15th Dec. 2015 Result Analysis 1 Weeks 9th Mar 2015 1 Day 10th Mar 2015 1 Day 11th Mar 2015 1 Weeks 18th Mar 2015 1 Week 25th Mar 2015 1 Week of April 2015 1 Week of April 2015 10 Literature Survey 11 Domain Knowledge Test 12 Project Seminar I 13 Design and Analysis Phase 14 Platform Knowledge Test 15 Project Seminar II 16 17 End Semester Project Examination a. 2014 8 Quality Assessment of Abstracts and Abstract seminar 31st Dec. 2015 (15 Marks) 1 Day 11th Feb. 2015 1 Weeks 9th Jan. 2014 7 Abstract Submission 29th Dec. Design Of An Efficient And Optimized Algorithm For Serial-Parallel Multiplication Using Aop 5 Page No. Prof. Design Of High Frequency Low Pass/High Pass Filter Using Microstrip Lines. Design Of Waveguide Windows For Variable Reactances – Implementation And Testing 1. Name Of The Faculty Prof.V. 1. Simulation Of Rectangular Micro strip Antenna Using HFSS Software – Performance Evaluation 3. 4. Design And Implementation Of 8-Psk System In AWGN Channel Using Matlab 3. A Modified Approach For Symmetric Key Cryptography Based On Blowfish Algorithm 2. Assoc. Ms. & Hod 4. Design . Ganesh Assoc. Design And Simulation Of Probe Feed A Square Microstrip Antenna V Mr. Array Of Two Horn Antenna For More DirectivityHardware Implementation And Testing 2.Pro f.V. Design And Implementation Of FDMA System For Wireless Communications VII Mr. A High Performance Binary To Bcd Converter For Decimal Multiplication 5. K. M. Prof.2. 2. Sireesha III Assoc. Design And Microstrip Feed Rectangular Microstrip Antenna 2. Prof. INDEX OF THE PROJECTS (GUIDE WISE) Sl No .Kumar Swamy II Designati on Professor Title Of The Project 1. Side-Channel Attack Tolerant Logic Styles And Its Application On SBOX Of Des System Using Spice. .V. Scalable Digital CMOS Comparator using a parallel prefix tree 6. Vinod Chavan Assoc. Prof. Performance Evaluation Of CSA Multiplier . 3. Design Of 2x1 Microstrip Antenna Array 4. Design Of Embedded Ethernet Based Web Server For Interface For Monitoring And Controlling 3.Srinivasa Rao I Mr. Simulation And Testing Of Helical Antennas. Design And Implementation Of High Performance 64 Bit Mac Unit For Dsp Applications. I. Performance Analysis Of Multi User Ds-CDMA System Over AWGN Channel In Mobile Environment VI Mr. Performance Of Symmetrical Pam For The Optimum Receiver In AWGN Channel 4. G. Bandwidth Improvement Technique For A Square Microstrip Antenna 5.S Rama Sastry Assoc. An Efficient FPGA Implementation Of The Advanced Encryption Standard Algorithm 1. 1. The Application Of Pic And Zigbee Technology Wireless Networks In Monitoring Mine Safety System 2. An ALU Optimized for area and power 1. 3. T. Braun Multiplier And Vedic Multiplier Using Microwind 2. Passenger Bus Alert System For Easy Navigation Of Blind 4. 2. Test Data Compression With Efficient Dictionary Selection Method 3. FPGA Implementation Of FIFO Controller 3. Prof. Orthogonal Frequency Divisional Multiplexing For Wireless Networks 2.T. Prof.A. Statistical Region Merging 4. Touch Screen And Zigbee Based Wireless Communication Assistant For Dumb/Illiterates In Airlines 3. FPGA Implementation Of Intelligent Car Parking System For Real Time Application 1. 1. Prof. FPGA Implementation Of Combinational Lock For Security System 2. FPGA Implementation Of Vending Machine Using State Machines 4. Prof. Asst. Error Detection In Majority Logic Decoding Of Euclidean Geometry Low Density Parity Check (Eg-Ldpc) Codes .N. Automatic Accident Detection And Ambulance Rescue With Intelligent Traffic Light System 1. Performance Analysis Of Manet Routing Protocols IX X Mr. Mr. Implementing Agricultural Field Management System Using GSM 4. Remote Control For Rural Irrigation 3. Asst. Prof.Saritha 6 Asst. Reduction Of Leakage Current And Power In Full Subtract or Using Mtcmos Technique 2. FPGA Implementation Of Alamouti Mimo Selection For Receiver-Antenna Selection Combining 3. Shravan Kumar Reddy M Sr. Prof. SVD Based Image Compression 5. Implementation Of BIST For Testing Combinational Circuit Using FPGA XII Mr.Pradee p Kumar Goud XI V Ms. Home Automation System Design Using Verilog Hdl. Implementation Of Touch Screen Based Home Appliances Control System Using Arm7 Lpc2148 And Zigbee 2. Human Health Monitoring Using Wireless Sensors Network 1. Asst. 3. Satish Assoc. 1. K. 2.5. Pramod Kumar Asst. Design Of Optimized Cic Decimator And Interpolator In FPGA 4. Design And Application Of Mobile Embedded System For Home Care Application 1. Sravan Kumar R. Remote Guidance For The Blind — A Proposed Tele Assistance System 2. Pulse Shaping Filters With Isi Free Properties 3. Asst.Sai Prasad Goud XIII Mr. C. Prof. Design Of Low Power And High Speed Configurable Booth Multiplier 1. Image Segmentation Techniques XI Mr. Vlsi Implementation Of Sha-2 Algorithm VIII Mr. Anti Theft Controlling System Using Embedded System 5. Antenna theory and design . www. Matlab 7.E. The project is about the theoretical calculations for directivity and performance along with array factor calculations in case of a two-horn antenna system . Books Antenna Handbook – Johnson 2.com Any other information 7 . Antennas and propagation magazine Websites 1. IEEE transactions on Antennas and propagation 2.orbanmicrowave. horn antennas. VSWR meter.php 2. Hardware/Equip. The gain of the antenna depends on the aperture area and flare angle.SRINIVASA RAO (Not to Department E. Windows 7 Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentati on 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books 1. Requirements Software Requirements Klystron microwave bench setup. Project Title ARRAY OF TWO HORN ANTENNAS FOR MORE DIRECTIVITYHARDWARE IMPLEMENTATION AND TESTING Description Horn Antenna is widely used in most of the microwave communication systems both at transmitter and receiver end.antenna-theory.V.Aurora’s Engineering College.Belanis Journals 1. www. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name K.C.1. many horns can be arranged as a linear array so that more directivity can be achieved. IEEE transactions on digital communications 3.com/antennas/patches/antenna. Instead of doing with a single horn. The Project is about the design and simulation and modeling of it using HFSS software.E.antenna-theory. An tenna theory and design . Performance evaluation also will be made in regard to the directional characteristics of the antenna .Aurora’s Engineering College. Windows 7 Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books 1. www.V.C. Antennas and propagation magazine Websites 1.SRINIVASA RAO Department E. HFSS. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name K. IEEE transactions on Antennas and propagation 2.orbanmicrowave.com Any other information 8 . The advantage of HFSS software is that the designer can directly model the structure and can investigate its performance. Books Antenna Handbook – Johnson 2. Project Title Description Hardware/Equip.com/antennas/patches/antenna. IEEE transactions on digital communications 3.Belanis Journals 1. The simplest of all microstrip antennas is the rectangular patch which can easily be fabricated on a substrate. Requirements Software Requirements (Not to SIMULATION OF RECTANGULAR MICROSTRIP ANTENNA USING HFSS SOFTWARE – PERFORMANCE EVALUATION In the present day research work connected with the design and simulation of microstrip antennas HFSS software is widely used worldwide.php 2. www. antenna-theory. This is used at VHF and UHF.1 Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings 1.orbanmicrowave. Requirements Software Requirements Helical antenna can be used in axial mode of operation for high directivity.www. Books Antenna Handbook – Johnson 2 . Project Title DESING . The project involves in the design of helical antenna in VHF range and is tested for its performance. IEEE transactions on digital communications 3.E.V.Aurora’s Engineering College.com/antennas/patches/antenna.Reich Journals 1. Antenna theory and design – Belanis 3 Microwave engineering . Matlab 7. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name K. Antennas and propagation magazine Websites 1. IEEE transactions on Antennas and propagation 2.C.SRINIVASA RAO (Not to Department E. SIMULATION AND TESTING OF HELICAL ANTENNAS Description Hardware/Equip.php Purpose: For learning basic concepts on Microstrip Antenna 2.com Any other information 9 .www. As it is cheaper and easier to construct and de4sign it can be used as an alternative to parabolic antenna. IEEE transactions on Microwave engineering Websites 1. Project Title DESIGN OF WAVEGUIDE WINDOWS FOR VARIABLE REACTANCES – IMPLEMENTATION AND TESTING Description Microwave windows are used for getting required reactance and are used in microwave repeaters as equalizers. Windows are simple to design for any required reactance.antenna-theory. Though irises can be used they are not precise and are very unstable in their values.Reich Journals 1. Microwave engineering .SRINIVASA RAO Department E. These are used during the signal transmission through a waveguide at a specific calculated position. Antenna theory and design .V. Antenna Handbook – Johnson 2.Aurora’s Engineering College. Hardware/Equip.orbanmicrowave. Requirements Software Requirements Windows 7 Matlab 7. The project involves the designing of rectangular windows and the calculation of reactance for various dimensions.E.Belanis 3.com/antennas/patches/antenna.1 Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books : 1.php Purpose: For learning basic concepts on Microstrip Antenna 2.www.www.C. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) (Not to Faculty Name K.com Any other information 10 . The strength of an encryption algorithm depends on the difficulty of cracking the original message.International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958. Leonordo Spectrum Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books 1. Cryptography and Network Security.Aurora’s Engineering College. August 2012 2. Issue-6. Requirements Software Requirements (Not to exceed one page) A Modified Approach for Symmetric Key Cryptography Based on Blowfish Algorithm The principal goal of designing any encryption algorithm is to hide the original message and send the non readable text message to the receiver so that secret message communication can take place over the web. Cryptography and Network Security . BLOWFISH has been developed to provide greater security affects one over the other. 2010 Journals 1. 5 Th Edtn. 2011 2. Volume-2. New Delhi. The blowfish algorithm is safe against unauthorized attack and runs faster than the popular existing algorithms. With this new approach we are implementing a technique to enhance the security level of blowfish algorithm and to further reduce the time for encryption and decryption. 1 st Edtn.ijeat. Bernard menezes. A number of symmetric key encryption algorithms like DES. CPLD/FPGA Board Xilinx ISE/Model Sim .mecs-press. Cengage Learning India . Kumara Swamy Department ECE Project Title Description Hardware/Equi p. Network Security and Cryptography.org.Volume-1. www. TRIPLE DES. August 2013 Websites www. Behrouz A. AES. Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name V. International Journal of Engineering and Research & Technology (IJERT) ISSN: 2278-0181. Issue 8. PC. Although the existing algorithms have their own merits and demerits but this project presents a new approach for data encryption based on Blowfish algorithm. 2010 3. William stallings. TMH.2nd Edition. Prentice Hall.org Any other information 11 .Forouzan. 12 . 5 Th Edtn. This gives low complexity architecture and easily achieves low latency as well as high throughput. Requirements Software Requirements A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this project. Leonordo Spectrum Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentati on Result Analysis Suggested Readings Books 1. 67~74 ISSN: 2089-4864 Websites : ieeexplore. July 2012. Simulation results. The design uses an iterative looping approach with block and key size of 128 bits. 2010 3. TMH. William stallings. Network Security and Cryptography. Cengage Learning India .2nd Edition. PC.Aurora’s Engineering College.com www. 2011 2.net Any other information 13 .ieee. Kumara Swamy Department ECE Project Title An efficient FPGA implementation of the Advanced Encryption Standard algorithm Description Hardware/Equip. Cryptography and Network Security . 1 st Edtn.researchgate. This implementation is compared with other works to show the efficiency. 2010 Journals 2.Forouzan. Behrouz A. CPLD/FPGA Board Xilinx ISE/Model Sim . Bhongir PROJECT DESCRIPTION DOCUMENT page) (Not to exceed one Faculty Name V. New Delhi. lookup table implementation of S-box.org iaesjournal. No. International Journal of Reconfigurable and Embedded Systems (IJRES)Vol. performance results are presented and compared with previous reported designs. Prentice Hall. Bernard menezes. 2. Cryptography and Network Security. 1. pp. Dr. Balwinder Singh. the number of times that it is added is the multiplier. Following multipliers are designed using DSCH2 and Microwind VLSI CAD tools and performance is evaluated and results are compared. Each step of addition generates a partial product. November 2009. August 2011. The first part is dedicated to the generation of partial products. IETE Journal of Research.Talari Jayachandra Prasad and Dr. of Recent Trends in Engineering and Technology. 2. Al Mijalli.Harini. Raminder Preet Pal Singh. 2. IJCSI International Journal of Computer Science Issues.K. 3. No. Prabha S. and the result is the product. physical. S. There has been extensive work on low-power multipliers at technology. May 2011. When the operands are interpreted as integers. Proposed Vedic multiplier Project Title Description Hardware/Equi p. Multiplication can be considered as a series of repeated additions. Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder. No. May 2010. Dr.11 No. 1. D. Multipliers consumes large area.Gautam.Christober Asir Rajan. 2.Ramasamy. Bhongir PROJECT DESCRIPTION DOCUMENT (Not to exceed one page) Faculty Name T. Performance Evaluation of Squaring Operation using Vedic Mathematics. International Journal of Recent Trends in Engineering. A New Design for Array Multiplier with Trade off in Power and Area. and V. B. S. Jan-Feb 2011. the product is generally twice the length of operands in order to preserve the information content. long latency and more power. 6. An 8x8 Subthreshold Braun Array Multiplier in 32nm CMOS Technology for Wireless SensorNodes. 8.Aurora’s Engineering College.pp 39-41 4. Parveen Kumar.Issue 1. Nirlakalla Ravi.0 VLSI CAD tools Project Activity Recommended Duration Literature Survey Analysis and Design Implementation/Experimentation Result Analysis Documentation Overall 3 weeks 4 weeks 3 weeks 2 weeks 1 week 13 weeks Suggested Faculty 4 weeks 3 weeks 3 weeks 2 weeks 1 week 13 weeks Duration by Suggested Readings Books: Journals: 1. Therefore designing multipliers having low-power consumption. Vol.Patil. CSA multiplier. Thota Subba Rao. International J. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. IJCSNS International Journal of Computer Science and Network Security. 2. 5. Virtex-5 FPGA Based Braun’s Multipliers. 3. circuit and logic levels. It is possible to decompose multipliers into two parts. Braun array multiplier. In the past multiplication was generally implemented via a sequence of addition and shift operations. Dr. Kasliwal. Vol 2. VOL. The number to be added is the multiplicand. No.8. minimum area is an important part in low-power VLSI system design. Rais and Mohammed H. Requirements Software Requirements PC DSCH2 VLSI CAD tools and MICROWIND 3. Vol 57 . and the second one is to collects and add them. Issue 3. 14 . These low-level techniques are not unique to multiplier modules and they are generally applicable to other types of modules. P. Vol. Anchula Satish.Sirisha Department ECE Performance Evaluation of CSA Multiplier . 3.Savari Rani. C. Braun Multiplier and Vedic Multiplier using MICROWIND Multiplication is a fundamental operation in most signal processing algorithms. Muhammad H. Diwakar. C. and M. high performance.6. 7. To appear in IEEE Trans. K. 2008 . A. Design of a low-power. Afzali-Kusha. M. IEEE Electr. (2008). Pedram . Websites: Any other information 15 . Senthilpari. Ajay Kumar Singh. A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture. Mottaghi-Dastjerdi. on VLSI Systems. 8*8 bit multiplier using a Shannon-based adder cell. 2005. Then a comprehensive comparison of the power. 3. Mathieu.Aurora’s Engineering College. M. LNCS. F. Edinburgh. Project Activity Recommended Duration Literature Survey 3 weeks Suggested Faculty 4 weeks Analysis and Design 4 weeks 3 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentati on Result Analysis Duration by Suggested Readings Books: Journals: 1. pp 383-397. I. Pacalet. Hassoune. pp 187-200.Masking at the Gate Level in The Presence ofGlitches. This also deal with the Spice simulation and layout design of non-standard logic styles. PC SPICE Design Evaluation tools. Scotland. 2. Sept. vol 3659. pp 997-1006.-D. num 9.Low-swing current mode logic(LSCML): a new logic style for secure smart cards against power analysis attacksin Microelectronics Journal. September 2006 Websites: Any other information 16 . B.Sirisha Department ECE Project Title Side-Channel Attack Tolerant Logic Styles and its application on SBOX of DES system using SPICE.S. Edinburgh. vol 37. J. area. Y. Gammel. The contribution of this project is to explore the design trade-off between various MOS logic styles with the same metrics. in the proceedings of CHES 2005. Mac ́e. UK. Requirements Software Requirements The objective of the project is to implement SBOX of a DES cryptosystem with standard CMOS logic style and different side-channel attack tolerant (SCAT) logic styles.vol 3659. Legat. Elsevier.The Backend Duplication Method: A LeakageProof Place-and-Route Strategy for ASICs. Hoogvorst. D. especially the cost of applying SCAT logic styles to deep sub-micron cryptosystems. Guilley. Fischer. August 2005. in the proceedings of CHES 2005.W. Flandre. P. speed and SCAT of these implementations will be made. R. Lecture Notes in Computer Science. Description Hardware/Equip . Bhongir PROJECT DESCRIPTION DOCUMENT page) (Not to exceed one Faculty Name T. Aurora’s Engineering College. the proposed DETFF design is suitable for low power and small area applications. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF).TRIGGERED STATIC D.0 VLSI CAD tools Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 4 weeks Analysis and Design 4 weeks 3 weeks Implementation/Experimentation 17 . Bhongir PROJECT DESCRIPTION DOCUMENT (Not to exceed one page) Faculty Name T. Requirements PC Software Requirements DSCH2 VLSI CAD tools and MICROWIND 3. Description This project deals with the new architecture of low power dual-edge triggered Flip-Flop (DETFF).E Project Title IMPLEMENTATION OF A LOW POWER DUAL EDGE . Hardware/Equip.Sireesha Department E.FLIP FLOP USING MICROWIND. In this project conventional and proposed DETFF are to be implemented and compared at same simulation conditions.C. Technol.5. (6). Neil H. Frank Propen. 2002. "Low-power explicit-pulsed triggered flip-flop with robust 18 . [5] Dai.-W.. Proceedings of the 2002 International Symposium on . ISLPED '02. 1279–1284. Ji-Zhong Shen. vol. 2005 . Journals [1] Stojanovic.59. Cent.536... Oklobdzija. “CMOS VLSI Design” Third Edition. Aleksic. 2002. M. “Low power design guide” reference book. Oklobdzija.2429... South Univ." Circuits and Systems. Oklobdzija." Low Power Electronics and Design.E.. J." Circuits and Systems. 23-26 May 2005. "A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. V. "Conditional pre-charge techniques for powerefficient dual-edge clocking. no. Jizhong. vol. Yeo. ISCAS 2005. Nikola.. ISCAS 2002. Yanyun. W.. 2010. 2002..-S. "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. 17. vol.4. vol." Solid-State Circuits.3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books : 1. no.2432 Vol.. V. 2. K. 3.V-105. 2005. no.V-108 vol. and Shen. pp. IEEE International Symposium on . V. no. Boston: Pearson. pp. Goh...34. M. “Structure and design method for pulse-triggered flip– flops at switch level”.G. IEEE International Symposium on . V. [3] Nedovic.David Harris.5.. 2002.G.L.. Apr 1999. M. Aleksic. pp.56. IEEE Journal of .. [2] Nedovic.G. Nikola. pp. pp. [6] Xue-Xiang Wu.. "Comparative analysis of double-edge versus single edge triggered clocked storage elements.548. [4] Phyu. Arithmetic Logic Unit (ALU) is the prime performing unit in any computing device and it has to be made fault tolerant.output.Fault Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the outputs. In this project we aim to design one such fault tolerant reversible ALU that is constructed using parity preserving reversible logic gates.C. no." Electronics Letters . November 22 2012. http://www.com/literature/cp/cp-pwropt.International Journal of VLSI design & Communication Systems (VLSICS) Vol.24.3. No. Description Reversible Logic is gaining significant consideration as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy . Requirements PC Software Requirements FPGA ADV .ModelSim Simulator & Leonardo Spectrum Synthesis tools. Significant contributions have been made in the literature towards the design of fault tolerant reversible logic gate structures and arithmetic units. there are not many efforts directed towards the design of fault tolerant reversible ALUs.altera. June 2013 Websites: 1.4.48. 19 . vol.E Project Title DESIGN AND IMPLEMENTATION OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC LOGIC UNIT USING VHDL. however. The designed ALU can generate up to seven Arithmetic operations and four logical operations.1525.Sireesha Department E. pp.1523.pdf Any other information Aurora’s Engineering College. Bhongir PROJECT DESCRIPTION DOCUMENT (Not to exceed one page) Faculty Name T. Hardware/Equip. 2. 20 . Brodersen “Minimizing Power Consumption in CMOS Circuits” Department of EECS. IBM Journal of R&D. Frank Propen. November 1973.. “CMOS VLSI Design” Third Edition. Neil H. 3.David Harris. “Logical reversibility of Computation”. IBM J. Research and Development.”Irreversibility and Heat Generation in the Computational Process”.E. “Low power design guide” reference book. Boston: Pearson.H.525532. Bennett. Landauer.University of California at Berkeley. Chandrakasan and Robert W.Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 4 weeks Analysis and Design 4 weeks 3 weeks Implementation/Experimentation 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books: 1.1961 [2] C. pp. Journals [1] R. 2005 . Anantha P. Vol. Saiful Islam et. Toffoli.pdf Any other information 21 . Manoj Kumar “Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate” VLSICS Vol.11.org/wiki/Power_optimization_(EDA) 2. 5(5). http://www.219-253.com/literature/cp/cp-pwropt. June 2012.R. “ A novel fault tolerant reversible gate for nanotechnology based systems”. No. Int’l J. “Design of Reversible Multipliers for linear filtering Applications in DSP” International Journal of VLSI Design and Communication systems. Reversible logic and quantum computers.[3] A. Fredkin and T.altera. Sci. Dec-12 [10] B. http://en. Appl. Asimolar Conf. A 32 (1985) 3266–3276. Peres. Navi. October 2006 Websites: 1. “Fault tolerant reversible circuits”. pp 11-20. Optical News.3. [5] R Feynman “ Quantum Mechanical Computers”. J..al” Synthesis of fault tolerant Reversible logic”IEEE 2009 [9] Rakshith Saligram and Rakshith T. Phys. Signal systems and computers”. Rev. 1982. [4] E. and K.”Conservative Logic”. Gayatri G. Theoretical Physics Vol 21.wikipedia.2008 [8] Md. Am. Parhami. [7] Haghparast. 1985 [6] Krishna Murthy. pp. M.3. “Gate Diffusion input (GDI): A power efficient method for digital combinatorial circuits”. NO. . 3rd Edition Journals [1] Radu Zlatanovici.6% less power as compare to Carry Propagate Adder using CMOS technique. IEEE JOURNAL OF SOLIDSTATE CIRCUITS. Comparative performance result shows that Carry Propagate Adder using GDI technique dissipated 55. IEEE Transaction on very large scale integration (VLSI) systems vol. 2008 22 . 2.H. 5 October 2002. Requirements Software Requirements This Project deals with performance of proposed Carry Propagate Adder based on GDI (Gate Diffusion Input)technique. 44. Pearson Education Publication. There are total three inputs (N. GDI also has an advantage of minimum propagation delay.18m technology. Sean Kao. Digital System Design. Circuit designed using CADENCE EDA tool and simulated using SPECTRE VIRTUOSO tool at 0.GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. We designed Carry Propagate Adder using GDI technique and compared its performance with CMOS technique in terms of area.Weste. inputs are applied at source/drain of nMOS and pMOS as well as gate input. “CMOS VLSI design.Sireesha (Not to Department E.E. [3] Arkadiy Morgenshtein.10.Aurora’s Engineering College. “Gate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process” 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel [4] N.C. Sixth Impression. and G) with one output. VOL. In GDI cell.wagner. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name T. minimum area required and less complexity for designing any digital circuit. no. delay and power dissipation. “Energy–Delay Optimization of 64Bit CarryLookahead Adders With a 240 ps 90 nm CMOS Design Example”. FEBRUARY 2009 [2] Arkadiy morgenshtein. Idan Shwartz and Alexander Fish. P. Alexander fish and Israel a . and Borivoje Nikolic. PC DSCH2 VLSI CAD tools and MICROWIND 3.E Project Title Design and Implementation of Power efficient carry propagate adder using microwind Description Hardware/Equip.0 VLSI CAD tools Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 4 weeks Analysis and Design 4 weeks 3 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentati on Result Analysis Suggested Readings Books : Morris Mano. David Harris Ayan Banerjee. 83. “Low. pp. Dec. [10] J. and K. P. “Pass-transistor logic design. 498–523. SolidState Circuits. [7] W. Websites: Any other information 23 . Friedman. W. Burns. A.” Proc. Electron.[5] A. S. vol. [8] K. pp. Circuits Signal Process. 14. Chandrakasan and R. Adler and E. pp.. [6] A.” Analog Integrat. and Y. Yano. Y. Solid-State Circuits. IEEE. Brodersen. Chandrakasan.. pp. 1997. 1995. 25. 473–484. “Delay and power expressions for a CMOS inverter driving a resistive capacitive load. P. 27.” IEEE J. vol. “Minimizing power consumption in digital CMOS circuits. vol. 739–749. Rikino. 1992. 31. pp. Apr. 70. 29–39.W. 1964.” RCA Rev. K. vol.” IEEE J. Apr. Sasaki. “Top-down pass-transistor logic design. “Switching response of complementary symmetry MOS transistor logic circuits. P. [9] V. R. K. J. Brodersen. Seki. Jayasumana. G.power CMOS digital design.” Int.. Sheng. vol. pp. Malaiya. Al-Assadi. 792–803. 627–661. June 1996. vol. and R. 1991. MAC unit is used for high performance digital signal processing systems. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder.Aurora’s Engineering College. Requirements Software Requirements FPGA/CPLD Trainer Kit Xilinx tools Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 03 Analysis and Design 4 weeks 04 3 weeks 03 2 weeks 02 Documentation 1 week 01 Overall 13 weeks 13 Implementation/Experimentati on Result Analysis Suggested Readings Books: Dsp processors and its Architecture by avtar singh Journals Websites: Any other information 24 . A design of high performance 64 bit Multiplier-andAccumulator (MAC) is proposed. Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name B. MAC unit is an inevitable component in many digital signal processing (DSP) applications involving multiplications and accumulations.C.Gouri Sivanandhini Department E.E Project Title (Not to exceed one Design and implementation of High Performance 64 bit MAC Unit for DSP Applications. The speed of the Description multiplication and addition arithmetic determines the execution speed and performance of the entire calculation . Hardware/Equip. its hardware occupies more area.C.E Project Title (Not to exceed one A High performance Binary to BCD Converter for Decimal Multiplication Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support or decimal arithmetic.Gouri Sivanandhini Department E. Requirements Software Requirements FPGA/CPLD Trainer Kit Xilinx tools Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 03 Analysis and Design 4 weeks 04 3 weeks 03 2 weeks 02 Documentation 1 week 01 Overall 13 weeks 13 Implementation/Experimentati on Result Analysis Suggested Readings Books Dsp processors and its Architecture by avtar singh journal Websites: Any other information 25 . A novel high speed low power architecture for Description fixed bit binary to BCD conversion is proposed. Hardware/Equip. Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name B. Binary to BCD conversion forms the basic building block of decimal digit multipliers.Aurora’s Engineering College. They are typically implemented using iterative approaches or lookup table based reduction schemes. Decimal arithmetic operations are generally slow and complex. by V.Gouri Sivanandhini Department E.2011 Journals: Saleh abdel hafeez.ijser. Requirements Software Requirements PC MICROWIND Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 03 Analysis and Design 4 weeks 04 Implementation/Experimentati on 3 weeks 03 Result Analysis 2 weeks 02 Documentation 1 week 01 Overall 13 weeks 13 Suggested Readings Books: “Fundamentals of CMOS VLSI Design”.E (Not to Scalable Digital CMOS Comparator using a parallel prefix tree Project Title Comparators are key design elements for a wide range of applications in scientific computation and image/signal processing.G Kiran kumar.C. A comparator design featuring wide range and high speed operation Description using conventional digital CMOS cells is proposed.”scalable digital CMOS Comparator using a parallel prefix tree”.org www.net Any other information 26 .Aurora’s Engineering College.Nagesh . Websites: www. This method reduces dynamic power dissipation by eliminating unnecessary transitions.R. proceeding bitwise towards the LSB only when compared bits are equal. IEEE Transaction on VLSI System. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name B.H. pearson publications. Hardware/Equip.researchgate. A Gordon ross and Behrooz parhami. Comparator exploits a novel scalable parallel prefix structure that leverages the comparison outcome of the MSB. IEEE Transaction 2014 ACCT. Websites: www. Hardware/Equip. GDI cells are used in design of multiplexer and full adders which are then associated to realize ALU.org www.Nagesh .R.C.Gouri Sivanandhini Department E. by V. Requirements Software Requirements PC MICROWIND Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 03 Analysis and Design 4 weeks 04 Implementation/Experimentati on 3 weeks 03 Result Analysis 2 weeks 02 Documentation 1 week 01 Overall 13 weeks 13 Suggested Readings Books: “Fundamentals of CMOS VLSI Design”.2011 Journals: Vivechana Dubey and Ravi mohan sai ram.net Any other information 27 . Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name B. the ALU are to be designed with compact size less power and propagation delay.”An ALU optimized for area and power”.E (Not to An ALU Optimized for area and power Project Title In the era of growing technology and scaling of devices up to nanometer. Design of 4 bit ALU by including the concept of gate Description diffusion input(GDI) technique is proposed.G Kiran kumar.H.ijettcs.Aurora’s Engineering College.researchgate. pearson publications. 45 GHz (Wireless LAN frequency) using transmission line model. Antennas and Wave propagation Library.Constaine A. 2. Ray : Broad band Microstrip Antennas” Artech House. To increase the rate of data transfer.3.. VSWR can be obtained by using High frequency simulation software version 12. Various schemes have been suggested for the design of antenna to get large bandwidth.V. Second/ Third Edition 2. cost. satellite and missile applications. space craft. Shahidulla. June 2012. Kishore Bhowmik. low profile antennas may be required. Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name I. Md.Rama Sastry Department Project Title Description (Not to exceed one ECE Design of Microstrip feed Rectangular Microstrip antenna APPLICATION: Wireless LAN application In high performance aircraft. No. International Journal of Electrical and Computer Engineering (IJECE). Md. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO ` 2. return loss. Kishore Bhowmik. “Antenna Theory analysis and design”. Md.Girish Kumar and K. Md.MAT LAB (For design calculations) Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 20hrs Analysis and Design 4 weeks 25hrs Implementation/Experimentation 3 weeks 24hr Result Analysis 2 weeks 16hrs Documentation 1 week 10hrs Overall 13 weeks 104hrs Suggested Readings Books: 1.1. weight. pp. The main aim of this project to design a rectangular microstrip antenna at a frequency of 2.The design calculations can be done by using MATLAB software tool and the various parameters of rectangular MSA Viz input impedance.. Journals“Rectangular Microstrip Patch Antenna at 2GHZ on Different Dielectric Constant for Pervasive Wireless Communication”. Shihabul Islam. Hardware/Equi p. such as mobile radio and wireless communications that have similar specifications. It is fed with 50 ohms microstrip line.ease of installation and aerodynamic profiles are constraints. The simplest form of microstrip antenna consists of radiator on one side of the substrate material and ground on the other side. Maruf Ahamed.Aurora’s Engineering College. where size. increased antenna bandwidth is required. There are numerous advantages of microstrip antennas in wireless communication system because of its desirable characteristic. Balanis. Presently there are many other government and commercial applications.2. 417 ~ 424 ISSN: 2088-8708.2003 Edition 1. performance ..P. Maruf Ahamed. “Analysis And Design of Rectangular Microstrip Patch Antenna On Different Resonant Frequencies For Pervasive Wireless Communication” Md.S.Many other broadband techniques are used in Microstrip antennas include thick substrates. To meet these requirements microstrip antennas can be used. employing parasitic elements either in coplanar or stacked configurations with other approaches such as cutting slots inside the regular MSA geometries or changing the shapes of MSA to a diamond shape.Vol. gain. Abdulla Al 28 . Abdur Rahman . Requirements Software Requirements 1. 3...ieee.lib. Design of a compact Microstrip Patch Antenna for use in Wireless ..com/antennas/patches/antenna.fsu. Hardware can be made. 5.etd.php Purpose: To understand the basic concepts &Design of Microstrip. Chapter-4.pdf Microstrip patch antenna design and results. 6.p. Only Simulation Results to be executed. www./Chapter4.com/online/index. Any other information Testing is not possible. june 2012 issn 2277-8616.edu/theses/available/etd-04102004-143656/..p 48-50 Websites www.antenna-theory.. 29 .. Suman. issue 5.iaesjournal.org › . 4. › Signal Processing and Communication Purpose:To familiar in the design of rectangular Microstrip antenna.php/IJECE/article/view/341/pdf Purpose:to understand the design of rectangular Microstrip antenna ieeexplore.international journal of scientific & technology research volume 1. BW . Bhongir PROJECT DESCRIPTION DOCUMENT one page) Faculty I. To increase the rate of data transfer. January 2013. Antennas and Wave propagation Library.V. International Journal of Application or Innovation in Engineering & Management (IJAIEM) “Design. can be obtained by using High frequency simulation software version 12. In this project work. Ray : Broad band Microstrip Antennas” Artech House.. 2.Girish Kumar and K.Many other broadband techniques are used in Microstrip antennas include thick substrates. a Square microstrip antenna at a frequency 1. Simulation and Analysis of a Square Shaped S band Microstrip Antenna”. return loss. Second/ Third Edition 2. Balanis. VSWR.8GHz APPLICATION: Wireless LAN application Description: There are numerous advantages of microstrip antennas in wireless communication system because of its desirable characteristic. Issue 1. But there are various disadvantages of microstrip antenna such as narrow bandwidth typically 1-5% and low gain which is the major limiting factor for the application of these antennas.Rama Sastry Name Department Project Title Description Hardware/E quip.Aurora’s Engineering College. Requiremen ts Software Requiremen ts (Not to exceed ECE A Design of a probe feed Square patch antenna at a frequency of 1..S. employing parasitic elements either in coplanar or stacked configurations with other approaches such as cutting slots inside the regular MSA geometries or changing the shapes of MSA to a diamond shape.Constaine A. “Antenna Theory analysis and design”. Various schemes have been suggested for the design of antenna to get large bandwidth. increased antenna bandwidth is required..MAT LAB (For design calculations) Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 20hrs Analysis and Design 4 weeks 25hrs Implementation/Experimentation 3 weeks 24hr Result Analysis 2 weeks 16hrs Documentation 1 week 10hrs Overall 13 weeks 104hrs Suggested Readings Books: 1. Web Site: www. gain. Journals: 1. .P. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO 2.ijaiem.International Journal of Innovative Technology and Exploring Engineering (IJITEE) 30 . Although these antennas have good impedance bandwidths. but have bidirectional radiation pattern which further reduces the gain .1 1..2003 Edition.8GHz will be designed using transmission line model and its various parameters Viz input impedance.org Volume 2. Issue 8. 3.com“Design. Issue-1. Hardware can be made. June 2012 “Design of a Square Microstrip Patch Antenna” Shruti Vashist. Volume-1. Pramod Singal. Volume 3.ijarcsse. Simulation and Analysis of a Square Shaped S-band” Websites: 1.com/antennas/patches/antenna.com 3.pdf Any other information Testing is not possible..www. Only Simulation Results to be executed 31 .. August 2013 ISSN: 2277 128X .Soni.www.K.www./V3I8-0177.ijarcsse.phpPurpose: 2.ISSN: 2278-3075. International Journal of Advanced Research in Computer Science and Software Engineering . M.www.com/docs/papers/Volume_3/8.orbanmicrowave.antenna-theory. Antennas and Wave propagation Library.V.2003 Edition Journals:1 “Bandwidth Enhancement for Microstrip Patch Antenna Using Stacked Patch and Slot” IEEE 2“Bandwidth Enhancement of Probe Fed Microstrip Patch Antenna” International Journal of Electronics Communication and Computer Technology (IJECCT) Volume 3 Issue 1 (January 2013) ISSN:2249-7838 IJECCT | www. to enhance the BW.The main objective of this project is to design a basic a Rectangular/Square microstrip antenna at a frequency of 2.org 368 Websites: 1 www. gain.Aurora’s Engineering College.Girish Kumar and K.ijecct.on microstrip antenna.1. Project Title Description Hardware/Equi p. diagonal slot. ring slot antennas. H-slot.0(For design calculations Suggested Duration by Project Activity Recommended Duration Faculty 20hrs Literature Survey 3 weeks 25hrs Analysis and Design 4 weeks Implementation/Experimentation 3 weeks 24hr Result Analysis 2 weeks 16hrs Documentation 1 week 10hrs Overall 13 weeks 104hrs Suggested Readings Books: 1. Requirements Software Requirements 1.MAT LAB 7. Issue 4 (Sep-Oct. PP 15-18 Any other information Testing is not possible.Rama Sastry Department ECE Bandwidth improvement technique for a square microstrip antenna APPLICATION: Wireless LAN application Description:. etc) by different feeding methods in single layer and multilayer configurations.P. making slots on patch (V-slot.www.S. The slot may be either V or U shape. 2012). square. ISBN: 2278-8735.iosrjournals. Various techniques have been implemented in the past to overcome these shortcomings including the use of modifying the shape of the patch.Constaine A.ijecct. Balanis. The design calculations can be done by using MATLAB software tool and the various parameters of rectangular MSA Viz input impedance.org 368 2. Bhongir PROJECT DESCRIPTION DOCUMENT (Not to exceed one page) Faculty Name I. VSWR can be obtained by using High frequency simulation software version 12. Second/ Third Edition 2. Only Simulation Results to be executed 32 . return loss. Hardware can be made.45 GHz (Wireless LAN frequency) using transmission line model.org 15 | Page ISSN: 2278-2834. In this work we introduce one of the BW enhancement techniques.org www. Ray : Broad band Microstrip Antennas” Artech House. Volume .. A reasonable thickness should be considered in the selection of substrate and the bandwidth would be enhanced using additional techniques. A slot is introduced on the radiator. U-slot. “Antenna Theory analysis and design”.iosrjournals. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO 2. Some of them are parabolic reflectors.Patch antennas play a very significant role in today's world of wireless communication systems. The elements can be fed by a single line or by multiple lines in a feed network arrangement. reflected loss. We can say antennas are the backbone and almost everything in the wireless communication without which the word could have not reached at this age of technology .Aurora’s Engineering College. increase the directivity. Microstrip antennas are very versatile and are used.0(For design calculations) Suggested Duration by Recommended Duration Faculty 20hrs 3 weeks Analysis and Design Implementation/Experimentatio n Result Analysis Documentation 33 (Not to 4 weeks 3 weeks 25hrs 24hr 2 weeks 16hrs 1 week 10hrs .e.. These patch antennas are used as simple and for the widest and most demanding applications. A microstrip patch antenna is very simple in the construction using a conventional microstrip fabrication technique. dual frequency operation. In this project work a two elementa antenna array has been proposed to develop the performance of this antenna. Requirements Software Requirements Project Activity Literature Survey ECE Design of 2x1 microstrip antenna array. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO 2. In addition. circular polarizations. efficiency and antenna gain. can be obtained by using electromagnetic simulator HFSS simulation results. Dual characteristics. they are used to scan the beam of an antenna system.S. APPLICATION: Wireless communication systems Description: Antennas play a very important role in the field of wireless communications.V. 1. Each type of antenna is good in its own properties and usage.. Low dielectric constant substrates are generally preferred for maximum radiation. etc.A microstrip antenna consists of conducting patch on a ground plane separated by dielectric substrate. feed line flexibility and beam scanning can be easily obtained from these patch antennas. broad band width. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name I.MAT LAB 7. slot antennas and folded dipole antennas. i. A single feed is provived for both elements. among other things. frequency agility. The patch can take any shape but rectangular and circular configurations are the most commonly used configurations. radiation patterns. The performance characteristics of the antenna array.Rama Sastry Department Project Title Description Hardware/Equip. patch antennas. and perform various other functions which would be difficult with any one single element. to synthesize a required pattern that cannot be achieved with a single element. Overall 13 weeks 104hrs Suggested Readings Books: 1.Constaine A. Balanis, “Antenna Theory analysis and design”, Second/ Third Edition 2..Girish Kumar and K.P. Ray : Broad band Microstrip Antennas” Artech House, Antennas and Wave propagation Library,2003 Edition 3.David.M.Pozar, “ Microwave Engineering”, Second Edition, 1993,John Wiley&Sons,INC Journals: 1.International Journal of Electronic Engineering Research , © Research India Publications Volume 1 Number 1 (2009) pp. 71– 77,http://www.ripublication.com/ijeer.htm 2. Modeling and simulation of Microstrip patch array for smart antennas by K Meena Cited by 8 - Related articles www.cscjournals.org/csc/manuscript/Journals/IJE/volume3/.../IJE-131.pd... Websites: 1. www.idc-online.com/.../Design%20of%20an%208X1%20Square%20Mi... 2.Design of an 8X1 Square Microstrip Patch. Antenna Array. V.R. Anitha. 1 and S. Narayana Reddy. Dept of EEE, SV University, Tirupati. 2. Any other information Testing is not possible. Hardware can be made. Only Simulation Results to be executed 34 Aurora’s Engineering College, Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name I.V.S.Rama Sastry Department Project Title Description (Not to exceed one ECE Design of high frequency Low pass/High pass filter using microstrip lines. APPLICATION: Wireless Communication systems Description: The microwave filters are based on distributed parameters rather than lumped inductors and capacitors. For low-power applications, stripline and microstrip filters are extensively used because of their low cost and repeatability. For high-power requirements, waveguide structures are utilized. Microstrip line is bimetallic which contain two metallic surface separated with a small distance, having a dielectric material between them.. The filter is required in all RF-communication techniques. Low Pass Filters play an important role in wireless power transmission systems. Transmitted and received signals have to be filtered at a certain frequency with a specific bandwidth. In this paper the design of filter is done in the ISM (Industrial, Scientific and Medical) band whose frequency lies between 1.55GHz- 3.99GHz. After getting the specifications required, we realized the filter structure with the help of HFSS software, and the filter characteristics and its various parameters Viz,insertion loss,S-paramers can be obtained from software simulation results. Hardware/Equi p. Requirements Software Requirements 1. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO 2.MAT LAB 7.0(For design calculations) Suggested Duration by Project Activity Recommended Duration Faculty 20hrs Literature Survey 3 weeks Analysis and Design 4 weeks 25hrs Implementation/Experimentation 3 weeks 24hr Result Analysis 2 weeks 16hrs Documentation 1 week 10hrs Overall 13 weeks 104hrs Suggested Readings Books: 1.David.M.Pozar, “ Microwave Engineering”, Second Edition, 1993,John Wiley&Sons,INC 2. Reinhold Ludwig, Gene Bogdanow “ RF circuits Design Theory and Applications “ , 2 nd Edition,Pearson publication Journals: 1.“Design and Simulation of Magic Tee and Ring Hybrid Coupler using Ansoft HFSS” Parul Dawar Dept. of ECE, Guru Tegh Bahadur Institute of Technology, Rajouri Garden,New Delhi, India.pp No.199-203, IJCST Vol. 2, Issue 1, March 2011; I S S N : 2 2 2 9 - 4 3 3 3 ( P r i n t ) | ISSN:0976-8491 2.Broad-Band Design of Improved Hybrid-Ring 3-dB Directional Couplers”. Dong Il Kim; Naito, Y.; "Microwave Theory and Techniques,IEEE Transactions, 1982 , pp. 2040 - 2046”, Websites: www.gooogle.com for this topic Any other information Testing is not possible. Hardware can be made. Only Simulation Results to be executed 35 Aurora’s Engineering College, Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name G.M.GANESH Department ECE Project Title Description Hardware/Equip. Requirements Software Requirements Performance Analysis of Multi User DS-CDMA System Over AWGN Channel in Mobile Environment Multiple Access Communications allows more than one sender use the same channel for transmission with potential problem of collision when sent simultaneously. In CDMA, each user is provided with an individual and distinctive PN code. The CDMA System uses in today’s 3G and 4G Mobile Communications. This project will include Transmitter design module, AWGN channel and Receiver design module. This project implemented using MATLAB software and also verify with theoretical results. COMPUTER SYSTEM ,Lenovo company,2GB RAM,250GB HD MATLAB 2010 a. Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentati on 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books : 1) Wireless communications -2002 edition, PHI, RAPPAPORT. 2) Digital communications -4th edition, TMG,JOHN.G.PROAKIS 3) Digital Communications – 2nd edition, PHI, BERNALD SKLAR. Journals: 1) Overview of CDMA Evolution Toward Wideband CDMA,IEEE Communications,Vol.1,No.1,1998 1) 2) Performance Analysis of CDMA Based Wireless Communication Systems Using Simplified Improved Gaussian Approximation Method, IEE Transaction On Communications, 19 May 2004. 2) 3) Venkategowda, N.K.D.; Jagannatham, A.K., \WR based semi-blind channel estimation for frequency-selective MIMO MC-CDMA systems," 2012 IEEE Wireless Communications and Networking Conference (WCNC), pp.317-321, 1-4 April 2012. Websites : 1) www.mathworks.com 2) www.wikipedia.com Any other information 36 2007.mathworks.wikipedia.JOHN.PROAKIS 3) Digital Communications – 2nd edition.M.G. Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name G.GANESH Department ECE Project Title Description Hardware/Equip.com Any other information 37 . COMPUTER SYSTEM with Internet connection MATLAB 2010A. In digital communication system design. Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentati on Result Analysis Suggested Readings Books : 1) MATLAB Help Documents. 3) IEEE Transaction on Spread Spectrum Websites : 1) 2) www. PHI. In digital modulation schemes. Mobile Radio Personal Communication. TMG. the PSK system has less probability of error than any other digital modulation schemes like ASK. BERNALD SKLAR. Communications Toolbox.com www. 2) IEEE International. Journals: 1) IEEE Transaction on Communications.. Requirements Software Requirements Design and implementation of 8-PSK System in AWGN Channel using MATLAB As the digital communications industry continues to grow and evolve. This project implemented using MATLAB software and also verify with theoretical results. the main objective is to receive data as similar as the data sent from the transmitter. The proposed system consists of transmitter block.Aurora’s Engineering College.FSK and DPSK systems . 2) Digital communications -4th edition. AWGN channel and receiver block. the applications of modulation techniques continue to grow as well. wikipedia.K. 1-4 April 2012. 2) Anti-jamming message Driven Frequency Hopping –Part-I:System Design.Jan 2000. frequency and time.. FDMA System allows more than one sender use the allocated channel band for transmission with potential problem of collision when sent simultaneously. results in Frequency Division Multiple Access (FDMA).1-5. Websites : 1) www.11. PHI. COMPUTER SYSTEM .com Any other information 38 . 3) 3) Venkategowda.IEEE WirelessCommunication.No. each user is provided with an individual and distinctive carrier frequency.page 70-79. A.JOHN. Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentation 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books : 1) MATLAB Help Documents. Journals: 1) Spread Spectrum For Global Communications-II..317-321.issue 1. pp. AWGN channel and Receiver design module." 2012 IEEE Wireless Communications and Networking Conference (WCNC).GANESH Department ECE Project Title Description Hardware/Equip. In FDMA..12.Vol. This project implemented using MATLAB software and also verify with theoretical results.18.mathworks. IEEE Transaction On Communications .G. 2) Digital communications -4th edition. The FDMA System useful in analog and multi carrier mobile communication systems. Requirements Software Requirements Design and Implementation of FDMA System for Wireless Communications For radio systems there are two resources. Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name G.Januvary 2013.D.K.Page No. \WR based semi-blind channel estimation for frequency-selective MIMO MC-CDMA systems.Vol .Lenovo 2GB RAM. N.M.250GB HD. Jagannatham.com 2) www. BERNALD SKLAR.Aurora’s Engineering College. so that each pair of communicators is allocated part of the spectrum for all of the time. Division by frequency.PROAKIS 3) Digital Communications – 2nd edition. TMG. Communications Toolbox.2007. This project will include Transmitter design module. MATLAB 2010 a. Pages 139-142.2007. Requirements Software Requirements COMPUTER SYSTEM . 2) Ultra Wideband System Performance studies in AWGN Channel with Intentional Interference-Hamalainen Websites : 1) www. Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name G. 2) Digital communications -4th edition. TMG.. A bit error analysis for the binary symmetrical rectangular PAM communication system with the optimum receiver can be obtained by using the ratio of Eb/No as the SNR parameter.Aurora’s Engineering College.3.mathworks. Hardware/Equip . The binary rectangular PAM transmitter and simple filtered PAM receiver can be implemented in the presence of AWGN with the optimum receiver (matched filter). This project implemented using Simulink software.com Any other information 39 .Lenovo.2GB RAM.dennis-silage. MATLAB 2010a AND SIMULINK Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation /Experimentation Result Analysis Suggested Readings Books : 1) MATLAB Help Documents. Communications Toolbox.M.5-7 July 2010.PROAKIS 3) Digital Communication Systems Using MATLAB and Simulink – Dennis Silage Journals: 1) Performance improvement of PAM DS UWB signal in AWGN Channel based on EMD –Signal Processing Systems(ICSPS).G.com 2) www.250 GB HD.JOHN.Vol.GANESH Department ECE Project Title Performance of Symmetrical PAM for the Optimum Receiver in AWGN Channel Description Binary digital data can be represented as either a symmetrical polar or a asymmetrical unipolar PAM signal. Aurora’s Engineering College. Bhongir PROJECT DESCRIPTION DOCUMENT page) (Not to exceed one Faculty Name Mr.Sohraby PIC Microcontroller and Embedded Systems : Using assembly and C for PIC 18 . mine operators can locate an individual miner within ten feet. Vinod Chavan Department E.C. In addition of tracking the location of miners we also include sensors such as temperature & humidity to intimate the base station & miners when some atmosphere changes occur.org www. Even after a full-day of use. Muhammad Ali Mazidi.researchgate. K. Many mines use a radio system to track miners. Zigbee Module and Sensors MPLAB. 2008. Communication.E The Application Of PIC and Zigbee Technology Wireless Networks In Monitoring Mine Safety System Project Title The foremost critical task for coal mine is of keeping track of miners spread out across a large mining areas .net Any other information 40 . Description In this project to overcome the demerits of radio system we used wireless technology for tracking the miners.ieee. CCCM '08 Websites:www. Rolin McKinlay. 1st Edition Journals International Conference: Computing. Mine operators are now able to monitor the real-time locations of each miner to better pinpoint their locations in the event of an emergency. the base stations connected by a thin wire often are rendered useless. Requirements Software Requirements Pic Microcontroller. Each transceiver placed in the mine look after the location of miners.It becomes even difficult when mine tunnels collapse. Control. The transceivers communicate with base stations through zigbee module. RF Module. Hardware/Equi p. and Management. Danny Causey. For this purpose a small RF transmitter module is equipped to each person entering a mine.ieeexplore. Embedded C Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentation 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books Wireless sensor networks. but when a collapse occurs. 41 . The client or a person on the PC is also connected to same LAN or Internet. A web server in the device provides access to the user interface functions for the device through a device web page. Sensor module KEIL Compiler.Aurora’s Engineering College. The web-server circuit is connected to LAN or Internet. By typing the IP-address of LAN on the web browser. Here all the devices. ARM processor. which are to be controlled. The user can also control the devices interfaced to the web server by pressing a button provided in the web page. Charles E. e-book Journals :International Journal of Advanced Research in Computer and Communication Engineering 42 . Home automation.C. this page contains all the information about the status of the devices. Vinod Chavan Name Department Project Title Description Hardware/Eq uip. Relay unit . A web server can be embedded into any appliance and connected to the Internet so the appliance can be monitored and controlled from remote places through the browser in a desktop. controlled using either special front-end software or a standard internet browser client from anywhere around the world. Philips Programmer. The aim of the project is to control the devices or equipment’s from the remote place through a web page. Bhongir PROJECT DESCRIPTION DOCUMENT one page) Faculty Mr. which can be easily. Web access functionality is embedded in a device to enable low cost widely accessible and enhanced user interface functions for the device. Using this knowledge many applications are imaginable. Requirement s Software Requirement s (Not to exceed E. appliances. utility meters. the user gets a web page on screen. card readers. Spurgeon ARM Processor .E Design of Embedded Ethernet based web server for Interface for Monitoring and Controlling Computer communication systems and especially the Internet are playing an important role in the daily life. security systems. and building controls. are connected to the relays (acts as switches) on the web server circuit board. EMBEDDED C Literature Survey Recommended Duration 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Project Activity Implementation/Experimentati on Result Analysis Suggested Readings Books : Ethernet: the definitive guide. com Any other information 43 . 2 . May 2013 Websites: www.ijarcce. Issue 5.Vol. org www. but the main objective is not reached that it fails to join them with traffic. Vinod Chavan (Not to exceed one Department E. Voice Synthesizer. These bus numbers are converted into audio output using the voice synthesizer APR 9600. echolocations are all useful in navigating the visually challenged people to reach their destination.Sohraby ARM Processor . The blind gives the input about the place he has to reach using microphones and the voice recognition system recognizes it .E Project Title Passenger BUS Alert System for Easy Navigation of Blind Description Talking signs. So the bus stops at the particular station. The blind takes the right bus parked in front of him and when the destination is reached it is announced by means of the GPS-634R which is connected with the controller and voice synthesizer which produces the audio output.in Any other information 44 . Speech Recognition System. Embedded C Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books :Wireless sensor networks.The blind people in the bus station is provided with a ZigBee unit which is recognized by the ZigBee in the bus and the indication is made in the bus that the blind people is present in the station.ieee. This project is also aimed at helping the elder people for independent navigation Hardware/Equi p. K.niueee. Wireless sensor networks. Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name Mr. In this project we propose a bus system using wireless sensor networks (WSNs). e-book Journals :International Conference on Circuits. guide cane. The desired bus that the blind want to take is notified to him with the help of speech recognition system HM2007. The ZigBee transceiver in the bus sends the bus number to the transceiver with the blind and the bus number is announced to the blind through the headphones. GPS.C.The input is then analyzed by the microcontroller which generates the bus numbers corresponding to the location provided by the blind. Requirements Software Requirements Microcontroller. Power and Computing Technologies [ICCPCT2013] Websites: www. Zigbee.Aurora’s Engineering College. 45 . To monitor the patient details in periodic interval is on overhead using existing technologies. ARM processor. Vinod Chavan Department E. To overcome this we have changed recent wireless sensor technologies.E Project Title Description Hardware/Equip.C. In general.Aurora’s Engineering College. Relay unit . K.org Any other information 46 .Sohraby ARM Processor . This adds the advantages of mobility. Embedded C Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experiment ation Result Analysis Suggested Readings Books Wireless sensor networks.ijaiem. e-book Journals International Journal of Application or Innovation in Engineering & Management (IJAIEM) Websites: www. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name Mr. Sensor module KEIL Compiler. There is no need for a doctor to visit the patient periodically. Requirements Software Requirements (Not to HUMAN HEALTH MONITORING USING WIRELESS SENSORS NETWORK Wireless devices have invaded the medical area with a wide range of capability. different sensors are used to gather patient medical information without being injecting inside the body by this we are achieving remote monitoring and data gathering of patients. A regular and localized bit-level dependence graph (DG) is derived from the proposed algorithm and mapped into an array architecture. In this thesis dependence graph is drawn using algorithm and then this dependence graph is regularized to perform unique operation at different nodes and finally this regularized dependence graph is mapped into dedicated hardware which consists of array of program element and the required multiplication is performed by using 2(m+1) D Flip Flops . where the modular reduction is achieved by a serial-in parallel out shift-register. Vinod Chavan Department ECE Project Title Description Hardware/Equip. Modelsim Xilinx Edition (MXE) Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books Journals IEEE Publications.Aurora’s Engineering College. and to perform circuit level optimization to reduce the area and the time complexities of implementation . Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name Mr. Requirements Software Requirements (Not to exceed one Design Of An Efficient And Optimized Algorithm For SerialParallel Multiplication Using AOP Efficient and optimizing an algorithm for hardware-efficient AOP-based on serial-parallel multiplication.Finite field multiplication over GF(2m) based on irreducible all onepolynomials (AOP).2013 Websites Any other information 47 . where the modular reduction of degree is achieved by cyclic-left-shift without any logic operations.(m+1) AND gates and (m+1) XOR gates. PC Xilinx-ISE(VHDL). Vassiliadis S (2006) Improving SHA-2 hardware implementations.gov Any other information 48 . Third Edition.: Cryptographic Hardware and Embedded Systems-CHES 2006. Websites: http://en.Aurora’s Engineering College.org/wiki/SHA-2 www. Requirements Software Requirements The Secure Hash Algorithm is a family of cryptographic hash functions. Bhasker.Cryptography and network security: principles and practices-4th edition Pearson Education Inc. Kuzmanov G. Bhongir PROJECT DESCRIPTION DOCUMENT (Not to exceed one page) Faculty Name K.nsit. A VHDL Primer. It is essentially a 256 bit block cipher algorithm which encrypts the intermediate hash value using the message block as key. A family of two similar hash functions.E Project Title VLSI IMPLEMENTATION OF SHA-2 ALGORITHM Description Hardware/Equip. William Stallings . The SHA-256 compression function operates on a 512-bit message block and a 256-bit intermediate hash value. Modelsim simulator Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books 1. with different block sizes. They differ in the word size. pp 298– 310.wikipedia. Sousa L.SATISH Department E. J.Chaves R. Prentice Hall Publication. known as SHA-256 and SHA-512. SHA-256 uses 32bit words where SHA-512 uses 64-bit words. 2009 Journals 1. 2.C. Requirements Software Requirements In this project the performance of the TCP over different Mobile Ad-hoc Network Routing Protocols is evaluated by using the network simulator (NS2). Dynamic Source Routing protocol (DSR) and Destination Sequenced Distance Vector routing protocol (DSDV). DSR is source routing algorithm i. 2005. source appends the complete route for the packet to reach the destination in the packet’s header. Journals: G. 219–230. pp. Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books :Andrew. Websites www.Network simulator-NS-2. Pearson Education.K. S. “Analysis of TCP performance over mobile ad hoc networks. The routing protocols used in the simulations are Ad-hoc On Demand Distance Vector Routing protocol (AODV).” Proceedings of ACM Mobicom.org/ijcnis/ijcnis-v5-n9/IJCNIS-V5-N9-6.SATISH Department ECE (Not to exceed one Performance analysis of MANET routing protocols Project Title Description Hardware/Equip.Aurora’s Engineering College.pdf Any other information 49 .mecs-press. PC LINUX. Raj Jain. COMPUTER NETWORKS.edu/nsnam/ns/ www. 4th Edition. 1 Mahbub Hassan. The DSDV is a table driven algorithm. Performance metrics are throughput and window size. Tanenbaum.e.isi. Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name Mr. High performance TCP/IP Networking –PHI. AODV is an on demand routing protocol. Vaidya. Holland and N. cise.edu/~kbasu/tvlsi09.L. Electron. Abramovici. the solution is going for Compression. no. 4. 1990.ufl. test data volume increases to test the circuit.D. PC The Project implemented in Hardware Description Language (HDL) and Simulation & Synthesis is performed on Xilinx ISE . and N. if circuit density increases. Li.Aurora’s Engineering College. Ayan Banerjee . David Harris. pp.K. Syst.org/publications/test-data-compression-using-efficientbitmask-and-dictionary-selection-methods Any other information 50 . To detect these faults we have to go for ATE(Automatic Test Equipment) or BIST(Built in Self Test) methods. M. IEEE Press. Websites 1 www. and A.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2.pdf 2 http://www.” ACM Trans. Neil H. it requires larger memory sizes. Pearson. Compression schemes are classified into two general groups: dictionary and bit masking schemes. M. BASU AND MISHRA: Test data compression using efficient Bitmask and dictionary selection methods. “Digital System Testing and Testable Design”. Friedman.CMOS VLSI Design: A Circuits and Systems Perspective. 8.sciweavers.tionaries with selective entries and fixed-length indices. A. 470–490. Des. Instead to decrease size of memory. “Test data compression using dic.2009 Journals 1. Bhongir PROJECT DESCRIPTION DOCUMENT page) Faculty Name Mr. 652 pages 2. If memory size is high we get more faults. Requirements Software Requirements Project Activity Literature Survey Data Compression (Not to exceed one with Efficient Dictionary Selection Method In System on Chips(SoC).SATISH Department ECE Project Title Test Description Hardware/Equip. Autom. Thrid Edition. Weste.. vol.E. Suggested Duration by Recommended Duration Faculty 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books 1. Touba. New York.. Chakrabarty. K. Breuer. .2028 vol.C. no.2023.. pp.892 2.. A. Websites: Any other information 51 . which aim to measure the potential usefulness of the system and discover possible problems with user-operator communication or device design. An early prototype utilizing two laptop PCs and a wireless Internet connection is used in orientation and mobility trials. Vol. S. 1994. Y. 1: Process Measurement and Analysis Hardcover by Bela G. J.Aurora’s Engineering College. Baranski. Transmitter and Receiver. P. "Remote guidance for the blind — A proposed teleassistance system and navigation trials. Liptak (Editor)  Transducer and instrumentation by dvsmurthy Journals 1. Moranski. Borenstein. P... Bujacz. M.. vol.Pramod Kumar (Not to Department E. pp. Requirements Sensor..E Project Title Remote guidance for the blind — A proposed tele assistance system Description The concept is based on the idea that a blind pedestrian can be aided by spoken instructions from an operator who receives a video stream from a camera carried by the visually impaired user. Proceedings.3.888." Robotics and Automation. Strumillo. Hardware/Equip.. 1994 IEEE International Conference on .... Koren. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name C.. vol. "Mobile robot obstacle avoidance in a computerized travel aid for the blind." Human System Interactions. SMPS. Software Requirements Microcontroller programming/Embedded C Programming Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 3 weeks Implementation/Experimentati on 3 weeks 4 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books  Instrument Engineers' Handbook. no. 2008 Conference on . Materka. Shoval. M. . SMPS.. no. 2011 International Conference on .419. 35 June 2011 2International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Impact Factor (2012): 3.. Microcontroller and allied circuitryTone generator. and save wastage of water and electricity." Communication Systems and Network Technologies (CSNT).Aurora’s Engineering College.422. 1: Process Measurement and Analysis Hardcover by Bela G. Requirements Software Requirements (Not to This project is to help farmers to keep their water motor pumps turned on continuously. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name C. Ladhake. and to control the pumps remotely. Antenna for GSM modem Microcontroller programming/Embedded C Programming Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 3 weeks 3 weeks 4 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentati on Result Analysis Suggested Readings Books  Instrument Engineers' Handbook. S. To help farmers overcome this issue. vol. "Innovative Cost Effective Approach for Cell Phone Based Remote Controlled Embedded System for Irrigation. pp. V. Liptak (Editor)  Transducer and instrumentation by dvs murthy Journals 1. GSM modem.358 Automatic Ambulance Rescue System Using Shortest Path Finding Algorithm .A.C. Websites: Any other information 52 . Vol.E Project Title Remote Control for Rural Irrigation Description Hardware/Equip.Pramod Kumar Department E.Ahmed. Infrared sensing. controls the traffic lights. Liptak (Editor)  Transducer and instrumentation by dvs murthy Journals 1.Aurora’s Engineering College. Calafate.. Sept.910. P.. thus it finds the accident spot. Vol.. This scheme is fully automated. "Automatic Accident Detection: Assistance Through Communication Technologies and Vehicles.913. pp. Fan Hanbo.T. no. Martinez. Vibration sensor. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name C.90. IEEE . J. F.GSM modem. Infrared sensing. Microcontroller programming/Embedded C Programming Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 3 weeks 3 weeks 4 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentati on Result Analysis Suggested Readings Books  Instrument Engineers' Handbook. Requirements Software Requirements (Not to E.3. 2012 2Wang Wei. Garrido. helping to reach the hospital in time Non-Intrusive types of sensor is fitted on the road. 2011 International Conference on .-C." Electric Information and Control Engineering (ICEICE).J. 1: Process Measurement and Analysis Hardcover by Bela G.E AUTOMATIC ACCIDENT DETECTION AND AMBULANCE RESCUE WITH INTELLIGENT TRAFFIC LIGHT SYSTEM The ambulance is controlled by the control unit which furnishes adequate route to the ambulance and also controls the traffic light according to the ambulance location and thus reaching the hospital safely.C." Vehicular Technology Magazine. M.. Antenna for Gps system..100. 15-17 April 2011 Websites: Any other information 53 . Microcontroller and allied circuitry. pp. SMPS power supply with battery back-up. "Traffic accident automatic detection and remote alarm device.. P. Cano.7.The controller identifies the location of the accident spot through the sensor systems in the vehicle which determined the accident and thus the controller walks through the ambulance to the spot. no. Max 232. Manzoni. vol. Fire sensor.Pramod Kumar Department Project Title Description Hardware/Equip.. C.. vol.Fogue. 54 . In July 1998. Requirements Software Requirements (Not to exceed Orthogonal Frequency Divisional Multiplexing for Wireless Networks Orthogonal frequency division multiplexing (OFDM) is a special case of multicarrier transmission. Universal Personal Communications. 2092-2100. Gerhard Bauch. Websites: 1. This new standard is the first one to use OFDM in packet-based communications. “Cyclic Delay Diversity with Bit-Interleaved Coded Modulation in Orthogonal Frequency Division Multiple Access”. 2004 edition. IEEE Transactions on Wireless Communications. Ramjee Prasad.E Project Title Description Hardware/Equip .C. 2001. Proakis. the IEEE standardization group decided to select OFDM as the basis for their new 5GHz standard. Senior Member.dsplog. In this project. Journals 1. pp. 5.Aurora’s Engineering College. No. to evaluate the performance and different possibilities in the implementation PC MATLAB Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentation 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books 1. 8. while the use of OFDM until now was limited to continuous transmission systems. Bhongir PROJECT DESCRIPTION DOCUMENT one page) Faculty Name Shravan Kumar Reddy M Department E. targeting a range of data stream from 6 up to 54 Mbps. New York. “OFDM for wireless communications”. and Javed Shamim Malik. October 2006. where a single data stream is transmitted over a number of lower rate subcarriers.” Fourth Edition. transmitter and receiver were simulated according to the parameters established by the standard. http://www. Vol. 2. John G. IEEE. McGraw Hill.com Any other information 55 . “Digital Communications. N. http://www.’ IEEE Transactions on Communications. Typically pulse shaping occurs after line coding. vol.com Any other information Date 56 . Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name Shravan Kumar Reddy M Department E.. 2.E Project Title Description Hardware/Equi p. “A family of pulse-shaping filters with ISI Free matched and unmatched filter properties”. Requirements Software Requirements (Not to Pulse shaping filters with ISI free properties Pulse shaping is the process of changing the waveform of transmitted pulses. NO. www. the inter symbol interference caused by the channel can be kept in control. 47.Aurora’s Engineering College. John G. ‘Generalized Raised-Cosine Filters. “Digital Communications. 7. no 10.com 2. Websites: 1. 2001. VOL. Journals 1. G. By filtering the transmitted pulses this way. ALAGHA and P. IEEE Trans. and before modulation. Communications. Oct.JULY 1999. pp. Its purpose is to make the transmitted signal suit better to the communication channel by limiting the effective bandwidth of the transmission.dsplog.mathworks.1157-1158. 45. New York. 1997. All the simulation work is done using MATLAB software. 989-997.C. Xia. In RF communication pulse shaping is essential for making the signal fit in its frequency band.” Fourth Edition. McGraw Hill. S. PC MATLAB Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentation 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books 1. KABAL. pp. Proakis. X. www. Fifth Indian Reprint . Nov. Requirements Software Requirements (Not to Statistical region merging Segmentation is the process of partitioning an image into disjoint and homogeneous regions.C. “ Statistical Region Merging”.mathworks. SRM is a lineartime fast and simple region growing segmentation algorithm based on an adaptive statistical threshold merging predicate on color channels that does not require maintaining dynamically the region adjacency graph. noise and user-input bias. vol.2004. there is lot of increase in speed of execution of algorithm and cost of computation is also decreased. Richard Nock and Frank Nielsen. Statistical Region Merging (SRM) algorithm is one of such algorithms.Aurora’s Engineering College. Journals 1. Gonzalez and Richard E. PC MATLAB Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentation 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books 1. Rafael C. Woods.com Any other information Date 57 . Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name Shravan Kumar Reddy M Department E. SRM handles nicely occlusion. "Digital Image Processing"' Addison-Wesley. Websites: 1. page(s) 1452-1458. IEEE transactions on Pattern Analysis and Machine Intelligence.E Project Title Description Hardware/Equip. So many advanced techniques have been developed for segmentation of color images. In recent days.2000.26. Rafael C. www.7. The reasons for choosing MATLAB are compactness (complex algorithms can be expressed in a very few lines of code) and graphics support. canny are used to detect surface deformities.com Any other information 58 . Requirements Software Requirements (Not to E. PC MATLAB Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books 1. "Digital Image Processing"' Addison-Wesley.C. Gonzalez and Richard E. Fifth Indian Reprint . Woods. All the simulation work undertaken during this mini project is performed in MATLAB v.mathworks. Journals Websites: 1.Aurora’s Engineering College.2000. prewitt.E Image segmentation techniques Segmentation techniques like region growing segmentation and edge detection using different operators like sobel. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name Shravan Kumar Reddy M Department Project Title Description Hardware/Equip. Dan.1 Jan 1998. and compute the SVD of a matrix example by calculation and by using MATLAB.27 No. The goal of studying the SVD of a matrix is to create approximations of the full mxn matrix by only using some of the terms of the diagonal matrix in the decomposition.Vol. Journals [1] Kalman. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name M Shravan Kumar Reddy Department E. Gonzalez and Richard E.mathworks. 2-23. “A Singularly Valuable Decomposition. since images can be viewed as matrices with each pixel being an element of a matrix. Woods. This approximation of the full matrix is the basis of image compression using SVD. Requirements Software Requirements (Not to Any mxn matrix can be factored into the product of an orthogonal matrix times a diagonal matrix times another orthogonal matrix.E Project Title SVD based image compression Description Hardware/Equip.2000. and implement the image compression algorithm developed for a sample image by using MATLAB. This is called the Singular Value Decomposition (SVD) of a matrix.Aurora’s Engineering College. PC MATLAB Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 2 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 2 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 11 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books :[1] Rafael C. Fifth Indian Reprint .C. we will prove the theorem of Singular Value Decomposition (SVD). In this project. Websites:[1] www. We will also explain how the SVD can be applied to compress images.” The college Mathematics Journal.com Any other information 59 . "Digital Image Processing"' Addison-Wesley. This is implemented using state machine concept. Hardware/Equip. Description This project mainly deals with the security system by using combinational circuit. If the input pattern is same as the pattern stored in memory then it will unlock the equipment. verilog hdl by palnitker and verilog hdl by j. Sravan kumar (Not to Department E. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name R.ac.bhakar.iitm.in Any other information 60 .E Project Title FPGA implementation of combinational lock for security system. Journals Websites: Nptel.C. Implementation/Experimentatio n Result Analysis Suggested Readings Books Verilog hdl by padmanabhan . We have to generate a particular combinational circuit for testing and we have to store the security code in memory.Aurora’s Engineering College.1 or higher Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks. Requirements Software Requirements Spartan 3E FPGA Xilinx 10. Requirements Software Requirements Spartan 3E FPGA Xilinx 10. Hardware/Equip.1 or higher Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks. Description This project mainly deals with data storage and flow within the memory of chip. Suggested Readings Books Verilog hdl by padmanabhan .Aurora’s Engineering College. verilog hdl by palnitker and verilog hdl by j.iitm. perfect synchronization is maintained for read and write cycles between memory chips if we are performing an interface operation.in Any other information 61 . Sravan kumar Department E. Here.E Project Title FPGA implementation of FIFO controller. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) (Not to Faculty Name R.C.bhakar. Journals Websites: Nptel.ac. Requirements Software Requirements Spartan 3E FPGA Xilinx 10.1 or higher Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks.iitm.e state1 for Rs1.ac. Implementation/Experimentatio n Result Analysis Suggested Readings Books Verilog hdl by padmanabhan .bhakar. etc. The items will dispatch based on the users input to the vending machine.in Any other information 62 .Aurora’s Engineering College. state2 for Rs2. verilog hdl by palnitker and verilog hdl by j.C.E Project Title FPGA implementation of vending machine using state machines. Sravan kumar (Not to Department E. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name R. Hardware/Equip. Description This project mainly develops an automatic vending machine which is controlled by state machines which has states upto 3 i. Journals Websites: Nptel. 1430– 1433.Aurora’s Engineering College. single 8X8 multiplication and twin parallel 8X8 multiplication operations. Choi. Honarmand and A. Requirements Software Requirements PC Xilinx-ISE(VHDL). 131–136. vol.-S. I. 2006. pp. Jan.com. A. Conf..com Any other information 63 .E Project Title DESIGN OF LOW POWER AND HIGH SPEED CONFIGURABLE BOOTH MULTIPLIER Description To Design a low power and high speed configurable booth multiplier that supports single 16X16 multiplication. N.” in Proc. pp. Dec. “A spurious-power suppression technique for multimedia/DSP applications. pp. “Power minimization of function units by partially guarded computation. no. Chen and Y. Jeon. [2]. A. Fayed A and M. Apr. 2001. Soc. Choi. 149–154. Jul.” in Proc. J. Chu.C. Int. 132–143. Des. Bayoumi. PHI Publications Circuit Desing using VHDL by Pedroni VHDL by B.xilinx.” in Proc. K.Bhaskar Digital Signal Processing by Vallavraj&Salivahanan Journals [1].” IEEE Trans. 2000. “Low power minimization combinational multipliers using data-driven signal gating. Symp. J. Asia-Pacific Circuits Syst. www. 1. Low Power Electron. Hardware/Equip. www.-H. Annu Workshop VLSI. 56. IEEE Int. [4]. Reg. Websites :www. Circuits Syst. Papers. Kusha. [3]. Bhongir PROJECT DESCRIPTION DOCUMENT one page) (Not to exceed Faculty Name SRAVAN KUMAR R. IEEE Comput. pp.. 2009.wikipedia. Department E.howstuffswork.com. and K. “A novel architecture for low-power design of parallel multipliers. Modelsim simulator Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentation 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books :Digital Signal Processing by Johny. C.1 or higher Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 2 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 12 weeks Implementation/Experimentati on Result Analysis Suggested Readings Books Verilog hdl by padmanabhan . Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name Sai Prasad Goud A (Not to Department E. verilog hdl by palnitker and verilog hdl by j. Journals Ijdacr Websites: Any other information 64 . Hardware/Equip.E Project Title Implementation of BIST for testing combinational circuit using FPGA Description This project mainly deals with the testing of any combinational circuit with the random test vectors which is to be applied to combinational circuit to test the functionality of the circuit. Requirements Software Requirements Spartan 3E FPGA Xilinx 10.bhakar.Aurora’s Engineering College. Requirements Software Requirements Spartan 3E FPGA Xilinx 10.Aurora’s Engineering College.E Project Title FPGA implementation of intelligent car parking system for real time application Description This project mainly deals with the car parking systems which is done automatically in a step by step process to verify the identity. Hardware/Equip.1 or higher Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 2 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 2 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 11 weeks Suggested Readings Books Verilog hdl by padmanabhan .C. This can be designed using verilog hdl and can implemented in real time applications.bhakar. verilog hdl by palnitker and verilog hdl by j. parking space in slots etc. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) (Not to Faculty Name Sai Prasad Goud A Department E. Journals Ijcsi Websites: Any other information 65 . verilog hdl by palnitker and verilog hdl by j. Journals International conference on recent trends in computer and information engineering-2013. Requirements Software Requirements Spartan 3E-FGPA board Xilinx 10.bhakar. Hardware/Equip.C. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name Saiprasad goud A (Not to Department E. Description This project mainly deals with the efficient design of home automation system using verilog HDL and a possible solution where the user controls the devices by employing an FPGA interface to which the devices and sensors are interfaced.1 or higher Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 2 weeks Analysis and Design 4 weeks 5 weeks 3 weeks 2 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books Verilog hdl by padmanabhan .E Project Title Home automation system design using verilog HDL. Websites: Any other information 66 .Aurora’s Engineering College. Zigbee Touch screen   Embedded C KEIL µVision IDE Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentati on 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books   Embedded Design with the PIC 18F452Micro Controller by John Peatman.1 st Edition.com  www.C. drinks etc. request them if they need anything in the flight like coffee.E Project Title Touch Screen and Zigbee Based Wireless Communication Assistant For Dumb/Illiterates In Airlines Description As there a different language in the world and it is impossible to know all the languages. So. PIC Micro Controller An Introduction to software & hardware interfacing.e. in this project a device is built that helps illiterate/dumb people in expressing their needs with other language people (Air hostess) i. published2003 by prentice Hall. Requirements Software Requirements   Micro controller .Aurora’s Engineering College. tea.freescale. In this project Touch screen Technology is used to make it easy even to illiterates to operate to convey their needs as it includes images. which indicates the needs.touchscreens.com Any other information 67 .networkworld. published 2004 by Delmav Cengage Learning Journals Websites  www.Han Way Huang. Leo Chartrand.PRADEEP KUMAR GOUD Faculty Name Department E. Bhongir PROJECT DESCRIPTION DOCUMENT N. This even reduces the difficulty to airhostess in receiving the passengers with different languages Hardware/Equi p.com  www. org/Xplore/login.com  www. IR Sensor.com Any other information 68 .jsp?url=/iel5/30/4560070/04560131.Aurora’s Engineering College. Gas Sensor.Steve Furber Journals http://ieeexplore.PRADEEP KUMAR GOUD Department E.C.nxp. Requirements Software Requirements Microcontroller (Lpc 2148). The security system consists of two modules.com  www. GSM Modem Embedded C. GSM modem and microcontroller board interfaced with different sensors. Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name N.ieee.national.Oliver Barley Arm system developer’s guide.pdf? arnumber=4560131 Websites:  www.E Design And Application Of Mobile Embedded System For Home Care Project Title Application In this project a low cost GSM based home security system is developed using embedded secured system with ARM microcontroller. Hardware/Equip. Temperature sensor.electronicsforyou.keil. This system Description need to be mounted in house.KEIL µVision IDE Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books Embedding systems design. which is continuously monitored.com  www. Dr TC Manjunath:'Design and Development of GSM based vehicle theft control system' Advanced Computer Control ICACC '09 International conference. If it fails automatically it alerts the by using GSM modem exact message will be given to the owner of the vehicle. The user can give three attempts to match the password.com/red/pie/ cri-car-the-crime-car-thefts http://www.C.Aurora’s Engineering College.architecture. The design is robust and simple Hardware/Equip. M.RS232 Embedded C .GSM . Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name N. The present system is an excellent and cost effective to prevent car theft . Ravi Rayappa. This technique helps in taking fast steps towards an attempt to steal . If the password matches then the user has to insert the key to start the vehicle.Mahesh. Chandrasekhar M Patil.unitracking. programming and design"Second Edition 2009 Journals B.nationmaster. com/howitworks.Here the user owning a car types a password if it matches with the existing only the vehicle gets started for the symbolic representation relay turns ON.PRADEEP KUMAR GOUD Department E.Nagaraja.G. KEIL µVision IDE Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books Raj Kamal "Embedded Systems .E Project Title ANTI THEFT CONTROLLING SYSTEM USING EMBEDDED SYSTEM Description This Project anti theft control system for automobiles tries to prevent the theft of a vehicle using GSM-SMS services.html Any other information 69 .LCD. Requirements Software Requirements Microcontrolller(LPC 2148).pp 148 Websites: http://www. M Calcutt Embedded System Design.based microcontrollers-Trevor Martin Journal Websites: www. Chris Wright 8051 Microcontrollers.By Steve Furber ARM System Developer Guide-By Andrew Sloss. TV. such as microwave oven. and for coordination among the various processes running on such devices. Requirements Software Requirements Implementation of Touch screen Based Home Appliances Control System Using ARM7 LPC2148 and Zigbee A home appliance control system (HACS) is a system which provides various services to remotely operate on home appliances. the HACS needs mechanisms for communication between the different devices in the system.com www.com www.nmsu. desktop and palm-top.Aurora’s Engineering College.Zigbee KEIL U VISION Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books ARM System-On-Chip Architecture(2nd Edition) .Software and Applications-By D. touch screen .electronicsforyou. Hardware. and garage door etc through remote devices such as mobile phone.et. Dominic Slymes. Bhongir PROJECT DESCRIPTION DOCUMENT Faculty Name N.By Frank Wahid Embedded System Design(Second Edition)-By Steve Heath The Insider’s Guide to the Philips ARM 7.Zigbee is one such mechanism by which wireless communicaion can be established LPC 2148 ARM controller. In order to activate home appliances and to allow for different ways of cooking.national.E Project Title Description Hardware/Equip.PRADEEP KUMAR GOUD Department E.C.edu Any other information 70 . "MIMO antenna subset selection with space time coding. and Y. Bahceci. T.Journal on FPGA implementation of MIMO module 2. Mar..2 580-2588. Gore and A. Duman. Journals: 1. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) (Not to Faculty Name T. Signal Process.Saritha Department E.E Project Title FPGA Implementation of Alamouti MIMO Selection for ReceiverAntenna Selection Combining Description The Alamouti multiple-input mUltiple-output (MIMO) detector based on the log-likelihood ratio (LLR) selection statistic for receiverantenna selection combining (SC) is implemented on an FPGA platform. pp.Aurora’s Engineering College. D.C. "Antenna selection for multipleantenna transmission systems: Performance analysis and code construction.2 002. In! Theory. 2. Oct. Hardware/Equip.dsplog.2 003. pp.Journal on ALAMOUTI STBC." IEEE Trans. M.com rfwireless-world." IEEE Trans. where hardware simulation using Verilog HDL is illustrated. Altunbasak. and the BPSK signaling is considered.com Any other information 71 . Paulraj. Requirements Software Requirements no Verilog hdl Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentati on 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Suggested Readings Books: 1.2 669-2681. Websites: www. Using MTCMOS approach compare leakage current and leakage power of full subtractor in active mode. Hardware/Equip. Reducing power dissipation is one of the most principle subjects in VLSI design today.Ken Martin.C. third Edition. But Scaling causes sub threshold leakage currents to become a large component of total power dissipation.pearsonhighered.pptsearch365. New York.7 volt using cadence virtuoso tool in 45nanometer technology. simulation result is performed at 0. Digital Integrated Circuit Design. 2. 2005. Harris.Aurora’s Engineering College.www. www. Journal: Design of Low Power Half-Subtractor Using AVL Technique Based on 65nm CMOS Technology Websites: 1. Oxford University Press. “CMOS VLSI Design: A Circuit and System Perspective Pearson Addition Wesley.Saritha (Not to Department E.Neil Weste and D. 2000.com Any other information 72 .E Project Title Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique Description In this paper a full subtractor using MTCMOS technique design is proposed.com 2. Requirements Software Requirements nil Xilinx Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books: 1. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) Faculty Name T. Ricardo A.com 2. CIC filters function as efficient anti-aliasing filters before downsampling of signals in decimation process and as anti. ieeexplore. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) (Not to Faculty Name T.May 2008. 2.enggjournals. www.ieee. Losada.”Digital Filters with Matlab” . .imaging filters after upsampling of signals in interpolation process. Multirate Signal Processing for Communicating Systems. This paper also discusses about pipelining.org Any other information 73 .The Mathworks Inc.Aurora’s Engineering College.E Project Title Design of Optimized CIC Decimator and Interpolator in FPGA Description This paper analyzes optimized architecture and implementation aspects of decimator and interpolator using CIC filter. Requirements Software Requirements Not required Modelsim and Matlab Project Activity Recommended Duration Literature Survey 3 weeks Suggested Duration by Faculty 3 weeks Analysis and Design 4 weeks 4 weeks 3 weeks 3 weeks 2 weeks 2 weeks Documentation 1 week 1 week Overall 13 weeks 13 weeks Implementation/Experimentatio n Result Analysis Suggested Readings Books: 1. Hardware/Equip. throughput and area reduction techniques and performance analysis with respect to the number of stages (N) and rate change factor (R) of the filter.Saritha Department E. Harris. 2004. Journal: Journal on FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications Websites:1.C.Fredric J. “Codes on finite geometries. “Fault secure encoder and decoder for nanomemory applications 2) H.Aurora’s Engineering College.C.wikipedia. Apr.(VLSI) Syst. 2009 Websites: 1)ita. Abdel-Ghaffar. Bhongir PROJECT DESCRIPTION DOCUMENT exceed one page) (Not to Faculty Name T. Hardware/Equip. Naeimi and A. The objective was to reduce the decoding time by stopping the decoding process when no errors are detected. 473–486. vol.ucsd.Saritha Department E.edu 2) en. 17. The designer now has a larger choice of word lengths and error correction capabilities. making the modified one step majority logic decoding more attractive for memory applications. Xu. and K. Tang. no. pp. The simulation results show that all tested combinations of errors affecting up to four bits are detected in the first three iterations of decoding. Lin. the detection of errors during the first iterations of serial one step Majority Logic Decoding of EG-LDPC codes has been studied. A. S. Requirements Software Requirements --xilinx Project Activity Recommended Duration Suggested Duration by Faculty Literature Survey 3 weeks 3 weeks Analysis and Design 4 weeks 4 weeks Implementation/Experimentatio n 3 weeks 3 weeks Result Analysis 2 weeks 2 weeks Documentation 1 week 1 weeks Overall 13 weeks 13 weeks Suggested Readings Books: 1) H. 4.” Journals: 1) IEEE Trans. These results extend the ones recently presented for DS-LDPC codes. Very Large Scale Integr.. DeHon. S. J.E Project Title Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes Description In this brief.org Any other information 74 .