BASIC CHARACTERISTICS OF DIGITAL ICsDigital ICs are a collection of resistors, diodes, and transistors fabricated on a single piece of semiconductor material (usually silicon) called a substrate, which is commonly referred to as a chip. The chip is enclosed in a protective plastic or ceramic package from which pins extend for connecting the IC to other devices. One of the more common types of package is the dual-inline package (DIP), shown in Figure 3.8. A DIP is a rectangular package with rows of pins running along its two longer edges. The pins are numbered counterclockwise when viewed from the top of the package with respect to an identifying notch or dot at one end of the package see Figure 3.9 (b) (a) figure 3-9 (a) Dual-in-line package (DIP); (b) top view; (c) actual silicon chip is much smaller than the protective package; (d) PLCC package (d) This numbering method is used for these packages PLCC (Plastic Leaded Chip Carrier) 48 | P a g e Digital ICs are often categorized according to their circuit complexity as measured by the number of equivalent logic gates on the substrate. resulting in an output voltage of (practically) 0 volts. but its basic circuit arrangement forms the foundation for all the TTL series ICs. we would say that the input signal is a binary "1" and that the output signal is a binary "0. Notice that the circuit contains several bipolar transistors as the main circuit element." Any voltage close to full supply voltage (measured in reference to ground. It is no longer used in new designs. Unipolar ICs use the unipolar field-effect transistor (P-channel and N-channel MOSFETs) as their main element. The transistor-transistor logic (TTL)family has been the major family of bipolar digital ICs for over 30 years. Because its saturated. of course) is considered a "1" and a lack of voltage is considered a "0. There are currently six levels of complexity that are commonly defined as shown in Table 3-4. The standard 74 series were the first series of TTL ICs. TTL INVERTER circuit In the above circuit. the transistor drops very little voltage between collector and emitter. If we were using this circuit to represent binary bits. Bipolar ICs are made using the bipolar junction transistor (NPN and PNP) as their main circuit element. the transistor is in a state of saturation by virtue of the applied input voltage (5 volts) through the two-position switch. Bipolar and Unipolar Digital ICs Digital ICs can also be categorized according to the principal type of electronic component used in their circuitry. having been replaced by several higher performance TTL series. This circuit arrangement is shown in Figure 3-10 for the standard TTL INVERTER." 49 | P a g e . because it outputs the exact opposite digital signal as what is input. Shown here is a schematic diagram for a real inverter circuit. or NOT gate. we apply a binary "0" to the input and receive a binary "1" at the output The gate shown here with the single transistor is known as an inverter.Moving the switch to the other position. Real inverter circuits contain more than one transistor to maximize voltage gain (so as to ensure that the final output transistor is either in full cutoff or full saturation). and other components designed to reduce the chance of accidental damage. complete with all necessary components for efficient and reliable operation: 50 | P a g e . The single-transistor inverter circuit illustrated earlier is actually too crude to be of practical use as a gate. stripping away all other portions of the circuit so that we can concentrate on the current "steered" through the two back-to-back diodes: 51 | P a g e . rather than positive. The following schematic shows the real function of Q1: The purpose of these diodes is to "steer" current to or away from the base of transistor Q 2. In reality. In fact. representing the baseemitter junctions of transistors Q2 and Q4 as single diodes.Let's analyze this circuit for the condition where the input is "high. With no voltage between the base and emitter of transistor Q1. with respect to ground). either. depending on the logic level of the input. as strange as it may seem. Exactly how these two diodes are able to "steer" current isn't exactly obvious at first inspection. the only purpose for having D1 in the circuit is to prevent transistor damage in the case of a negative voltage being impressed on the input (a voltage that is negative. Q1 is being used in this circuit as nothing more than a back-to-back pair of diodes. transistor Q1 is not being used as is customary for a transistor. so a short example may be necessary for understanding. and therefore not conduct any current. We can simulate this by showing the input terminal connected to V cc through a switch: In this case. However. diode D1 will be reverse-biased. we would expect no current through it. Suppose we had the following diode/resistor circuit." or in a binary "1" state. With the input switch in the "up" position (connected to V cc). which will turn them on to conduct collector current. approximately 0. transistors Q2 and Q4 will have base current. Q 2's baseemitter diode. and R1. there will be current through the right steering diode of Q1. And then when they 52 | P a g e . because there isn't any voltage in the switch-diode-R1-switch loop to motivate electrons to flow. The total voltage dropped between the base of Q1 (the node joining the two back-to-back steering diodes) and ground will be about 2. it should be obvious that there will be no current through the left steering diode of Q1. we would find that all of the current goes through the left steering diode of Q1 and none of it through the right diode. Why is this? It still appears as though there is a complete path for current through Q4's diode. so why will there be no current through that path? Remember that PN junction diodes are very nonlinear devices: they do not even begin to conduct current until the forward voltage applied across them reaches a certain minimum quantity. equal to the combined voltage drops of three PN junctions: the right steering diode. Q2's diode. as well as through Q2's base-emitter diode junction and Q4's base-emitter diode junction: This tells us that in the real gate circuit. and Q4's base-emitter diode.3 volts for germanium. the right diode of the pair.7 volts for silicon and 0. However.1 volts. Now. let's move the input switch to the "down" position and see what happens: if we were to measure current in this circuit. 7 volts provided by the left diode's forward voltage drop is simply insufficient to allow any electron flow through the series string of the right diode. the input is held "high" by the switch (connected to Vcc).begin to conduct current. making the left steering diode (zero voltage dropped across it). which also happens to be the minimum voltage necessary to forward-bias three series-connected silicon PN junctions into a state of conduction. neither one will be able to conduct collector current: transistors Q2 and Q4 will both be in a state of cutoff. thus saturating it as well: 53 | P a g e . and the R3//Q4 diode parallel sub circuit. they will not drop substantially more than 0. Consequently." More specifically. Q2's diode. With no current through the bases of either transistor Q 2 or Q4. resistor R3will be dropping enough voltage to forward-bias the base-emitter junction of transistor Q4. However.7 volts across it and no more. there was about 2. the right steering diode is conducting current through the base of Q2. In the case of our example gate circuit. this circuit configuration allows 100 percent switching of Q2 base current (and therefore control over the rest of the gate circuit. With Q2 saturated. through resistor R1: With base current provided.1 volts dropped between those same two points (Q1's base and ground). and so no electrons flow through that path. and so it drops about 0. transistor Q2 will be turned "on. The 0. it will be saturated by virtue of the more-than-adequate current allowed by R1 through the base. the left diode of the steering diode pair is fully conducting. including voltage at the output) by diversion of current through the left steering diode.7 volts. When the switch in this circuit is in the "down" position. Recall that with the switch in the "up" position (transistors Q2 and Q4 conducting). there is no longer a path for Q4 base current. With this. Due to the presence of diode D2. thus turning it off. Q3. there will be no current through the left steering diode of Q1. With the input terminal left unconnected. leaving the output terminal at a voltage (in reference to ground) of almost 0 volts.With Q4 saturated. thus raising the output terminal voltage to a "high" state. note that this inverter circuit's input will assume a "high" state of left floating (not connected to either Vcc or ground). or a binary "0" ("low") logic level. our simulation of the inverter circuit is complete: a "1" in gives a "0" out. With Q2 off. so Q4 goes into cutoff as well. on the other hand. In actuality. and vice versa. This eliminates current through the base of Q2. but still high enough to be considered a "high" (1) logic level. the output voltage will be somewhere around 4 volts depending on the degree of saturation and any load current. Let's see now what happens if we reverse the input's logic level to a binary "0" by actuating the input switch: Now there will be current through the left steering diode of Q1 and no current through the right steering diode. now has sufficient voltage dropped between its base and ground to forward-bias its baseemitter junction and saturate it. thus saturating Q2 and driving the circuit output to a "low" state: 54 | P a g e . leaving all of R1's current to go through Q2's base. there will not be enough voltage between the base of Q3 and its emitter to turn it on. the output terminal will be almost directly shorted to ground. so it remains in cutoff. through the emitter of Q3. then the output of any gate driving a TTL input need only provide a path to ground for a low state and be floating for a high state. Technically. there is continuity from the output terminal to V cc through the top output transistor (Q3). known as Transistor-to-Transistor Logic. into the gate's output terminal.The tendency for such a circuit to assume a high input state if left floating is one shared by all gate circuits based on this type of design. this is known as sourcing and sinking current. A gate circuit as we have just analyzed has the ability to handle output current in two directions: in and out. knowing that the outputs of gates typically drive the inputs of other gates. When the gate output is high. and eventually up to the Vcc power terminal (positive side of the DC power supply): 55 | P a g e . If the input of a TTL gate circuit assumes a high state when floating. through a load. This concept may require further elaboration for full understanding. respectively. or TTL. so I will explore it in detail here. This characteristic may be taken advantage of in simplifying the design of a gate's output circuitry. allowing electrons to flow from ground. the combination of Q3 saturated and Q4 cutoff is analogous to a double-throw switch in the "Vcc" position. and back to V cc. when a gate circuit is outputting a "low" logic level to a load. capable of connecting the output terminal either to V cc or ground. In this condition. providing a path for current through a grounded load: Please note that this two-position switch shown inside the gate symbol is representative of transistors Q3 and Q4 alternately connecting the output terminal to Vcc or ground. not of the switch previously shown sending an input signal to the gate! Conversely. depending on its state.To simplify this concept. Current will then be going the other way if the load resistance connects to Vcc: from ground. the gate is said to be sinking current 56 | P a g e . we may show the output of a gate circuit as being a double-throw switch. through the emitter of Q4. For a gate outputting a "high" logic level. it is analogous to the double-throw switch being set in the "ground" position. through the load resistance. out the output terminal. and need not source current to provide a "1" or a "high" logic level at the input of the receiving gate: This means we have the option of simplifying the output stage of a gate circuit so as to eliminate Q3 altogether.The combination of Q3 and Q4 working as a "push-pull" transistor pair (otherwise known as a totem pole output) has the ability to either source current (draw in current to V cc) or sink current (output current from ground) to a load. a standard TTL gate input never needs current to be sourced. only sunk. That is. since a TTL gate input naturally assumes a high state if left floating. However. The result is known as an open-collector output: 57 | P a g e . any gate output driving a TTL input need only sink current to provide a "0" or "low" input. the acceptable input voltage ranges for the logic 0 and logic 1 levels are defined as shown in Figure 3-11(a). and voltages from 3. The indeterminate range includes voltages between 1. TROUBLESHOOTING DIGITAL SYSTEMS There are three basic steps in fixing a digital circuit or system that has a fault (failure): 1. For standard TTL devices. The IC manufacturers cannot guarantee how a TTL circuit will respond to input levels that are in the indeterminate range (between 0. A logic probe is used to monitor the logic level activity at an IC pin or any other accessible point in a logic circuit. although +5 V is most often used when CMOS integrated circuits are used in the same circuit with TTL integrated circuits.0 V).8 and 2. and so on.8 V.5 V are defined as a logic 0.5 and 3.Logic-Level Voltage Ranges For TTL devices. Voltages that are not in either of these ranges are said to be indeterminate and should not be used as inputs to any TTL device. 58 | P a g e . Observe the circuit/system operation and compare it with the expected correct operation.5 to 5 V are defined as a logic 1. Perform tests and make measurements to isolate the fault. The logic input voltage ranges for CMOS integrated circuits operating with VDD= +5 V are shown in Figure 3-11(b). VDD can range from +3 to +18 V. The logic probe has a pointy metal tip that is touched to the specific point you want to test. repair the faulty connection. remove the short. 2. Fault correction. VCC is nominally +5 V. For CMOS integrated circuits. it is shown probing (touching) pin 3 of an IC.5 V. a logic 1 is any voltage from 2 to 5 V. A logic 0 is any voltage in the range from 0 to 0. Fault detection. Replace the faulty component. Fault isolation. 3. Here. Voltages between 0 and 1. the LED will continue to flash at around 3 Hz. If the transitions are occurring frequently. Inputs or outputs shorted to ground or VCC 3. Any transitions (LOW to HIGH or HIGH to LOW) will cause the yellow LED to flash on for a fraction of a second and then turn off. the IC outputs do not respond properly to the IC inputs.The logic level that is present at the probe tip will be indicated by the status of the indicator LEDs in the probe. By observing the green and red LEDs along with the flashing yellow. not connected to any source of voltage. Inputs or outputs open-circuited 4. Figure 3-12 INTERNAL DIGITAL IC FAULTS The most common internal failures of digital ICs are: 1. This type of probe also offers a yellow LED to indicate the presence of a pulse train. There is no way to predict what the outputs will do because it depends on what internal component has failed. you can tell whether the signal is mostly HIGH or mostly LOW. Malfunction in the internal circuitry 2. Examples of this type of failure would be a base-emitter short in transistor Q4 Input Internally Shorted to Ground or Supply 59 | P a g e . The four possibilities are given in the table of Figure 3-12. Short between two pins (other than ground or VCC) Malfunction in Internal Circuitry This is usually caused by one of the internal components failing completely or operating outside its specifications. This includes the condition where the probe tip is touched to a point in a circuit that is open or floating that is. When this happens. Note that an indeterminate logic level produces no indicator light. as in Figure 3-13(b). an IC input pin could be internally shorted to +5 V. The open gate input will be in the floating 60 | P a g e . Similarly. as shown in Figure 3-13(d). it will not reach the NAND-1 gate input and so will not have an effect on the NAND-1 output. Thus.This type of internal failure will cause an IC input to be stuck in the LOW or HIGH state. in other words. producing an open circuit. Open-Circuited Input or Output Sometimes the very fine conducting wire that connects an IC pin to the IC’s internal circuitry will break. If this input pin is being driven by a logic signal A. This will cause pin 2 always to be in the LOW state. Figure 3-13(c) shows pin 3 of the NAND gate shorted to ground within the IC. Note that this type of failure has no effect on the logic signals at the IC inputs. and it will not respond to the conditions applied to input pins 1 and 2. If a signal is applied to pin 13. it will effectively short A to +5 V. this type of fault will affect the output of the device that is generating the B signal. This would keep that pin stuck in the HIGH state. it will effectively short B to ground. This forces the output pin 3 to be stuck HIGH regardless of the state of the signals at the input pins. Figure 313(a) shows input pin 2 of a NAND gate shorted to ground within the IC. This output is stuck LOW. An IC output pin can also be shorted to + 5 V within the IC. Figure 3-14 in Example 1 shows this for an input (pin 13) and an output (pin 6). If this input pin is being driven by a logic signal B. Figure 3-13 Output Internally Shorted to Ground or Supply This type of internal failure will cause the output pin to be stuck in the LOW or HIGH state. logic inputs A and B will have no effect on output X. thereby keeping it stuck LOW. If not. however. Second. The open at the NAND-4 output prevents the signal from reaching IC pin 6. First. pin 1 of Z2 could be shorted to ground internal to Z2. there could be an internal component failure in the INVERTER that prevents it from responding properly to its input. Examine these results and determine if the circuit is working properly. As stated earlier. Third.state. and CMOS devices will respond erratically and may even become damaged from overheating. pin 4 of the INVERTER could be shorted to ground internal to Z1. Because this is connected to Z2 pin 1. Example 1 A technician uses a logic probe to determine the conditions at the various IC pins.This would prevent the INVERTER output pin from changing. If this pin is connected to the input of another IC. In addition to these possible faults. The recorded results. we can list three possible faults that could produce this operation. suggest some of the possible faults. show that pin 4 is stuck LOW. it will produce a floating condition at that input. TTL devices will respond as if this floating input is logic 1. so there will be no stable voltage present at that pin. The results are recorded in the figure. From our preceding discussion. Solution Output pin 4 of the INVERTER should be pulsing because its input is pulsing. this keeps the NAND output HIGH. there can be external shorts to ground anywhere in the conducting path between Z1 pin 4 and Z2 pin 1 Example 2 What would a logic probe indicate at pin 13 and at pin 6 of Figure 3-14? 61 | P a g e . Example 3: Refer to the circuit of Figure 3-15 and the recorded logic probe indications. but it becomes disconnected inside the NAND chip Short Between Two Pins An internal short between two pins of an IC will force the logic signals at those pins always to be identical. there is a good possibility that the signals are shorted together. this open circuit would produce the same effect as logic HIGH at pin 1. What are some of the possible faults that could produce the recorded results? Assume that the ICs are TTL. the internal open circuit at pin 1 might have produced an indeterminate output and possible overheating and destruction of the chip. This LOW should prevent the NAND gate from responding to the pulses at pin 2.Solution At pin 13. the logic probe will indicate the logic level of the external signal that is connected to pin 13 (which is not shown in the diagram). The NAND output should be HIGH because its input pin 1 is LOW. but the NAND output is inconsistent with its inputs. There is no open circuit between Z1 pin 4 and Z2 pin 1. you might have expected that the voltage of pin 1 of Z2 would be 1. If the IC had been CMOS. Because the IC is TTL.8 V and should have been registered as indeterminate by the logic probe. It is probable that this LOW is not reaching the internal NAND gate circuitry because of an internal open. and so the voltage at Z1 pin 4 is reaching Z2 pin 1.4 to 1. At pin 6. Solution Examination of the recorded results indicates that the INVERTER appears to be working properly. From our earlier statement regarding open TTL inputs. Whenever two signals that are supposed to be different show the same logic-level variations. EXTERNAL FAULTS 62 | P a g e . This would have been true if the open circuit had been external to the NAND chip. the logic probe will show no LED lit for an indeterminate logic level because the NAND output level never makes it to pin 6. Crack or cut trace on a printed circuit board (some of these are hairline cracks that are difficult to see without a magnifying glass) 4. Example 3 Consider the CMOS circuit of Figure 3-16 and the accompanying logic probe indications. this LOW should also be at Z2-2. Open Signal Lines This category includes any fault that produces a break or discontinuity in the conducting path such that a voltage level or signal is prevented from going from one point to another. What is the most probable circuit fault? Solution The indeterminate level at the NOR gate output is probably due to the indeterminate input at pin 2. loose wire-wrap connection 3. and there must be an open circuit in the signal path between these two points. The location of this open circuit can be determined by starting at Z1-6 with the logic probe and tracing the LOW level along the signal path toward Z2-2 until it changes into an indeterminate level.We have seen how to recognize the effects of various faults internal to digital ICs. Broken wire 2. Because there is a LOW at Z1-6. Bent or broken pin on an IC 5. we will describe the most common ones in this section. Many more things can go wrong external to the ICs.e. Poor solder connection. a low-resistance path) with an ohmmeter between the two points in question. Faulty IC socket such that the IC pin does not make good contact with the socket This type of circuit fault can often be detected by a careful visual inspection and then verified by disconnecting power from the circuit and checking for continuity (i. Shorted Signal Lines This type of fault has the same effect as an internal short between IC pins. It causes two signals to be exactly the same (signal contention). the LOW from Z1-6 is not reaching Z2-2. Some of the causes of open signal lines are: 1. A signal line may be shorted to ground or VCC rather 63 | P a g e . Clearly.. Some ICs are more tolerant of power supply variations and may operate properly. while others do not. 64 | P a g e .It is also a good idea to check them on an oscilloscope to verify that there is no significant amount of ac ripple on the dc levels and to verify that the voltage levels stay regulated during the system operation. and the ICs either will not operate or will operate erratically. or because the circuits that it is powering are drawing more current than the supply is designed for.than to another signal line. such as adjacent pins on a chip. They commonly occur between points that are very close together. In those cases. The copper between adjacent conducting paths on a printed circuit board is not completely etched away. This can happen if a chip or a component has a fault that causes it to draw much more current than normal. Sloppy wiring. The main causes for unexpected shorts between two points in a circuit are as follows: 1. and the output voltage can fall into the indeterminate range. Output Loading When a digital IC has its output connected to too many IC inputs. 2. These are splashes of solder that short two or more points together. An example of this is stripping too much insulation from ends of wires that are in close proximity. One of the most common signs of a faulty power supply is one or more chips operating erratically or not at all. the signal will be forced to the LOW or the HIGH state. and an ohmmeter check can verify that the two points in the circuit are shorted together.Again. its output current rating will be exceeded. You should always check the power and ground levels at each IC that appears to be operating incorrectly. Faulty Power Supply All digital systems have one or more dc power supplies that supply the VCC and VDD voltages required by the chips. a careful visual inspection can very often uncover this type of fault. It is good troubleshooting practice to check the voltage levels at each power supply in the system to see that they are within their specified ranges. 3. This effect is called loading the output signal (actually it’s overloading the output signal) and is usually the result of poor design or an incorrect connection. A power supply may go out of regulation because of a fault in its internal circuitry. A faulty power supply or one that is overloaded (supplying more than its rated amount of current) will provide poorly regulated supply voltages to the ICs. Solder bridges. Incomplete etching.