Barrel Shifter

www.btechzone.com ABSTRACT A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (MUX), and in such an implementation the output of one MUX is connected to the input of the next MUX in a way that depends on the shift distance. The number of multiplexers required for an n-bit word is n X log2(n). A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic. A barrel shifter, comprising: an n-bit by n-bit transistor array arranged into n rows and n columns, wherein the source of a transistor in one row is connected to the source of a transistor in the next row; a first plurality of multiplexors, each having a first and a second input and an output; a second plurality of multiplexors each having inputs and an output, each multiplexor selecting one of three inputs depending on the data length; and a third plurality of multiplexors, each having a first and a second input and an output, the output is coupled to one transistor in each row of the array beginning with a transistor in a corresponding bit position in the second row and continuing with transistors in ascending bit positions. HDL LANGUAGE SIMULATOR SYNTHESIS TOOL TARGET DEVICE FAMILY : VHDL : ISE SIMULATOR : XILINX 9.1i : FPGA : SPARTAN 3E www.btechzone.com Page 1 www.btechzone.com BLOCK DIAGRAM : data(16- bits) clk rst load_shift no. of bits to be shifted(16-bit) dataout(16bits) BARREL SHIFTER right/left/circular right/circular left shift Fig : Block Diagram of Barrel Shifter www.btechzone.com Page 2 www.btechzone.com LIST OF FIGURES: BLOCK DIAGRAM OF BARREL SHIFTER STRUCTURE OF ARRAY SHIFTER STRUCTURE OF LOG SHIFTER CLB LOCATION SPARTON-3E CLB RESOURCES BASYS PROGRAMMING CIRCUIT FLOWCHART STANDARD USB TYPE A/TYPE B CABLE SIMULATION RESULTS LEFT SHIFT RIGHT SHIFT CIRCULAR LEFT SHIFT CIRCULAR RIGHT SHIFT LOGICAL LEFT SHIFT LOGICAL RIGHT SHIFT LOGICAL CIRCULAR RIGHT SHIFT LOGICAL CIRCULAR LEFT SHIFT REGISTER TRANSFER LOGIC TECHNOLOGY SCHEMATIC DESIGN SUMMARY PIN ASSIGNMENT PIN ALLOCATION 2 6 7 24 24 26 30 38 42 43 43 44 44 45 45 46 47 48 48 49 49 www.btechzone.com Page 3 btechzone. the output of one MUX is connected to the input of the next MUX in a way that depends on the shift distance.btechzone. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits. Four common word sizes and the number of multiplexers needed are listed below: • • • • 64-bit — 64 * log2(64) = 64 * 6 = 384 32-bit — 32 * log2(32) = 32 * 5 = 160 16-bit — 16 * log2(16) = 16 * 4 = 64 8-bit — 8 * log2(8) = 8 * 3 = 24 Basically. each output can be connected to any input depending on the shift distance.a normal style for C programming code. It can be implemented as a sequence of multiplexers. In this implementation.com Page 4 . and is useful for most applications that shift data left or right .www. It is implemented like a {multiplexer}. such as Digital Signal Processing (DSP).com CHAPTER – 1 INTRODUCTION 1. for an n bit word. a barrel shifter works to shift data by incremental stages which avoids extra clocks to the register and reduces the time spent shifting or rotating data (the specified number of bits are moved/shifted/rotated the desired number of bit positions in a single clock cycle). The number of multiplexers required is n*log2(n). www.1 Introduction to barrel shifter A hardware device that can shift or rotate a data word by any number of bits in a single operation. A barrel shifter is commonly used in computer-intensive applications. With rotation. which has led most research to be directed toward speed optimizations.com Page 5 . and environment levels. architecture.www. however. With the advent of mobile computing.btechzone. Data shifting is required in many key computer operations from address decoding to computer arithmetic. while in shifting the empty space in the lower order bits after shifting is filled with zeros. In this project we present a range of 32-bit barrel shifters that vary at the gate. www.btechzone. Full barrel shifters are often on the critical path. power has become as important as speed for circuit designs.com Rotation (right) is similar to shifting in that it moves bits to the left. bits which "fall off" the left side get tacked back on the right side as lower order bits. com CHAPTER – 2 FUNCTION OF BARREL SHIFTER Each shifter will be designed as a 16-bit shifter that receives a 16-bit input data value along with a two’s compliment encoded shift value. www. and will produce a 16. 1) decodes the shift value into individual shift bit lines that mesh across all input data values. array shifter and logarithmic shifters. 2. so it is fast.1 Architecture There are two common architectural layouts for shifts. This section will describe the internal design characteristics for each shifter. Fig. a gate will either allow or not allow the input data value to pass to the output line. 1: Structure of an array shifter. The advantage of this design is that there is only ever one gate between the input data lines and the output data lines.www.com Page 6 . controlled by a shift bit line.bit shifted result. and the fact that each input data line sees a load from every shift bit line. An array shifter(Fig.btechzone. At each crossing point.btechzone. The disadvantages of this design are the requirement for a decoder. and the log shifter requires 2-to-1 muxes to propagate either a shifted or a non-shifted bit.two shift. the shifter is divided into loga(n) stages. and we will consider four types of mux www. The advantage of a log shifter is that it has small area and does not require a decoder. 2). but the disadvantage is that there are five levels of gates separating the input data from the output data. Each bit of the encoded shift value is sent to a different stage of the shifter. There are two types of gates that are required for these shifters: the array shifter requires switches that will either propagate or not propagate an input data bit. Five stages would be required when considering 32 bit data. and (2) a full transmission gate switch. The input data will be shifted or not shifted by each of the stages in sequence. powerof. where n is the input data length.com Page 7 . Each stage handles a single.com In a logarithmic shifter(Fig.btechzone. In this project we will consider two types of CMOS switches: (1) ntype pass transistor switch.www.btechzone. 1000.e left shifter and condition3 as 0001 i. Therefore the Dout=1100.com Page 8 .2 ARRAY SHIFT: An array shifter consists of four different shifts in each type of shift the data is shifted uniquely. The four types of array shifts are as follows • • • • Left shifting Right shifting Right Rotation Left Rotation 2.2 RIGHT SHIFTING: www. After the declaration of condition1 the desired shift is implemented by the next condition i. Now the 4 bit data present in din is shifted to its left by one bit continuously till all the 4 bits are shifted. (2) full transmission mux. depending on the direction and specification of the data to be shifted the shifts are titled. The dynamic gate design is the only type that requires a clock signal for a precharge stage. The static and dynamic gates are self buffering so no additional buffers are needed.btechzone.btechzone. Let us assume the condition2 as 00 i. If the condition 1 is high then the array shift is implemented for shifting the bits in the user specified data. Depending on the number of bits to be shifted specified in condition 3 the given data is shifted bit wise to left and zeros are appended in the other side. output data is 2.e a single bit shift in left direction.e condition2. 2. In this condition the user can specify one of the four types of shifts by passing binary digits specified. For example let us consider a 4 bit input data as Din= 0110. In the enclosed vhdl code for barrel shifter condition 1 specifies whether the shift desired is an array shift or logical shift. The number of bits to be shifted is intialized by the condition3.0000. but will require occasional buffering to strengthen the signals in the log shifters.www.com designs: (1) n-type pass transistor mux. The pass transistor and transmission gates are simple and fast. (3) a static CMOS mux. and (4) a dynamic logic mux.2.1 LEFT SHIFTING: In the left shifting the given 16 bit data is shifted bit wise in left side. but contain more transistors. Figure 3 shows schematics for each gate design.2. Now the 4 bit data present in din is shifted to its right by one bit continuously till all the 4 bits are shifted. For example let us consider a 4 bit input data as Din= 0110. Therefore the Dout=0011.com Page 9 .e a single bit shift . Depending on the number of bits to be shifted specified in condition 3 the given data is shifted bit wise to right and zeros are appended in the other side. Let us assume the condition2 as 10 i.1100 output data is 2.www. The addition of one to Rotateleft can be accomplished in two ways: (1) include a 5 bit incrementor. Now the 4 bit data present in din is shifted to its right by one bit continuously till all the 4 bits are shifted. This mux allows either the rotation wrap-around bit. The inversion of the Rotateleft bits can be accomplished by adding muxes that pass either the shift bit or its inverse. We consider three options: (1) a wrap around least significant bit for right rotation.e right shifter and condition3 as 0001 i.2. www.1001. (2) a sign bit for arithmetic right shifting.com In the right shifting the given 4 bit data is shifted bit wise in right side.4 LEFT ROTATION: Left rotations can be accomplished by rotating right 32 . Let us assume the condition2 as 01 i. which requires inverting all the Rotateleft bits and adding one.btechzone.3 RIGHT ROTATION: Right rotation is similar to right shifting. The number of bits to be shifted is intialized by the condition3. and (3) GND for signed magnitude right shifting. For example let us consider a 4 bit input data as Din= 0110.e a single bit shift in right direction.2.0001. Therefore the Dout=0011. except that additional hardware is required to determine which values get shifted into the upper bits of the output. the sign bit. or (2) add an additional one-bit shift stage.e right rotation and condition3 as 0001 i.ht can be calculated by taking the two's-compliment of the Rotateleft value.Rotatereft bits.btechzone. A 3-to-1 control mux was added to each wrap around bit line.0000 output data is 2. Rotate. or GND to be selected.i. e. left rotation and condition3 as 0001 i. For example let us consider a 4 bit input data as Din= 0110.www.3….1. If the condition 1 is low then the logical shift is implemented for shifting the bits in the user specified data. A second method is to initially reverse the input data bits and perform a right shift of length Shiftleft.0110. After the declaration of condition1 the desired shift is implemented by the next condition i. 2. The number of bits to be shifted is not user defined. Now the 4 bit data present in din is shifted to its left by one bit continuously till all the 4 bits are shifted.0011.3.btechzone.e a single bit shift .com Page 10 .1 LOGICAL LEFT SHIFTING: In the logical left shifting the given 16 bit data is shifted bit wise in left side. For example let us consider a 4 bit input data as Din= www.S h i f t l e f t bits. and including an additional row of pull down gates that mask out the lower n bits of the n bit left shift.2. Let us assume the condition2 as 11 i. In the logical shift 2n bits are sifted at a time where n=0. In this condition the user can specify one of the four types of shifts by passing binary digits specified.btechzone.1001.com Left shifting can be performed by right shifting 16 .3 LOGICAL SHIFT: A logical shifter consists of four different shifts in each type of shift the data is shifted uniquely.e condition2. The four types of a logical shifts are as follows • • • • Logical Left shifting Logical Right shifting Logical Right Rotation Logical Left Rotation 2. depending on the direction and specification of the data to be shifted the shifts are titled. Therefore the output data is Dout=1100. When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 and zeros are appended in the other side. and finally reverse the output bits. In the enclosed vhdl code for barrel shifter condition 1 specifies whether the shift desired is an a logical shift or array shift. The condition3 is not significant for logical shift. 2. For example let us consider a 4 bit input data as Din= 0110. The number of bits to be shifted is not user defined. In the logical shift 2n bits are shifted at a time where n=0.2 LOGICAL RIGHT SHIFTING: In the logical right shifting the given 16 bit data is shifted bit wise in right side.com 0110.btechzone. Now the 4 bit data present in din is shifted to its right by one bit initially and goes on till all the 4 bits are shifted. The number of bits to be shifted is not user defined.4 LOGICAL LEFT ROTATION: In the logical left rotation the given 16 bit data is shifted bit wise in left side.1. Now the 4 bit data present in din is shifted to its right by one bit initially and goes on till all the 4 bits are shifted.btechzone.3 LOGICAL RIGHT ROTATION: In the logical right rotation the given 16 bit data is shifted bit wise in right side. Therefore the output data is Dout= 1100.com Page 11 . Let us assume the condition2 as 10 i.2.3.1. In the logical shift 2n bits are shifted at a time where n=0. 2. www. 2. 2.3.0000.3…. instead of zeros getting appended the most significant bits are shifted to least significant bit positions.www. The condition3 is not significant for logical shift.2. The number of bits to be shifted is not user defined. Let us assume the condition2 as 01 i.3…. In the logical shift 2n bits are shifted at a time where n=0.e logical right shifter . For example let us consider a 4 bit input data as Din= 0110. The condition3 is not significant for logical shift.1100. Now the 4 bit data present in din is shifted to its left by one bit initially and goes on till all the 4 bits are shifted.1.e logical right rotation . When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 . When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 . Therefore the output data is Dout= 0011.3. The condition3 is not significant for logical shift.3…. When the value of n=0 the number of shifts is a single bit shift and when n=2 the number of shifts is 4 and zeros are appended in the other side. Therefore the output data is Dout= 0011.e logical left shifter . Let us assume the condition2 as 00 i.0000. www. Therefore the output data is Dout= 0011. Let us assume the condition2 as 11 i. For example let us consider a 4 bit input data as Din= 0110.com instead of zeros getting appended the most significant bits are shifted to least significant bit positions.e logical left rotation . Now the 4 bit data present in din is shifted to its left by one bit initially and goes on till all the 4 bits are shifted.com Page 12 .btechzone.www.1100.btechzone. To create a new project: 1. www. Select File New Project.com Page 13 .1i provides Xilinx PLD designers with the basic design process using ISE 9...1 Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board.1i. The New Project Wizard appears.www.1i and SPARTAN 3E FPGA KIT The ISE 9. This chapter contains the following sections: • • • • • • • “Create a New Project” “Create an HDL Source” “Design Simulation” “Create Timing Constraints” “Implement Design and Verify Constraints” “Reimplement Design and Verify Pin Locations” “Download Design to the Spartan™-3E Demo Board” 3.com CHAPTER – 3 AN INTRODUCTION TO XILINX 9.btechzone. Type tutorial in the Project Name field.btechzone. 2. Verify that HDL is selected from the Top-Level Source Type list.www. 5.com Page 14 .com 3. When the table is complete.btechzone. Enter or browse to a location (directory path) for the new project. 4. Click Next to move to the device properties page 6. Fill in the properties in the table as shown below: • • • • • • • • • • Product Category: All Family: Spartan3E Device: XC3S250E Package: TQ144 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL (or Verilog) Verify that Enable Enhanced Design Summary is selected. A tutorial subdirectory is created automatically.btechzone. your project properties will look like the following: www. Leave the default values in the remaining fields. 3. 3. your new project will be complete.com Page 15 . you will create the top-level HDL file for your design. Verify that the Add to project checkbox is selected. Select VHDL Module as the source type. Creating a VHDL Source Create a VHDL source file for the project as follows: 1. Click Next. Click Next to proceed to the Create New Source window in the New Project Wizard. Click the New Source button in the New Project Wizard. or skip to the “Creating a Verilog Source” section. www.btechzone. 4. continue either to the “Creating a VHDL Source” section below. 2. Determine the language that you wish to use for the tutorial. Then. Type in the file name counter.www. At the end of the next section.2 Create an HDL Source In this section. 5.btechzone.com 7. Create a new test bench source by selecting Project New Source. The source file containing the entity/architecture pair displays in the Workspace. Create the test bench waveform as follows: 1. The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. then Finish in the New Source Wizard .btechzone. 4.btechzone. Click Next. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. The requirements for this design are the following: • • • The counter must operate correctly with an input clock frequency = 25 MHz. Declare the ports for the counter design by filling in the port information. 3. 2. setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens.com 6. In the New Source Wizard.www. Click Finish. and the counter displays in the Source tab. type and name. 7. 6. The Summary page shows that the source will be added to the project.Summary dialog box to complete the new source file template. 8.com . 5. then Next.3 Design Simulation Verifying Functionality using Behavioral Simulation Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. Select the counter HDL file in the Sources window. as shown below: 3. select Test Bench WaveForm as the source type. and type counter_tbw in the File Name field. The test bench waveform is a graphical view of a test bench. The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. Page 16 www. and it displays the source directory. Click Next. Click Next. 7. then Finish. You need to set the clock frequency. www. 9. select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project. Clock Low Time: 20 ns. Offset: 0 ns. 8. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Toggle the DIRECTION port to define the input stimulus for the counter design as follows: • • Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. Leave the default values in the remaining fields. Click Finish to complete the timing initialization. In the Sources window. 10.btechzone. 100 ns.com The design requirements correspond with the values below. Note: When GSR(FPGA) is enabled. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. 11. Save the waveform. you can use the Zoom In and Zoom Out toolbar buttons. Note: For more accurate alignment.www.btechzone. Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the counter will count down. Global Signals: GSR (FPGA) Initial Length of Test Bench: 1500 ns.com Page 17 . is added to the Offset value automatically. Fill in the fields in the Initialize Timing dialog box with the following information: • • • • • • • Clock High Time: 20 ns. com 12. The simulation waveform results will look like the following: Note: You can ignore any rows that start with TX. “You have an active simulation open. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window. To view your simulation results.www. In the Processes tab. The timing is specified by entering constraints that guide the placement and routing of the design. Verify that the counter is counting up and down as expected.4 Simulating Design Functionality Verify that the counter design functions as you expect by performing behavior simulation as follows: 1. 5. 3. If you are prompted with the following message. click the “+” to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process. click Yes to continue. You have now completed simulation of your design using the ISE Simulator.5 Create Timing Constraints Specify the timing between the FPGA and its surrounding logic as well as the frequency the design must operate at internal to the FPGA. select the Simulation tab and zoom in on the transitions. Are you sure you want to close it?“. It is recommended that you enter global constraints. 3.btechzone. The clock period constraint specifies the clock frequency at which www.btechzone. Close the test bench waveform. Close the simulation view.com Page 18 . 3. 2. 4. The ISE Simulator opens and runs the simulation to the end of the test bench. 6 Implement Design and Verify Constraints Implement the design and verify that it meets the timing constraints specified in the previous section.btechzone. 2.1 Entering Timing Constraints To constrain the design do the following: 1. The counter.ISE runs the Synthesis and Translate steps and automatically creates a User Constraints File (UCF). 4.btechzone. In the next step.www. Click Yes to add the UCF file to your project.com your design must operate inside the FPGA. Note: You can also create a UCF file for your project by selecting Project Create New Source. 5. Select CLOCK in the Clock Net Name field. 3. Select Synthesis/Implementation from the drop-down list in the Sources window. then select the Period toolbar button or double-click the empty Period field to display the Clock Period dialog box. 3.com Page 19 . 6. enter values in the fields associated with CLOCK in the Constraints Editor Global tab.ucf file is added to your project and is visible in the Sources window. Click the “+” sign next to the User Constraints processes group. and double-click the Create Timing Constraints process.5. Select the counter HDL source file. The offset constraints specify when to expect valid data at the FPGA inputs and when valid data will be available at the FPGA outputs. 3. The Xilinx constraints Editor opens automatically. Enter 40 ns in the Time field. www. To constrain the design ports to package pins. 3. Notice that after Implementation is complete. 3. Double-click the Implement Design process in the Processes tab. 4. Select the Package View tab.btechzone. 2.com Implementing the Design 1. Verify that counter is selected in the Sources window. 5. Locate the Performance Summary table near the bottom of the design Summary.www.btechzone.com Page 20 . In the Design Object List window. 2. Click the All Constraints Met link in the Timing Constraints field to view the Timing Constraints report. 4. Select the counter source file in the Sources window. 6. Open the Design Summary by double-clicking the View Design Summary process In the Processes tab. do the following: 1. enter a pin location for each pin in the Loc column using the following information: • • • • • CLOCK input port connects to FPGA pin T9 (GCK0 signal on board) COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board) COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board) COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board) COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board) www. Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3 Startup Kit demo board. Verify that the design meets the specified timing requirements. Double-click the Assign Package Pins process found in the User constraints process group. The Xilinx Pinout and Area Constraints Editor (PACE) opens. the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings. Connect the 5V DC power cable to the power input on the demo board (J4). indicating they are out-of-date with one or more of the design files.www.com Page 21 . www.btechzone. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select File Save. 3. Select XST Default <> and click OK.com • DIRECTION input port connects to FPGA pin K13 (SW7 signal on board) Notice that the assigned pin locations are shown in blue: 5. Notice that the Implement Design processes have an orange question mark next to them. This is because the UCF file has been modified. 6. 1. This section provides simple instructions for downloading the counter design to the Spartan-3E Starter Kit demo board.7 Download Design to the Spartan™-3E Demo Board This is the last step in the design verification process. Close PACE.btechzone. 17. LEDs 0. click the “+” sign to expand the Generate Programming File processes. 11. 15. click OK. To assign a configuration file to the xc3s200 device in the JTAG chain. The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window. The Assign New Configuration File dialog box appears. The Xilinx WebTalk Dialog box may open during this process. Connect the download cable between the PC and demo board (J7).com 2. Click OK to program the device.btechzone. click OK to continue. select Configure devices using Boundary-Scan (JTAG). 4. Select Bypass to skip any remaining devices. 18. Click Finish. Select Disable the collection of device usage statistics for this project only and click OK..www. and select Program. 13. Select Synthesis/Implementation from the drop-down list in the Sources window. 10.. 1. 6. Click Decline. 8. In the Processes window. On the board. 3. 12. If you get a message saying that there are two devices found. 14. www. Select counter in the Sources window. Close iMPACT without saving. When programming is complete. 7. If you get a Warning message. iMPACT opens and the Configure Devices dialog box is displayed.btechzone. bit file and click Open. Double-click the Configure Device (iMPACT) process. indicating that the counter is running.com Page 22 . the Program Succeeded message is displayed. 16. Right-click on the xc3s200 device image. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. In the Welcome dialog box. 9. 2. and 3 are lit. 5. The Programming Properties dialog box opens. select the counter. com 3.btechzone.8 Introduction to FPGA: As described in Architectural Overview.www. and each slice contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage elements that can be used as flip-flops or latches.btechzone.com Page 23 . The LUTs can be used as a 16x1 memory (RAM16) or as a 16-bit shift register (SRL16). and additional www.8. the Spartan™-3E FPGA architecture consists of five fundamental functional elements: • Input/output Blocks (IOBs) • Configurable Logic Block (CLB) • Block RAM • Dedicated Multipliers • Digital Clock Managers (DCMs) 3.1 Input/output Blocks (IOBs) The Input/Output Block (IOB) provides a programmable.2 Configurable Logic Block (CLB) The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits.8. unidirectional or bidirectional interface between a package pin and the FPGA’s internal logic. Each CLB contains four slices. The IOB is similar to that of the Spartan-3 family with the following differences: • Input-only blocks are added • Programmable input delays are added to all blocks • DDR flip-flops can be shared between adjacent IOBs 3. Each density varies by the number of rows and columns of CLBs. CLB Array The CLBs are arranged in a regular array of rows and columns as shown in Figure 14.www.com multiplexers and carry logic simplify wide logic and arithmetic functions.com Page 24 .btechzone. Fig 3 CLB Locations www.btechzone. Each CLB is identical. Most generalpurpose logic in a design is automatically mapped to the slice resources in the CLBs. and the Spartan-3E family CLB structure is identical to that for the Spartan-3E family. interconnect resources are identical to that of the Spartan-3 architecture.8. such as IOBs. and direct lines. Functionally. The Xilinx Place and Route (PAR) software exploits the rich interconnect array to deliver optimal system performance and the fastest compile times.8. and block RAM. Spartan-3E CLB Resources 3. CLBs. hex lines.btechzone. double lines.com Page 25 .4 Overview Interconnect.btechzone. 3. also called routing.com Table 1. www. is segmented for optimal connectivity. There are four kinds of interconnects: long lines.www.3 Interconnect Interconnect is the programmable network of signal pathways between the inputs and outputs of functional elements within the FPGA. DCMs. 9 Introduction to Spartan 3E FPGA: The Basys board is a circuit design and implementation platform that anyone can use to gain experience building real digital circuits.com Page 26 . A large collection of on-board I/O devices and all required FPGA support circuits are included. ready-to-use hardware suitable for hosting circuits ranging from basic logic devices to complex controllers.btechzone. and Block RAM/Multiplier) 3.www. so countless designs can be created without the need for any other components. DCMs. Built around a Xilinx Spartan-3E Field Programmable Gate Array and a Cypress EZUSB controller.btechzone.Four Types of Interconnect Tiles (CLBs.com Fig4. www. the Basys board provides complete. IOBs. 9. Basys programming circuit locations 3.www. To use USB power.com Four standard expansion connectors allow designs to grow beyond the Basys board using breadboards. Signals on the 6-pin connectors are protected against ESD damage and short-circuits. 100-mil spaced battery connector (four AA cells in series www. sensor inputs.btechzone. and many other features).com Page 27 .1 Board Power The Basys board is typically powered from a USB cable.1/5. ensuring a long operating life in any environment. To use battery power. The Basys board works seamlessly with all versions of the Xilinx ISE tools.btechzone. so no other power supplies or programming cables are required Figure 5. set the power source switch (SW8) to USB and attach the USB cable. set SW8 to EXT and attach a 4V9V battery pack to the 2-pin. user-designed circuit boards. or Pmods (Pmods are inexpensive analog and digital I/O modules that offer A/D & D/A conversion. including the free WebPack. It ships with a USB cable that provides power and a programming interface. 2. motor drivers.5mm power jack. set SW8 to EXT and attach a 5VDC to 9VDC supply to the centerpositive. To use an external wallplug power supply. but a power jack and battery connector are also provided so that external supplies can be used. com make a good 6+/. Total board current is dependent on FPGA configuration.volt supply). The free ISE/WebPack CAD software from Xilinx can be used to create bit files from VHDL. and external connections.3V supply for the board.btechzone.9. Verilog. The Platform Flash ROM will retain a bit file until it is reprogrammed.com Page 28 .pin expansion connectors and to a National Semiconductor LP8345 voltage regulator. and it also drives secondary regulators to produce the 2. SW8 can also be used to turn off main power by setting it to the unused power input (e. The LP8345 produces the main 3. Once programmed. and 50mA from the 3. The FPGA will remain configured until it is reset by a power-cycle event or by the FPGA reset button (BTNR) being pressed..g.2V supply.2V supply voltages required by the FPGA. Adept can also program a bit file into an on-board non-volatile ROM called “Platform Flash”.5V supply.www. about 100mA of current is drawn from the 1. clock frequency. the Platform Flash can automatically transfer a stored bit file to the FPGA at a subsequent power-on or reset event if the Mode Jumper is set to ROM. Input power is routed through the power switch (SW8) to the four 6. Required current will increase if larger circuits are configured in the FPGA. 50mA from the 2. regardless of power-cycle events. and all LEDs illuminated. www.5V and 1. During configuration. Digilent’s PC-based program called Adept can be used to configure the FPGA with any suitable bit file stored on the computer. if USB power is used. the FPGA on the Basys board must be configured before it can perform any useful functions.btechzone. In test circuits with roughly 20K gates routed.2 Configuration After power-on. Adept uses the USB cable to transfer a selected bit file from the PC to the FPGA (via the FPGA’s JTAG programming port). or if peripheral boards are attached. a “bit” file is transferred into memory cells within the FPGA to define the logical functions and circuit interconnects. Voltages higher than 9V on either power connector may cause permanent damage. a 50MHz clock source. setting SW8 to EXT will shut off board power without unplugging the USB cable). 3.3V supply. or schematic-based source files. www. Pushbuttons and slide switches all have series resistors for protection against short circuits (a short circuit would occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). 3.com To program the Basys board.mcs file with the Platform Flash ROM. The “configuration done” LED (LD_D) will also illuminate after the FPGA has been successfully configured. Right-click on the device to be programmed. and the software will indicate whether programming was successful. and select the “program” function. and a tenth LED (LD-D) illuminates any time the FPGA has been successfully programmed.www. so they will illuminate when a logic ‘1’ is written to the corresponding FPGA pin. and/or the desired . A ninth LED is provided as a power-indicator LED.bit file with the FPGA. Use the browse function to associate the desired . Start the Adept software. 50MHz. The configuration file will be sent to the FPGA or Platform Flash. and wait for the FPGA and the Platform Flash ROM to be recognized. or 100MHz based on the position of the clock select jumper at JP4.com Page 29 . attach the USB cable to the board.9. Eight LEDs and a four-digit seven segment LED display are provided for circuit outputs.3 Oscillators The Basys board includes a primary.9. user settable silicon oscillator that produces 25MHz.btechzone. The primary and secondary oscillators are connected to global clock input pins at pin 54 and pin 53 respectively 3. A socket for a second oscillator is provided at IC7 (the IC7 socket can accommodate any 3.3V CMOS oscillator in a half-size DIP package). Slide switches generate constant high or low inputs depending on position. Pushbutton inputs are normally low and driven high only when the pushbutton is pressed.4 User I/O Four pushbuttons and eight slide switches are provided for circuit inputs. LED anodes are driven from the FPGA via current-limiting resistors.btechzone. 3V operation.btechzone. For 3. Most PS/2 devices can operate from a 3.5 PS/2 Port The 6-pin mini-DIN connector can accommodate a PS/2 mouse or keyboard. For 5V.3V. The timings define signal requirements for mouseto-host communications and bi-directional keyboard communications. but the data packets are organized differently. set JP1 to VU and ensure that Basys is powered with a 5VDC wall plug supply.3V supply. For 3. stop and odd parity bit.3V.1 FLOW CHART: Start Specifications Of Barrel Shifter Analysis VHDL Design of Barrel Shifter www. set the jumper to 3.9. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface.btechzone. CHAPTER – 4 IMPLEMENTATION 4. any board power supply (including USB) can be used.3V or VU is supplied to the PS/2 connector. Both the mouse and keyboard use a two-wire serial bus (clock and data) to communicate with a host device.www. but some older devices may require a 5VDC supply. and otherwise they are held in the “idle” state at logic ‘1’. and the keyboard interface allows bi-directional data transfers The clock and data signals are only driven when data transfers occur.com Functional Simulation Page 30 . A jumper on the Basys board (JP1) selects whether 3.com 3. Both use 11-bit words that include a start. ALL. Placement & Routing Bit file Dumping on Spartan 3E FPGA 4.STD_LOGIC_ARITH.VComponents. www.STD_LOGIC_UNSIGNED.any Xilinx primitives in this code.ALL. --library UNISIM. use IEEE. use IEEE.btechzone. use IEEE. --use UNISIM.com Page 31 .www.2 VHDL CODE FOR BARREL SHIFTER: library IEEE. ---.com YES Error ? Synthesis Floor Planning.ALL.Uncomment the following library declaration if instantiating ---. entity barrel_shft is Port ( clk : in STD_LOGIC.btechzone.STD_LOGIC_1164.all. www. begin process(rst. cond3 : in STD_LOGIC_VECTOR (3 downto 0).www.com rst : in STD_LOGIC.btechzone.btechzone. cond1 : in STD_LOGIC. cond2 : in STD_LOGIC_VECTOR (1 downto 0). elsif(clk'event and clk='1') then if(cond1='1') then case cond2 is when "00" => case cond3 is when "0000" => i<=i. signal sclk: std_logic:='0'. dout : out STD_LOGIC_VECTOR (15 downto 0)). signal cnt:std_logic_vector(2 downto 0):="000". signal logical:std_logic_vector(3 downto 0). signal din : STD_LOGIC_VECTOR (15 downto 0):="0011001111001100".clk) begin if(rst='1') then i<=din. architecture Behavioral of barrel_shft is signal i: std_logic_vector(15 downto 0). when "0001" => i<=i(14 downto 0)& '0'. --din : in STD_LOGIC_VECTOR (15 downto 0). end barrel_shft.com Page 32 . when "0011" => i<="000" & i(15 downto 3). when "1001" => i<=i(6 downto 0) & "000000000". end case. when "1100" => i<=i(3 downto 0) & "000000000000". when "1111" => i<=i(0) when others => i<=i. when "0101" => i<=i(10 downto 0) & "00000". when "0011" => i<=i(12 downto 0) & "000".com when "0010" => i<=i(13 downto 0) & "00". & "000000000000000". when "1101" => i<=i(2 downto 0) & "0000000000000". when "0110" => i<=i(9 downto 0) & "000000". when "0111" => i<="0000000" & i(15 downto 7) . when "1110" => i<=i(1 downto 0) & "00000000000000". www. when "0101" => i<="00000" & i(15 downto 5) . when "0110" => i<="000000" & i(15 downto 6) . when "0001" => i<= '0' & i(15 downto 1). when "0100" => i<="0000" & i(15 downto 4) . when "1011" => i<=i(4 downto 0) & "00000000000". when "0010" => i<= "00" & i(15 downto 2). when "01" => case cond3 is when "0000" => i<=i.btechzone.com Page 33 . when "0100" => i<=i(11 downto 0) & "0000". when "1010" => i<=i(5 downto 0) & "0000000000". when "1000" => i<=i(7 downto 0) & "00000000". when "1001" => i<="000000000" & i(15 downto 9) .www.btechzone. when "0111" => i<=i(8 downto 0) & "0000000". when "1000" => i<="00000000" & i(15 downto 8) . when "1110" => i<=i(1 downto 0) & i(15 downto 2). when "0111" => i<=i(8 downto 0) & i(15 downto 9).www. when "0011" => i<=i(12 downto 0) & i(15 downto 13). when "1100" => i<=i(3 downto 0) & i(15 downto 4). when "0010" => i<=i(13 downto 0) & i(15 downto 14). when "0110" => i<=i(9 downto 0) & i(15 downto 10). when "1101" => i<=i(2 downto 0) & i(15 downto 3).com when "1010" => i<="0000000000" & i(15 downto 10). when "0101" => i<=i(10 downto 0) & i(15 downto 11). when "1011" => i<="00000000000" & i(15 downto 11). when "1000" => i<=i(7 downto 0) & i(15 downto 8). when "1001" => i<=i(6 downto 0) & i(15 downto 7).btechzone. when "0001" => i<=i(14 downto 0)& i(15). when "0100" => i<=i(11 downto 0) & i(15 downto 12). . www.btechzone. when "1100" => i<="000000000000" & i(15 downto 12) . when "1110" => i<="00000000000000" & i(15 downto 14) . when "10" => case cond3 is when "0000" => i<=i. end case. when "1011" => i<=i(4 downto 0) & i(15 downto 5). when "1101" => i<="0000000000000" & i(15 downto 13) .com Page 34 . when "1111" => i<="000000000000000" &i(15) when others => i<=i. when "1010" => i<=i(5 downto 0) & i(15 downto 6). & i(15 downto 1). when "1111" => i<=i(0) when others => i<=i. end case. when "1110" => i<=i(13 downto 0) & i(15 downto 14). when "0101" => i<=i(4 downto 0) & i(15 downto 5). when "1101" => i<=i(12 downto 0) & i(15 downto 13). when "1111" => i<=i(14 downto 0) & i(15). when "0110" => i<=i(5 downto 0) & i(15 downto 6). when "1010" => i<=i(9 downto 0) & i(15 downto 10).btechzone.com when "11" => case cond3 is when "0000" => i<=i. when "1000" => i<=i(7 downto 0) & i(15 downto 8).www. when "0010" => i<=i(1 downto 0) & i(15 downto 2). end case. when "0100" => i<=i(3 downto 0) & i(15 downto 4). when "0111" => i<=i(6 downto 0) & i(15 downto 7). when "0011" => i<=i(2 downto 0) & i(15 downto 3). elsif(cond1='0') then cnt<=cnt+"001".com Page 35 . when "0001" => i<=i(0)& i(15 downto 1). when "1100" => i<=i(11 downto 0) & i(15 downto 12).btechzone. end case. when "1001" => i<=i(8 downto 0) & i(15 downto 9). when others => i<= i. when others => i<=i. when "1011" => i<=i(10 downto 0) & i(15 downto 11). case cnt is www. www. when "0100" => i<="0000" & i(15 downto 4) . when "01" => case logical is when "0000" => i<=i. end case. when "011"=> logical <="0100". end case.com when "000" => logical<="0000".btechzone. when others => i<=i.com Page 36 . when "0010" => i<= "00" & i(15 downto 2). case cond2 is when "00" => case logical is when "0000" => i<=i. when "0010" => i<=i(13 downto 0) & "00". when "0100" => i<=i(11 downto 0) & "0000". end case. when "001" => logical <="0001". when"010" => logical <="0010". when "1000" => i<=i(7 downto 0) & "00000000". when "1000" => i<="00000000" & i(15 downto 8) .www. when "100"=> logical <="1000". when "0001" => i<=i(14 downto 0)& '0'. when "0001" => i<= '0' & i(15 downto 1). when others => logical<="0000".btechzone. when others => i<=i. when "0001" => i<=i(0)& i(15 downto 1). when "1000" => i<=i(7 downto 0) & i(15 downto 8). end case. when "0010" => i<=i(1 downto 0) & i(15 downto 2). when "0100" => i<=i(11 downto 0) & i(15 downto 12).com Page 37 . when "11" => case logical is when "0000" => i<=i. end case. when "1000" => i<=i(7 downto 0) & i(15 downto 8). when "0001" => i<=i(14 downto 0)& i(15). when "0010" => i<=i(13 downto 0) & i(15 downto 14). end case. when others => i<=i.com when "10" => case logical is when "0000" => i<=i. when others => i<= i. when others => i<=i.www. when "0100" => i<=i(3 downto 0) & i(15 downto 4). if(cnt="100")then www.btechzone.btechzone. process(clk) variable cnt:integer:=0. dout<=i. cnt:=0.com Page 38 .btechzone. end if. end process. end Behavioral. 4. end if. So the FPGA is programmed through this cable.com cnt<="000". end if.3 Dumping Procedure Programming through JTAG For programming the FPGA we need a JTAG cable which is a 6 pin cable converted to a parallel port cable connected to CPU. end if. And this type of programming is called “flash programming”. if(cnt=25000000)then sclk<=not sclk. end process.www. end if. www.btechzone. begin if(clk'event and clk='1') then cnt:=cnt +1. www.btechzone. Standard USB Type A/Type B Cable The wider and narrower Type A connector fits the USB connector at the back of the computer. The actual cable colour might vary from the picture. When the board is powered on. indicating a good connection. the Windows operating system should recognize and install the associated driver software. When the USB cable driver is successfully installed and the board is correctly connected to the PC. as shown in Figure20.btechzone. connect the USB cable to the starter kit board and apply power to the board. Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software. as shown in Figure 19 . double-click Configure Device (iMPACT) from within Project Navigator.com Connecting the USB Cable The kit includes a standard USB Type A/Type B cable. connect the square Type B connector to the Spartan-3E Starter Kit board.com Page 39 . The USB connector is on the left side of the board. After installing the Xilinx software. similar to the one shown in Figure . the design can be downloaded using the iMPACT programming software and the USB cable. Then. a green LED lights up. To begin programming. www. immediately next to the Ethernet connector. If not already prompted.btechzone. Right-click the FPGA and select Assign New Configuration File. iMPACT issues the warning message shown in Figure 22. the iMPACT programming software automatically recognizes the three devices in the JTAG programming file. Right-Click to Assign a Configuration File to the Spartan-3E FPGA If the original FPGA configuration file used the default StartUp clock source.com Page 40 . Select the desired FPGA configuration file and click OK.btechzone. to highlight it. This message can be safely www. the Spartan-3E FPGA. as shown in Figure 21.com Double-Click to Invoke iMPACT If the board is connected properly.www. CCLK. click the first device in the chain. btechzone. right-click the FPGA and select Program. The iMPACT software reports status during programming process.btechzone. When downloading via JTAG. the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source.com Page 41 . iMPACT Issues a Warning if the StartUp Clock Was Not CCLK To start programming the FPGA.com ignored. Direct programming to the FPGA takes a few seconds to less than a minute. depending on the speed of the PC’s USB port and the iMPACT settings. Figure 23: Right-Click to Program the Spartan-3E FPGA www.www. as shown in Figure 24 The FPGA application is now executing on the board and the DONE pin LED (see Figure 17) lights up.com Page 42 . iMPACT Programming Succeeded.btechzone.www. the FPGA’s DONE Pin is High CHAPTER – 5 RESULTS 5.com When the FPGA successfully programs. the iMPACT software indicates success.1 SIMULATION RESULTS FOR ARRAY SHIFT www.btechzone. btechzone.com Page 43 .com Fig .1: simulation result for left shift www.btechzone.www. btechzone.www.2: Simulation results for right shift Fig3: Simulation results for circular left shift www.com Page 44 .btechzone.com Fig. btechzone.com Fig4: simulation results for circular right shift 5.2 SIMULATION RESULTS FOR LOGICAL SHIFT Fig6: logical left shift www.www.com Page 45 .btechzone. www.com Fig7: logical right shift Fig8: logical circular right shift www.btechzone.btechzone.com Page 46 . btechzone.www.com Page 47 .com Fig9: logical circular left shift www.btechzone. com 5.btechzone.www.btechzone.com Page 48 .3 REGISTER TRANSFER LOGIC FOR BARREL SHIFTER: www. btechzone.btechzone.com Page 49 .www.com Fig 10: Register Transfer Logic for Barrel shifter Fig11:technology schematic for barrel shifter Fig 12: Design summary for Barrel shifter www. www.btechzone.com Page 50 .com Fig 13: Pin assignment for barrel shifter Fig 14: Pin allocation www.btechzone. prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.00 s --> Reading design: barrel_shft.com 5.xst J.4.00 / 0.1 SYNTHESIS REPORT: Release 9.3) TIMING REPORT www. --> Parameter TMPDIR set to .btechzone.1) Device utilization summary 9.00 / 1. All rights reserved.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9. Inc.16 s | Elapsed : 0.btechzone.36 Copyright (c) 1995-2007 Xilinx.00 s --> Parameter xsthdpdir set to .www.4 REPORTS 5.tmp CPU : 0.2) Partition Resource Summary 9.00 / 0.16 s | Elapsed : 0./xst/projnav.com Page 51 .1) HDL Synthesis Report 6) Advanced HDL Synthesis 6./xst CPU : 0.00 / 1.2i . com .www.prj" : mixed Synthesis Options Summary * ================================================================= Ignore Synthesis Constraint File : NO ---.Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm Safe Implementation FSM Style RAM Extraction RAM Style ROM Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing : lut : Yes : Auto : Yes : Auto : YES : YES : YES : YES : YES Page 52 : barrel_shft : YES : Auto : No : "barrel_shft" : NGC : xc3s250e-4-tq144 www.com ================================================================= ======== * ======== ---.Source Parameters Input File Name Input Format : "barrel_shft.btechzone.Target Parameters Output File Name Output Format Target Device ---.btechzone. www.Target Options Add IO Buffers Global Maximum Fanout Register Duplication Slice Packing Use Clock Enable Use Synchronous Set Use Synchronous Reset Pack IO Registers into IOBs Equivalent register Removal ---.btechzone.lso : NO : Yes : AllClockNets : YES : NO : NO www.com ROM Style Mux Extraction Resource Sharing Multiplier Style : Auto : YES : YES : NO : No : auto Asynchronous To Synchronous Automatic Register Balancing ---.com Page 53 .btechzone.General Options Optimization Goal Optimization Effort Library Search Order Keep Hierarchy RTL Output Global Optimization Read Cores Write Timing Constraints Cross Clock Analysis Hierarchy Separator :/ : YES : 500 : 24 : YES : YES : Yes : Yes : Yes : auto : YES Add Generic Clock Buffer(BUFG) Optimize Instantiated Primitives : NO : Speed :1 : barrel_shft. com .vhd" in Library work. Design Hierarchy Analysis * ================================================================= HDL Compilation * ================================================================= ================================================================= ======== * HDL Analysis * Page 54 www.btechzone.btechzone. Architecture behavioral of Entity barrel_shft is up to date.www.com Bus Delimiter Case Specifier Slice Utilization Ratio BRAM Utilization Ratio Verilog 2001 Auto BRAM Packing Slice Utilization Ratio Delta : <> : maintain : 100 : 100 : YES : NO :5 ================================================================= ======== ================================================================= ======== * ======== Compiling vhdl file "D:/Xilinx/a/barrel_shft. ================================================================= ======== * ======== Analyzing hierarchy for entity <barrel_shft> in library <work> (architecture <behavioral>). "D:/Xilinx/a/barrel_shft."D:/Xilinx/a/barrel_shft."D:/Xilinx/a/barrel_shft.vhd" line 143: Mux is complete : default of case is discarded INFO:Xst:1561 .vhd" line 99: Mux is complete : default of case is discarded INFO:Xst:1561 .vhd" line 76: Mux is complete : default of case is discarded INFO:Xst:1561 .www."D:/Xilinx/a/barrel_shft.com ================================================================= ======== Analyzing Entity <barrel_shft> in library <work> (Architecture <behavioral>)."D:/Xilinx/a/barrel_shft.vhd" line 47: The following signals are missing in the process sensitivity list: din..vhd" line 213: Mux is complete : default of case is discarded WARNING:Xst:819 . HDL Synthesis * ================================================================= www."D:/Xilinx/a/barrel_shft. Entity <barrel_shft> analyzed. Unit <barrel_shft> generated. i. ================================================================= ======== * ======== Performing bidirectional port resolution.com Page 55 . INFO:Xst:1561 .vhd" line 121: Mux is complete : default of case is discarded INFO:Xst:1561 .btechzone. Synthesizing Unit <barrel_shft>.vhd".btechzone."D:/Xilinx/a/barrel_shft.. Related source file is "D:/Xilinx/a/barrel_shft.vhd" line 143: Mux is complete : default of case is discarded INFO:Xst:1561 . inferred 22 D-type flip-flop(s).Property "use_dsp48" is not applicable for this technology. Found 3-bit up counter for signal <cnt>. Using one-hot encoding for signal <logical>. Found 1-bit register for signal <sclk>. Found 1-bit 16-to-1 multiplexer for signal <i_0$mux0001> created at line 127. Unit <barrel_shft> synthesized. ================================================================= ======== HDL Synthesis Report Macro Statistics # Adders/Subtractors 32-bit adder # Counters 3-bit up counter 32-bit up counter # Registers :1 :2 :1 :1 : 17 Page 56 :1 www.com WARNING:Xst:653 . Found 32-bit up counter for signal <cnt0>.Signal <din> is used but never assigned.btechzone. WARNING:Xst:2734 . inferred 2 Multiplexer(s). Tied to value 0011001111001100.www.btechzone. Found 32-bit adder for signal <cnt0$addsub0000> created at line 234.com . inferred 1 Adder/Subtractor(s). Found 5-bit register for signal <logical>. Summary: inferred 2 Counter(s). Found 1-bit 16-to-1 multiplexer for signal <i_15$mux0001> created at line 104. Found 16-bit register for signal <i>. www. ================================================================= ======== Advanced HDL Synthesis Report Macro Statistics # Counters 3-bit up counter # Registers Flip-Flops # Multiplexers 1-bit 16-to-1 multiplexer :1 :1 : 20 : 20 :2 :2 Advanced HDL Synthesis * ================================================================= www.btechzone.nph' in environment D:\Xilinx.btechzone.com Page 57 .com 1-bit register 5-bit register # Multiplexers 1-bit 16-to-1 multiplexer : 16 :1 :2 :2 ================================================================= ======== ================================================================= ======== * ======== Loading device for application Rf_Device from file '3s250e.Node <logical_0> of sequential type is unconnected in block <barrel_shft>. WARNING:Xst:2677 . Mapping all equations. FlipFlop i_0 has been replicated 1 time(s) FlipFlop i_1 has been replicated 1 time(s) FlipFlop i_10 has been replicated 1 time(s) FlipFlop i_11 has been replicated 1 time(s) FlipFlop i_12 has been replicated 1 time(s) FlipFlop i_13 has been replicated 1 time(s) FlipFlop i_14 has been replicated 1 time(s) FlipFlop i_15 has been replicated 1 time(s) FlipFlop i_2 has been replicated 1 time(s) FlipFlop i_3 has been replicated 1 time(s) FlipFlop i_4 has been replicated 1 time(s) FlipFlop i_5 has been replicated 1 time(s) FlipFlop i_6 has been replicated 1 time(s) FlipFlop i_7 has been replicated 1 time(s) FlipFlop i_8 has been replicated 1 time(s) FlipFlop i_9 has been replicated 2 time(s) FlipFlop logical_1 has been replicated 1 time(s) Low Level Synthesis * ================================================================= www.btechzone.btechzone. Building and optimizing final netlist .. Found area constraint ratio of 100 (+ 5) on block barrel_shft..www..com Page 58 .com ================================================================= ======== ================================================================= ======== * ======== Optimizing unit <barrel_shft> .... actual ratio is 9. ..www.com Page 59 .btechzone.com FlipFlop logical_2 has been replicated 2 time(s) FlipFlop logical_3 has been replicated 2 time(s) FlipFlop logical_4 has been replicated 1 time(s) Final Macro Processing . ------------------------------Partition Report * ================================================================= www.btechzone. ================================================================= ======== Final Register Report Macro Statistics # Registers Flip-Flops : 46 : 46 ================================================================= ======== ================================================================= ======== * ======== Partition Implementation Status ------------------------------No Partitions were found in this design. www.btechzone.ngr : barrel_shft Final Report * ================================================================= # FlipFlops/Latches www.com .btechzone.com ================================================================= ======== * ======== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # # # # # # # # # # # # # GND LUT2 LUT2_L LUT3 LUT3_D LUT3_L LUT4 LUT4_D LUT4_L MUXF5 MUXF6 MUXF7 FDCP : 448 :1 : 20 : 10 : 43 :4 : 11 : 277 :5 : 57 : 14 :4 :2 : 46 : 33 Page 60 : 25 : NGC : Speed : NO : barrel_shft. btechzone.www.com Page 61 .btechzone. --------------------------25 25 out of 108 23% 1 out of 24 4% 237 out of 2448 46 out of 4896 427 out of 4896 9% 0% 8% www.com # # # # FDE BUFGP IBUF OBUF : 13 :1 :1 : 24 :8 : 16 # Clock Buffers # IO Buffers ================================================================= ======== Device utilization summary: --------------------------Selected Device : 3s250etq144-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: Number of GCLKs: --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. 515MHz) www. Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal clk | Clock buffer(FF name) | Load | | BUFGP | 46 | -----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: --------------------------------------------------------------------------+------------------------+-------+ Control Signal rst N0(XST_GND:G) | Buffer(FF name) | IBUF | 33 | | NONE(i_5_1) | 33 | | Load | -----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -4 Minimum period: 6. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.www.com ================================================================= ======== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.com Page 62 .btechzone.btechzone.600ns (Maximum Frequency: 151. 499 i_15_mux0000186 (i_15_mux0000_map52) 1 0.308 i_15 Page 63 ---------------------------------------.000 i_15_mux0000248 (i_15_mux0000) 0.163ns Maximum output required time after clock: 5.600ns (frequency: 151.125ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns) ================================================================= ======== Timing constraint: Default period analysis for Clock 'clk' Clock period: 6.www.668 i_6_1 (i_6_1) 1 0.com .704 0.704 0.704 0.515MHz) Total number of paths / destination ports: 1565 / 46 ------------------------------------------------------------------------Delay: Source: Destination: Source Clock: 6.135 i_15_mux0000223 (i_15_mux0000_map57) 2 0.704 0.455 i_15_mux0000160 (i_15_mux0000_map42) 1 0.btechzone.btechzone.704 0.591 0.com Minimum input arrival time before clock: 11.600ns (Levels of Logic = 5) i_6_1 (FF) i_15 (FF) clk rising Destination Clock: clk rising Data Path: i_6_1 to i_15 Gate Cell:in->out FDCP:C->Q LUT4:I2->O LUT4:I2->O LUT2:I1->O LUT4_L:I3->LO LUT4:I2->O FDCP:D Net fanout Delay Delay Logical Name (Net Name) 5 0.424 i_15_mux0000195 (i_15_mux0000_map53) 1 0.------------ www. 424 i_13_mux000090 (i_13_mux0000_map24) 1 0.0% logic.www. 42.com Page 64 .704 0. 33.0% route) ================================================================= ======== Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 4835 / 46 ------------------------------------------------------------------------Offset: Source: Destination: 11.179 i_13_mux0000103 (i_13_mux0000_map30) 1 0.709ns route) (57.226 i_15_cmp_eq00181 (i_15_cmp_eq0018) 7 0.104 i_13_mux000077_SW0 (N2154) 2 0.2% route) www. 4.883 i_8_mux0000141 (N57) 1 0.704 0.455 i_13_mux0000177 (i_13_mux0000_map49) 1 0.218 1.704 0.com ---------------------------------------Total 6.704 0.btechzone.600ns (4.704 0.------------ ---------------------------------------11.163ns (6.704 0.419ns logic.454ns logic.181ns route) (67.163ns (Levels of Logic = 8) cond3<0> (PAD) i_13 (FF) Destination Clock: clk rising Data Path: cond3<0> to i_13 Gate Cell:in->out IBUF:I->O LUT4:I0->O LUT3:I0->O LUT4:I0->O LUT4_L:I3->LO LUT4:I1->O LUT4_L:I2->LO LUT4:I3->O FDCP:D Total Net fanout Delay Delay Logical Name (Net Name) 33 1.704 1. 2.btechzone.438 cond3_0_IBUF (cond3_0_IBUF) 17 0.8% logic.000 i_13_mux0000286 (i_13_mux0000) 0.308 i_13 ---------------------------------------. btechzone.4% logic.6% route) ================================================================= ======== CPU : 13.com ================================================================= ======== Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 16 / 16 ------------------------------------------------------------------------Offset: Source: Destination: Source Clock: 5. 1.262ns route) (75.125ns (Levels of Logic = 1) i_4 (FF) dout<4> (PAD) clk rising Data Path: i_4 to dout<4> Gate Cell:in->out FDCP:C->Q OBUF:I->O Total Net fanout Delay Delay Logical Name (Net Name) 31 0.262 i_4 (i_4) 3.www.125ns (3.863ns logic.272 dout_4_OBUF (dout<4>) ---------------------------------------.com Page 65 .btechzone.48 s | Elapsed : 13.00 s --> Total memory usage is 174492 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 4 ( 0 filtered) Number of infos : 6 ( 0 filtered www.------------ ---------------------------------------5.23 / 13.591 1.00 / 14. 24. speed -4 Initializing temperature to 85. version 3.ncd barrel_shft. www. Note: For the fastest runtime. set the effort level to "std".26 2007-04-13".www. All rights reserved. Inc.ncd barrel_shft.36 Copyright (c) 1995-2007 Xilinx. device xc3s250e.140 to 1.4. Device speed data version: "PRODUCTION 1.No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x").140 Volts.Range: 1.1.pcf Constraints file: barrel_shft.320 Volts) INFO:Par:282 . package tq144.Range: -40.000 Celsius.000 Celsius) Initializing voltage to 1.btechzone.com 5. For best performance. set the effort level to "high". Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. (default . set the effort level to "med". ARJUN-PC:: Sat Jul 25 18:32:45 2009 par -w -intstyle ise -ol std -t 1 barrel_shft_map.btechzone. The PAR timing summary will list the performance achieved for each clock.2i par J.2 PLACE AND ROUTE REPORT: Release 9.com Page 66 .pcf. "barrel_shft" is an NCD.000 to 100. (default .nph' in environment D:\Xilinx. For a balance between the fastest runtime and best performance. Loading device for application Rf_Device from file '3s250e. btechzone.com Page 67 .com Design Summary Report: Number of External IOBs Number of External Input IOBs Number of External Input IBUFs Number of External Output IOBs Number of External Output IOBs Number of External Bidir IOBs 25 out of 108 23% 9 9 16 16 0 Number of BUFGMUXs Number of Slices Number of SLICEMs 1 out of 24 239 out of 2448 9% 4% 4 out of 1224 1% Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard Starting Placer Phase 1.btechzone.1 (Checksum:989db0) REAL time: 3 secs www.1 Phase 1.www. ....www.5 Phase 7.3 (Checksum:39386fa) REAL time: 3 secs Phase 7..30 (Checksum:2faf07b) REAL time: 3 secs Phase 6. Phase 4. .btechzone......... ...com Phase 2......31 Phase 3...com Page 68 ....8 (Checksum:a7c507) REAL time: 6 secs Phase 9..5 (Checksum:42c1d79) REAL time: 3 secs Phase 8.7 Phase 2....7 (Checksum:1312cfe) REAL time: 3 secs Phase 3..30 Phase 5.... .3 Phase 6.31 (Checksum:1c9c37d) REAL time: 3 secs Phase 4.2 ..8 ......btechzone...........2 (Checksum:989e4f) REAL time: 3 secs Phase 5..... Phase 8.5 Phase 9. .5 (Checksum:55d4a77) REAL time: 6 secs www.... 18 (Checksum:5f5e0f6) REAL time: 7 secs Phase 11.5 (Checksum:68e7775) REAL time: 7 secs REAL time consumed by placer: 7 secs CPU time consumed by placer: 6 secs Writing design to file barrel_shft.btechzone. REAL time: 9 secs REAL time: 9 secs REAL time: 10 secs REAL time: 10 secs REAL time: 10 secs REAL time: 10 secs REAL time: 10 secs Phase 4: 532 unrouted. Phase 2: 1693 unrouted.www.btechzone. (0) Phase 7: 0 unrouted.com Page 69 . Phase 3: 532 unrouted.com Phase 10.ncd Total REAL time to Placer completion: 8 secs Total CPU time to Placer completion: 7 secs Starting Router Phase 1: 1737 unrouted. (0) www. (0) Phase 6: 0 unrouted. (711) Phase 5: 543 unrouted.5 Phase 11.18 Phase 10. ------------------------------Generating "PAR" statistics. (0) REAL time: 10 secs REAL time: 10 secs Total REAL time to Router completion: 10 secs Total CPU time to Router completion: 9 secs Partition Implementation Status ------------------------------No Partitions were found in this design. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays.btechzone.www.com Phase 8: 0 unrouted.btechzone. (0) Phase 9: 0 unrouted. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| clk_BUFGP | BUFGMUX_X1Y10| No | 43 | 0.com Page 70 .098 | +---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net.012 | 0. www. Note this is different from Clock Skew which is reported in TRCE timing report. 531 Listing Pin Delays by value: (nsec) d < 1.956 1.00 < d < 4.392ns| ------------------------------------------------------------------------------------------------------ www.com Page 71 .com The Delay Summary Report The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: The MAXIMUM PIN DELAY IS: 4.100ns| 0 N/A| -----------------------------------------------------------------------------------------------------Autotimespec constraint for clock net clk | SETUP 0 _BUFGP | HOLD | 1.www.--------. -----------------------------------------------------------------------------------------------------Constraint | | Check | Worst Case | Best Case | Timing | Timing | Slack | Achievable | Errors | Score | | N/A| 0| 8.00 < d < 5.00 < d < 3.--------819 630 200 68 31 0 Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met.--------.00 < d < 2. This may be due to a setup or hold violation.00 d >= 5.--------.00 --------.231 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.btechzone.--------.btechzone. INFO:Timing:2761 .btechzone.com Page 72 . Total REAL time to PAR completion: 11 secs Total CPU time to PAR completion: 10 secs Peak Memory Usage: 150 MB Placement: Completed .N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report.www.ncd PAR done! 5.com All constraints were met.3 BITGEN REPORT: www. Routing: Completed .4.No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 Writing design to file barrel_shft.No errors found.btechzone. All signals are completely routed. www.btechzone.com Release 9.2i - Bitgen J.36 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. Loading device for application Rf_Device from file '3s250e.nph' in environment D:\Xilinx. "barrel_shft" is an NCD, version 3.1, device xc3s250e, package tq144, speed -4 Opened constraints file barrel_shft.pcf. Sat Jul 25 18:33:06 2009 D:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:1 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No barrel_shft.ncd Summary of Bitgen Options: +----------------------+----------------------+ | Option Name | Compress | Readback | CRC | Current Setting | (Not Specified)* | (Not Specified)* | Enable** | No** | 1** | Page 73 | | | | | +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ | DebugBitstream | ConfigRate +----------------------+----------------------+ www.btechzone.com www.btechzone.com +----------------------+----------------------+ | StartupClk | Cclk** | +----------------------+----------------------+ | DCMShutdown | Disable** | +----------------------+----------------------+ | DonePin | Pullup** | +----------------------+----------------------+ | ProgPin | Pullup** | +----------------------+----------------------+ | TckPin | Pullup** | +----------------------+----------------------+ | TdiPin | Pullup** | +----------------------+----------------------+ | TdoPin | TmsPin | UnusedPin | GWE_cycle | GTS_cycle | LCK_cycle | DONE_cycle | Persist | DriveDone | DonePipe | Security | Pullup** | Pullup** | Pulldown** | 6** | 5** | NoWait** | 4** | No* | No** | No** | None** | | | | | | | | | | | +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ www.btechzone.com Page 74 www.btechzone.com | UserID | MultiBootMode | ActivateGclk | ActiveReconfig | PartialMask0 | PartialMask1 | PartialMask2 | PartialGclk | PartialLeft | PartialRight | IEEE1532 | Binary | 0xFFFFFFFF** | No* | No* | No* | (Not Specified)* | (Not Specified)* | (Not Specified)* | (Not Specified)* | (Not Specified)* | (Not Specified)* | No* | No** | | | | | | | | | | | | +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ +----------------------+----------------------+ * Default setting. ** The specified setting matches the default setting. Running DRC. DRC detected 0 errors and 0 warnings. Creating bit map... Saving bit stream in "barrel_shft.bit". www.btechzone.com Page 75 com Bitstream generation is complete.btechzone. CHAPTER 6 6.com Page 76 .btechzone.www.1 CONCLUSION: www. google.xilinx.digilent. 6.www.com 2.com (for reference manual) www.3 FUTURE SCOPE: The design has been done for the 16-bit Barrel Shifter. 64-bit and so on to be utilized in DSP Processors and any communication systems like USB transmitters etc.com 4. The bit file has been generated and the output is dumped on the FPGA Device (Spartan3E). The core can be used to design for further designs of 32-bit . www.btechzone.2 Applications of barrel shifter • • • • • Digital Signal Processing Array Processing Graphics Database Addressing High Speed Arithmetic Processors 6. www. The synthesis has been done using XILINX ISE 9.com 3.1i. www.com Page 77 . The simulation has been done using ISE Simulator.wikipedia.com Hence we have designed the IP Core for Barrel Shifter using VHDL. REFERENCES 1. www.btechzone. Advanced VHDL Design by J. Basker www.btechzone. Fourth Edition 6.btechzone. Wakerly.com Page 78 .www.com 5. Digital Design Principles and Practices by John F.