AV02-0120EN+DS+ACPL-332J+11Oct2011

ACPL-332J2.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (VCE) Desaturation Detection, UVLO Fault Status Feedback and Active Miller Clamping Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description The ACPL-332J is an advanced 2.5 A output current, easyto-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-to implement. Features such as integrated VCE detection, under voltage lockout (UVLO), “soft” IGBT turn-off, isolated open collector fault feedback and active Miller clamping provide maximum design flexibility and circuit protection. The ACPL-332J contains a AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. ACPL-332J is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V and 150 A. For IGBTs with higher ratings, the ACPL-332J can be used to drive a discrete power stage which drives the IGBT gate. The ACPL-332J has an insulation voltage of VIORM = 1230 VPEAK. Features • Under Voltage Lock-Out Protection (UVLO) with Hysteresis • Desaturation Detection • Miller Clamping • Open Collector Isolated fault feedback • “Soft” IGBT Turn-off • Fault Reset by next LED turn-on (low to high) after fault mute period • Available in SO-16 package • Safety approvals: UL approved, 5000 VRMS for 1 minute, CSA approved, IEC/EN/DIN-EN 60747-5-2 approved VIORM = 1230 VPEAK Specifications • 2.5 A maximum peak output current • 2.0 A minimum peak output current • 250 ns maximum propagation delay over temperature range • 100 ns maximum pulse width distortion (PWD) • 50 kV/μs minimum common mode rejection (CMR) at VCM = 1500 V Block Diagram 13 UVLO ANODE CATHODE 6, 7 5, 8 LED1 D R I V E R VCC2 11 VOUT DESAT • ICC(max) < 5 mA maximum supply current • Wide VCC operating range: 15 V to 30 V over temperature range • 1.7 A Miller Clamp. Clamp pin short to VEE if not used • Wide operating temperature range: –40°C to 105°C 14 DESAT 9, 12 SHIELD VCLAMP VCC1 FAULT 2 3 LED2 16 10 VEE VCLAMP VE Applications • Isolated IGBT/Power MOSFET gate drive • AC and brushless DC motor drives • Industrial inverters and Uninterruptible Power Supply (UPS) VS 1, 4 SHIELD 15 VLED CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Pin Description 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 12 11 10 9 Pin 1 2 3 Symbol VS VCC1 FAULT Description Input Ground Positive input supply voltage. (3.3 V to 5.5 V) Fault output. FAULT changes from a high impedance state to a logic low output within 5 μs of the voltage on the DESAT pin exceeding an internal reference voltage of 7 V. FAULT output is an open collector which allows the FAULT outputs from all ACPL-332J in a circuit to be connected together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller. Input Ground Cathode Anode Anode Cathode Output supply voltage. Miller clamp Gate drive voltage output Output supply voltage. Positive output supply voltage Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 6.5 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 μs. LED anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only) Common (IGBT emitter) output supply voltage. 4 5 6 7 8 9 10 11 12 13 14 VS CATHODE ANODE ANODE CATHODE VEE VCLAMP VOUT VEE VCC2 DESAT 15 VLED 16 VE Ordering Information ACPL-332J is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part number ACPL-332J RoHS Compliant -000E -500E Package SO-16 Surface Mount X X Tape& Reel X IEC/EN/DIN EN 60747-5-2 X X Quantity 45 per tube 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-332J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: ACPL-332J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-52 Safety Approval and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. 2 005 (3.505 ± 0.127) 0.203 ± 0.458 (11.254) 9° 0.8° 0. Non-Halide Flux should be used.25 mm (10 mils) max.270) LAND PATTERN RECOMMENDATION 1 2 3 4 5 6 7 8 0.363 ± 0.010 (7. 3 .254) ALL LEADS TO BE COPLANAR ± 0.018 (0. Floating Lead Protrusion is 0.Package Outline Drawings ACPL-332J 16-Lead Surface Mount Package 0.002 0.345 ± 0.406 ± 0. 0.312 ± 0.008 ± 0.16) 0. J-STD-020 (latest revision).254) 0.10 (10.254) 0.64) 0.63) 0.050 (1.138 ± 0.457) 16 15 14 13 12 11 10 9 TYPE NUMBER DATE CODE A 332J YYWW 0.076) STANDOFF Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the ACPL-332J’s white mold compound is normal and does note affect device performance or reliability. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard.408 ± 0.085 (2.003 (0.010 (10.025 (0.018 (0.457) 0.025 MIN.763 ± 0.295 ± 0.010 (8.493 ± 0. Method a**.875=VPR.7) 4 . File E55361. VIORM x 1. (take from DS AV01-0579EN Pg. component recognition program up to VISO = 5000 VRMS. under Product Safety Regulations section IEC/EN/ DIN EN 60747-5-2. tm=10 sec. Surface mount classification is class A in accordance with CECCOO802. 100% Production Test with tm=1 sec. Table 1. VIO = 500 V * Symbol Characteristic I – IV I – IV I – IV I – III 55/100/21 2 Unit VIORM VPR VPR VIOTM TS IS. Method b**.Regulatory Information The ACPL-332J is approved by the following organizations: IEC/EN/DIN EN 60747-5-2 Approval under: IEC 60747-5-5 :1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 UL Approval under UL 1577. VIORM x 1. OUTPUT RS 1230 2306 1968 8000 175 400 1200 >109 Vpeak Vpeak Vpeak Vpeak °C mA mW Ω Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. File CA 88324.6=VPR. CSA Approval under CSA Component Acceptance Notice #5. ** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog. Partial discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) Safety-limiting values – maximum values allowed in the event of a failure.89) Maximum Working Insulation Voltage Input to Output Test Voltage. for a detailed description of Method a and Method b partial discharge test profiles. Partial discharge < 5 pC Input to Output Test Voltage. INPUT PS. Case Temperature Input Current Output Power Insulation Resistance at TS. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* Description Installation classification per DIN VDE 0110/1. Dependence of Safety Limiting Values on Temperature.89. Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1. Type and Sample Test. -55 -40 Max. usually the straight line distance thickness between the emitter and detector.(VE . .VEE) (VCC2 .3 8.VEE) (VCC2 .6 Max.7 VCC2 VE + 10 600 150 6 2 2 See Package Outline Drawings section Table 4.5 Units °C °C °C mA A V A A V mA V V V V V A V V mW mW Note 2 2 1 3 3 -0.VE) VO(PEAK) IClamp VClamp VDESAT PO PI Min. 105 30 15 30 .5 -0.8 Units °C V V V mA V Note 2 7 4 5 .5 -0.5 -0.0 5 2.VEE) VCC2 1.3 0. Measured from input terminals to output terminals.5 -0. Insulation and Safety Related Specifications Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Symbol L(101) L(102) ACPL-332J 8.VEE) 12 0.5 -0.5 VE 7.Table 2.40 15 0 15 8 .VE) IF(ON) VF(OFF) Min. Recommended Operating Conditions Parameter Operating Temperature Total Output Supply Voltage Negative Output Supply Voltage Positive Output Supply Voltage Input Current (ON) Input Voltage (OFF) Symbol TA (VCC2 .5 -0.VEE) (VE . 125 105 125 25 1.5 Units mm mm mm Conditions Measured from input terminals to output terminals. shortest distance path along body. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110. 1/89.VEE) (VE .5 2. Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Output IC Junction Temperature Average Input Current Peak Transient Input Current. shortest distance through air.(VE . Through insulation distance conductor to conductor.0 VCC1 33 15 33 . Table 1) >175 IIIa V Table 3.0 8. 300pps) Reverse Input Voltage “High” Peak Output Current “Low” Peak Output Current Positive Input Supply Voltage FAULT Output Current FAULT Pin Voltage Total Output Supply Voltage Negative Output Supply Voltage Positive Output Supply Voltage Gate Drive Output Voltage Peak Clamping Sinking Current Miller Clamping Pin Voltage DESAT Voltage Output IC Power Dissipation Input IC Power Dissipation Solder Reflow Temperature Profile Symbol TS TA TJ IF(AVG) IF(TRAN) VR IOH(PEAK) IOL(PEAK) VCC1 IFAULT VFAULT (VCC2 . (<1 μs pulse width.3. 3 1. 0. VE . VCC1 = 3. Positive Supply Voltage used.2 0.35 1.1 2.5 IO = 0 mA IO = 0 mA VDESAT = 2 V VDESAT = 7.5 5 5 -0.0 90 VCC-2. 26 11.1 0. 7. 10.5 1.5 230 2.1 mA.5 -2. 21 3. VCC2 .1 0.6 -1.4 0.5 VO = VEE + 15 VOUT .0 0.5 2. 23 5.1 mA.5 12.2 1.3 Units V V μA μA A A A A Test Conditions IFAULT = 1. VO > 5 V 0. 6.5 9.3 V.6 10.0 0.VUVLO-) IFLH VFHL VF ΔVF/ΔTA BVR CIN 8 mA V IO = 0 mA.9 -1.5 11. Electrical Specifications (DC) Unless otherwise noted.VEE = 0 V. 24 7.4 -0.0 9. 4.5 2. VCC1 = 5.0 0.5 11. 9.3V VO = VCC2 .24 30 6.17 2.VEE = 30 V.3 5 70 1. all typical values at TA = 25°C.5V VFAULT = 3.1 V V V V UVLO Hysteresis Threshold Input Current Low to High Threshold Input Voltage High to Low Input Forward Voltage Temperature Coefficient of Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance (VUVLO+ .5V IFAULT = 1. 25.4 VO = VCC2 – 15 VO = VEE + 2. 27 28 12 9 7. 9.33 VO = VEE + 2. 10 7. Typ.3 2.5 0. all Minimum/Maximum specifications are at Recommended Operating Conditions.Table 5.95 V mV/°C V pF IF = 10 mA IR = 10 μA f = 1 MHz. VF = 0 V 6 .4 0.13 10 6 10. VCC1 = 3. 9 23 0.8 1. 8.VEE = 14 V IO = -650 μA IO = 100 mA Fig. 5. Note IOH IOL IOLF VOH VOL VtClamp ICL ICC2H ICC2L ICHG IDSCHG VDESAT VUVLO+ VUVLO- -0.5 140 VCC-2. 22 5 3 5 3 6 mA V V V A 4.3V VFAULT = 5. 12 9 mA mA mA mA -0.002 Max.0 V VCC2 -VE >VUVLOVO > 5 V VO < 5 V 8 9. Parameter FAULT Logic Low Output Voltage FAULT Logic High Output Current High Level Output Current Low Level Output Current Low Level Output Current During Fault Condition High Level Output Voltage Low Level Output Voltage Clamp Pin Threshold Voltage Clamp Low Level Sinking Current High Level Supply Current Low Level Supply Current Blanking Capacitor Charging Current Blanking Capacitor Discharge Current DESAT Threshold UVLO Threshold Symbol VFAULTL IFAULTH Min. 0. 11 7.5 V.02 0. VCC1 = 5. CF = Open. Rg = 10 Ω. VCC2 = 30 V μs CDESAT = 100pF. 13. 15 tPHL 100 180 250 ns PWD (tPHL . 29 1.3 1 2.tPLH) PDD tR tF tDESAT(90%) tDESAT(10%) -100 -350 20 100 350 ns ns 14. 14. Cg = 10 nF. Cg = 10 nF.1 kΩ. VF = 0 V VCM = 1500 V. 37 18. Only Positive Supply Voltage used.25 tDESAT(MUTE) tRESET(FAULT) 5 0. 34 21 30. Rg = 10 Ω. CF = 15 pF TA = 25°C. 1. VF = 0 V VCM = 1500 V. 250 Units ns Test Conditions Rg = 10 Ω. Cg = 10 nF. VCC1 = 3. Cg = 10 nF. 32. VCC2 = 30 V CDESAT = 100pF. Cg = 10 nF. 100 Typ.1 kΩ.1 kΩ. CF = 1 nF. 29 Note 13. Rg = 10 Ω. Rg = 10 Ω. VCC2 = 30 V. Duty Cycle = 50%. all Minimum/Maximum specifications are at Recommended Operating Conditions. 37 18 19 tDESAT(FAULT) 0.8 1.25 0.5 2. RF = 2.3V. 14. VCC2 = 30 V CDESAT = 100 pF. IF = 10 mA VCM = 1500 V. VCC2 = 30 V. VCC2 = 30 V Fig.8 DESAT Sense to DESAT Low Propagation Delay DESAT Input Mute RESET to High Level FAULT Signal Delay tDESAT(LOW) 0. RF = 2.Table 6. VCC2 = 30 V CDESAT = 100pF. 180 Max.1 kΩ.5 μs Output High Level Common Mode Transient Immunity |CMH| 15 25 kV/μs 50 60 21.15 2 0.5 3 ns ns μs μs CDESAT = 100pF. RF = 2.1 kΩ. 16. Cg = 10 nF. CF = 1 nF kV/μs TA = 25°C. CF = 1 nF 31. 30. Rg = 10 Ω. 37 30. VCC2 = 30 V TA = 25°C.VEE = 0 V. VCC2 = 30 V.5V. Cg = 10 nF. 30.VEE = 30 V. CF = 15 pF TA = 25°C. 33. all typical values at TA = 25°C.0 μs μs 37 20 0. 13. 15.1 kΩ. IF = 10 mA VCM = 1500 V. 19. 32. VCC1 = 5. 26 Output Low Level Common Mode Transient Immunity |CML| 15 25 22 50 60 7 . f = 10 kHz.1 kΩ. VE . VCC2 = 30 V. RF = 2. 17 17.1 kΩ.5 μs 0. VCC2 = 30 V CDESAT = 100 pF. RF = 2. Rg = 10 Ω. Rg = 10 Ω. 16 50 50 0. VCC2 . Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Difference Between Any Two Parts or Channels Rise Time Fall Time DESAT Sense to 90%VO Delay DESAT Sense to 10% VO Delay DESAT Sense to Low Level FAULT Signal Delay Symbol tPLH Min. RF = 2. RF = 2. 34 31. 20. 16.1 kΩ. RF = 2. IF = 10 mA. RF = 2. Cg = 10 nF. VCC2 = 30 V CDESAT = 100pF. Switching Specifications (AC) Unless otherwise noted. 15. 37 19 17. 33. and the FAULT output to go low. to assure that the output will remain in the high state (i. Derate linearly from 3. Required only when negative gate drive is implemented. This is the “decreasing” (i.5 A at +105°C.VE 12. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. CATHODE of LED to VOUT 18. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. turn-on or “positive going” direction) of VCC2 . 17. The actual power dissipation achievable will depend on the application environment (PCB Layout. Once VCC2 is increased from 0V to above VUVLO+. As measured from ANODE. Max. t = 1 min. This is the “increasing” (i. 7. When driving capacitive loads. TA = 25°C VI-O = 500 V freq=1 MHz TA = 25°C Fig. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse. As measured from IF to VO. and 10 require ground plane connections and may require airflow. Units Vrms Test Conditions RH < 50%. 5. VO > 15 V or FAULT > 2 V). part placement. This value is intended to allow for component tolerances for designs with IO peak minimum = 2. UVLO is needed to ensure DESAT is functional.8 V).0 A at +25°C to 2. See the Recommended PCB Layout section in the application notes for layout considerations. This compensates for increased IOPEAK due to changes in VOL over temperature. In accordance with UL 1577. 9. Pulse Width Distortion (PWD) is defined as |tPHL . Thus. Maximum pulse width = 50 μs. VCM. Maximum pulse width = 1. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together. This supply is optional.e.e.VE > VUVLO+). 23. Once VO of the ACPL-332J is allowed to go high (VCC2 . See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. VCM.3 30 Ω pF °C/W Notes: 1. the DESAT detection feature of the ACPL-332J will be the primary source of IGBT protection.3 mA/°C.0 V or FAULT < 0. 10. 8. The difference between tPHL and tPLH between any two ACPL-332J parts under the same test conditions. a pull-down resistor between the output and VEE is recommended to sink a static current of 650 μA while the output is high. 15.3 VBE. In most cases the absolute maximum output IC junction temperature is the limiting factor. 2. Split resistors network with a ratio of 1:1 is needed at input LED1. 9. 19. This is the amount of time from when the DESAT threshold is exceeded. 24. to assure that the output will remain in a low state (i. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse.0 ms. air flow. VOH will approach VCC as IOH approaches zero units. For High Level Output Voltage testing.5V. 14.Table 7. This is supply voltage dependent. 26. 25 25 > 109 1. the DESAT detection and UVLO features of the ACPL-332J work in conjunction to ensure constant IGBT protection. until the FAULT output goes low. 4. See Figure 34. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used. 5000 Typ. 20.VE 13.0 A. Derate linearly above 70°C free air temperature at a rate of 0. 15 V is the recommended minimum operating positive supply voltage (VCC2 . Maximum pulse width = 10 μs. 22. To clamp the output voltage at VCC . 16. 25. 3. Package Characteristics Parameter Input-Output Momentary Withstand Voltage Input-Output Resistance Input-Output Capacitance Output IC-to-Pins 9 &10 Thermal Resistance Symbol VISO RI-O CI-O θ09-10 Min...e. etc. VO < 1. See the Description of Operation (Auto Reset) topic in the application information section. 21. This load condition approximates the gate load of a 1200 V/150A IGBT. each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second.). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table. turn-off or “negative going” direction) of VCC2 . 11. 8 . VOH is measured with a dc load current.tPLH| for any given unit. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low. pins 4. DESAT will remain functional until VCC2 is decreased below VUVLO-. Note 24.VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 12.. In order to achieve the absolute maximum power dissipation specified. Input IC power dissipation does not require derating. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details. 6.e. temperature 0.V ____ I -0.0 1.OUTPUT LOW CURRENT 2.OUTPUT LOW VOLTAGE .TEMPERATURE - Figure 4.TEMPERATURE . IOL vs.5 -40 -20 0 TA 20 40 60 80 105 .1 0.5 -2 -2.5 -1 -1.o C Figure 2.HIGH OUTPUT VOLTAGE DROP .TEMPERATURE .OUTPUT HIGH CURRENT .A 5 4 3 2 1 0 -40 -----V OUT =VEE +15V ___VOUT =VEE +2.05 0 -40 -20 0 20 40 oC 60 80 105 T A .V 0.oC OUT Figure 3.oC IOL . temperature Figure 5. VOL vs.25 = -650uA VOL .0 IOH . IOH vs.15 0.5 1.2 0.IF tr tf 90% 50% V OUT t PLH t PHL 10% Figure 1.5 T A .5V -20 0 20 40 60 80 105 2.0 -40 -20 0 20 40 60 80 105 T A . temperature 9 .TEMPERATURE . temperature 0 (VOH .VCC) . VOUT propagation delay waveforms 3. VOH vs. 0 0.5 1 1.mA 3. VOH vs. VOL vs.55 -0.A _ _ _ _ 105 o C ______ 25 o C --------.BLANKING CAPACITOR CHARGING CURRENT .V _ _ _ _ 105 o C ______ 25 o C --------.OUTPUT SUPPLY CURRENT .HIGH OUTPUT VOLTAGE DROP .35 2. IOL 4 3.30 2.00 2.45 -0.-40 o C Figure 6.25 2.-40 o C 8 7 6 5 4 3 2 1 0 0 0.5 IoL .20 Cc 2 H ICC _________ 2 L ICC2 .75 2. ICC2 vs. temperature 2.50 2.4 0. temperature -0.OUTPUT SUPPLY CURRENT .25 15 20 25 VCC2 .mA 30 2.5 2 2.30 V OH .8 1. temperature 10 .mA ICH .25 3.V 29 28 27 26 25 0.oC Figure 8.65 ---------I Figure 9.----I CC2 H _____ ___CC2 L _ I 2 1 0 -40 -20 0 20 40 oC 60 80 105 -20 0 TA 20 40 60 80 105 T A -TEMPERATURE- .LOW OUTPUT VOLTAGE DROP .25 2.00 -40 .0 VOL .OUTPUR SUPPLY VOLTAGE .50 ICL .6 .TEMPERATURE .---.OUTPUT LOW CURRENT . VCC2 Figure 11.A 0.35 -40 -20 0 20 40 60 oC 80 105 T A . IOH Figure 7.CLAMP LOW LEVEN SINKING CURRENT 3 ICC2 .TEMPERATURE - Figure 10. ICHG vs.2 I OH 0. ICL vs.OUTPUT HIGH CURRENT . ICC2 vs.V -0. load capacitance 11 . Propagation delay vs.PROPAGATION DELAY .ohm Figure 14. Propagation delay vs.ms 200 100 0 0 10 20 30 40 50 LOAD CAPACITANCE .tPLH _______tPHL TP . DESAT threshold vs.V 25 30 0 10 20 30 40 50 LOAD RESISTANCE .5 300 ---------.SUPPLY VOLTAGE .ns 250 200 6.0 TP .tPLH _______tPHL TP . Propagation delay vs.ms 250 200 200 150 150 100 15 100 20 Vcc .nF Figure 16.PROPAGATION DELAY . temperature 300 ---------.0 -40 -20 0 20 40 60 oC 80 105 100 -40 -20 0 20 40 60 oC 80 105 T A .ns 250 Figure 13.DESAT THRESHOLD . Propagation delay vs.PROPAGATION DELAY . temperature 300 ---------. supply voltage Figure 15.5 150 6.t PLH _______t PHL VDESAT .V 7. load resistance 300 ---------.PROPAGATION DELAY .7.t PLH _______tPHL TP .TEMPERATURE - T A .TEMPERATURE - Figure 12. ms ------.ns TDESAT .nF Figure 19.0 TDESAT90% .004 1.o C T A .DESAT Sense to 90% Vo Delay .012 ------.TEMPERATURE .0 TDESAT10% . temperature 0.V cc2 =15V _____Vcc2 =30V 0.5 100 -40 -20 0 20 40 60 80 105 1.0 150 1.5 250 200 2.0 10 20 30 LOAD RESISTANCE . temperature 4. load capacitance 12 .3.V cc2 =15V _____Vcc2 =30V 0.ohm 40 50 0.0 -40 -20 0 20 40 oC 60 80 105 T A .0 0. DESAT sense to 10% VOUT delay vs.us Figure 18.0 TDESAT10% .DESAT Sense to 10% Vo Delay .000 0 10 20 30 40 50 LOAD CAPACITANCE . DESAT sense to 10% VOUT delay vs.0 2.TEMPERATURE - Figure 17. DESAT sense to 10% VOUT delay vs. load resistance Figure 20.DESAT Sense to 10% Vo Delay .DESAT Sense to 10% Vo Delay .us 300 ------.Vcc2 =15V _____Vcc2 =30V 2. DESAT sense to 90% VOUT delay vs.008 3. 1μF + _ + _ 30V Figure 22.1μF + _ 30V Figure 23. IOL Pulsed test circuit 1 2 3 4 5 6 7 10mA 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 12 VOUT 11 0.1μF + _ 0.1 2 3 4 5 6 7 10mA 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 15V Pulsed 12 11 10 9 0.1μF IOUT + _ 30V Figure 21. IOH Pulsed test circuit 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 15V Pulsed 12 IOUT 11 0.1μF 10 9 650μA 0.1μF 10 9 0. VOH Pulsed test circuit 13 . 1μF 10 9 ICC2 0. ICC2L test circuit 14 .1μF 10 9 0. VOL Pulsed test circuit 1 2 3 4 5 6 7 10mA 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 12 11 0.1μF + _ 30V Figure 26.1μF + _ 30V Figure 24.1μF + _ 30V Figure 25. ICC2H test circuit 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 12 11 0.1μF 10 9 I CC2 0.1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 100mA 12 VOUT 11 0. 1μF 0. 10kHz. tr. test circuit 15 + + _ _ 0.1μF 10mA.1μF 10 9 7V Figure 28.1μF 10 9 0. tf. tPHL.1μF + _ 30V + _ 30V .1μF + _ 30V Figure 27. ICHG Pulsed test circuit 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 IDSCHG 13 12 11 0. tPLH. IDSCHG test circuit 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 12 VOUT 11 10Ω 10 9 10nF 0. 50% Duty Cycle Figure 29.1 2 3 4 5 6 7 10mA 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 ICHG 15 14 13 12 11 0. 1kΩ CF=15pF or 1nF VCM VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 30V 13 12 10Ω 11 10 9 3 4 0. CMR Test circuit LED2 off 1 5V 2 RF=2.1kΩ CF=15pF or 1nF VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 30V 13 12 10Ω 10 11 10 9 3 4 0.1μF SCOPE 5 6 360Ω 7 8 0.1μF SCOPE 5 6 360Ω 7 8 0.1 2 RF=2. CMR Test Circuit LED2 on 16 VCM .1μF VFAULT CF 3 5V + _ 4 5 6 7 + _ 30V 10mA 8 Figure 30.1μF 10 10nF 9 VIN 0.1kΩ VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 12 VOUT 11 10Ω 0.1μF 10nF Figure 31. tDESAT fault test circuit 1 5V 2 RF=2.1μF 10nF Figure 32. 1μF 5 6 360 Ω 7 8 10 9 10nF 12 11 SCOPE 10 Ω 0.1kΩ CF=15pF or 1nF VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 30V 13 3 4 0.1 5V 2 RF=2. CMR Test circuit LED1 off 1 5V 2 RF=2.1μF 3 4 0.1kΩ CF=15pF or 1nF VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 30V 13 12 11 10 9 SCOPE 10Ω 10 0. CMR Test Circuit LED1 on 17 .1μF 5 6 5V 7 8 CATHODE ANODE ANODE CATHODE Split resistors network with a ratio of 1:1 VCM Figure 34.1μF 5 6 360Ω 7 8 10nF VCM Figure 33. An optically isolated power output stage drives IGBTs with power ratings of up to 150 A and 1200 V. and two optical channels. However. Because of the transient nature of the charging currents. 4 SHIELD 15 VLED Figure 35. this fault status is transmitted back to the input via LED2. 7 5. In this application. and an open collector fault output suitable for wired ‘OR’ applications. and LED2 remains off. An output IC provides local protection for the IGBT to prevent damage during over current. The following describes about driving IGBT. ERA34-10) and capacitor CBLANK are necessary external components for the fault detection circuitry.1 kΩ) and a 1000 pF filtering capacitor. Once the output is in the high state.5V for IGBT and 12. Depending upon the MOSFET or IGBT gate threshold requirements. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. the LED1 directly controls the IGBT gate through the isolated output detector IC. The output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path. Thus. where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. designers may want to adjust the VCC supply voltage (Recommended VCC = 17. transmits the fault status feedback signal. 18 . the IGBT gate driver will shut down when a fault is detected and fault reset by next cycle of IGBT turn on. 12 SHIELD VCLAMP VCC1 FAULT 2 3 LED2 16 10 VEE VCLAMP VE VS 1. During power-up.Application Information Product Overview Description The ACPL-332J is a highly integrated power control device that incorporates all the necessary components for a complete. UVLO and DESAT work in conjunction to provide constant IGBT protection. isolated IGBT / MOSFET gate drive circuit with fault protection and feedback into one SO-16 package. The recommended application circuit shown in Figure 36 illustrates a typical gate drive implementation using the ACPL-332J. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost. the DESAT (VCE) detection feature of the ACPL-332J provides IGBT protection. the output power stage. it is also applicable to MOSFET.1 μF) provide the large transient currents necessary during a switching transition. CF. Active Miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. Under normal operation. Application notes are mentioned at the end of this datasheet. The gate resistor RG serves to limit gate charge current and controls the IGBT collector voltage rise and fall times. A 47 kΩ pull down resistor RPULL-DOWN on VOUT provides a predictable high level output voltage (VOH).5V for MOSFET). 13 UVLO ANODE CATHODE 6. as indicated by LED1. and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. a low current (5mA) power supply suffices. size. The two supply bypass capacitors (0. the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT. The desaturation diode DDESAT 600V/1200V fast recovery type. transmits the gate control signal. The return optical signal path. Simultaneously. trr below 75ns (e. The open collector fault output has a passive pull-up resistor RF (2. Block Diagram of ACPL-332J Recommended Application Circuit The ACPL-332J has an LED input gate control. by forcing the ACPL-332J’s output low. A built in “watchdog” circuit. Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input control circuitry. When an IGBT fault is detected. and complexity of a discrete design.g. UVLO monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. as indicated by LED2. 8 LED1 D R I V E R VCC2 11 VOUT DESAT 14 DESAT 9. reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive over voltages. the output detector IC immediately begins a “soft” shutdown sequence. All input LED signals will be ignored during the mute period to allow the driver to completely soft shut-down the IGBT.5V VDESAT tBLANK VOUT tDESAT(LOW)) Reset done during the next LED turn-on 50% tDESAT(10%) 90% 10% tDESAT(90%) tRESET(FAULT)) FAULT tDESAT(FAULT)) 50% tDESAT(MUTE)) )) 50% Figure 37. When the voltage on the DESAT pin exceeds 6.1μF VLED 15 DESAT 14 VCC2 13 VEE 12 RG VOUT 11 VCLAMP 10 VEE 9 RPULL--DOWN Q2 + VCE CBLANK 100 Ω DDESAT + _ 0. activated is an internal feedback channel which brings the FAULT output low for the purpose of notifying the micro-controller of the fault condition. See Figure 37.1 2 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE 16 0. 7 and 8). The FAULT output is high. Fault Timing diagram 19 .1μF RF 3 CF 4 5 6 R 7 8 + _ Q1 + HVDC + VCE - + _ 3-PHASE AC . VOUT is slowly brought low in order to “softly” turn-off the IGBT and prevent large di/dt induced voltages. The fault mechanism can be reset by the next LED turn-on after the 5us (minimum) mute time. VOUT of the ACPL-332J is controlled by input LED current IF (pins 5. See Figure 37. the output will be muted for 5 μs (minimum). IF 6. 6.HVDC Figure 36. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp Description of Operation Normal Operation During normal operation.5 V while the IGBT is on. Fault Reset Fault Condition The DESAT pin monitors the IGBT Vce voltage. with the IGBT collector-to-emitter voltage being monitored through DESAT. Also Once fault is detected. During the off state of the IGBT. Therefore. local IGBT desaturation detection and shut down. a weak pull-down device in the ACPL-332J output drive stage will turn on to ‘softly’ turn off the IGBT. The nominal blanking time is calculated in terms of external capacitance (CBLANK). The fault detection method. By directly measuring the collector voltage. is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. This nominal blanking time represents the longest time it will take for the ACPL-332J to respond to a DESAT fault condition. the fault detect circuitry is simply disabled to prevent false ‘fault’ signals. The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT threshold. Thus.5 V / 240 μA = 2. but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known. IF ON ON ON OFF OFF UVLO(VCC2-VE) Active Not Active Not Active Active Not Active DESAT Function Not Active Active (with DESAT fault) Active (no DESAT fault) Not Active Not Active Pin 3 (FAULT) Output High Low (FAULT) High (or no fault) High High VOUT Low Low High Low Low 20 . high output current driver. Once VCC2 is increased from 0V to above VUVLO+. Once UVLO is not active (VCC2 VE > VUVLO). the DESAT detection and UVLO features of the ACPL-332J work in conjunction to ensure constant IGBT protection. UVLO and a detected IGBT Desat condition. This time period. Slow IGBT Gate Discharge during Fault Condition When a desaturation fault is detected. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on. an overly conservative over current threshold is not needed to protect the IGBT. the DESAT voltage threshold. Before the dissipated energy can reach destructive levels. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short). DESAT Fault Detection Blanking Time Desaturation Detection and High Current Protection The ACPL-332J satisfies these criteria by combining a high speed. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. The recommended 100pF capacitor should provide adequate blanking as well as fault response times for most applications.Output Control The outputs (VOUT and FAULT) of the ACPL-332J are controlled by the combination of IF. while the current sense method relies on a preset current threshold to predict the safe limit of operation. called the DESAT blanking time is controlled by the internal DESAT charge current. the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. the IGBT is shut off. and DESAT charge current (ICHG) as tBLANK = CBLANK x VDESAT / ICHG. high voltage optical isolation between the input and output. During the slow turn off. the ACPL-332J limits the power dissipation in the IGBT even with insufficient gate drive voltage. at which time the large pull down device clamps the IGBT gate to VEE. and an optically isolated fault status feedback signal into a single 16-pin surface mount package. VOUT is allowed to go high. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored. FAULT threshold voltage (VDESAT ). though a value smaller than 100 pF is not recommended. and the external DESAT capacitor. DESAT will remain functional until VCC2 is decreased below VUVLO-. which is adopted in the ACPL-332J. and the DESAT (pin 14) detection feature of the ACPL-332J will be the primary source of IGBT protection. The capacitance value can be scaled slightly to adjust the blanking time. the large output pull-down device remains off until the output voltage falls below VEE + 2 Volts. The nominal blanking time with the recommended 100pF capacitor is 100pF * 6.7 μsec. the soft shut-down sequence will begin after approximately 3 μsec. RPULL-DOWN between the output and VEE is recommended to sink a static current of several 650 μA while the output is high. and a FAULT pin pullup resistor and Active Miller Clamp connection. the UVLO and DESAT Fault detection feature work together to provide seamless protection regardless of supply voltage (VCC2). The added resistance will not alter the DESAT threshold or the DESAT blanking time. 21 . a pull-down resistor. The UVLO function causes the output to be clamped whenever insufficient operating supply (VCC2) is applied. This may result in a large negative voltage spike on the DESAT pin which will draw substantial current out of the driver if protection is not used. At very low gate voltages (below 10 V). Output pull-down resistor. Rpull-down = [VCC2-3 * (VBE)] / 650 μA. first the DESAT protection circuitry becomes active. To limit this current to levels that will not damage the driver IC. 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 13 12 RG 11 10 9 RPULL-DOWN VCC Figure 38. 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 15 14 VCC 13 12 RG 11 10 9 100pF 100 Ω DDESAT Active Miller Clamp A Miller clamp allows the control of the Miller current during a high dV/dt situation and can eliminate the use of a negative supply voltage in most of the applications.Under Voltage Lockout The ACPL-332J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the ACPL-332J output low during power-up. As VCC2 is increased from 0 V (at some level below VUVLO+). A 1000 pF capacitor should be connected between the fault pin and ground to achieve adequate CMOS noise margins at the specified CMR value of 50 kV/μs. Figure 39. Before the time the UVLO clamp is released. the output voltage rapidly rises to within 3 diode drops of VCC2. At gate voltages below 13 V typically. the UVLO clamp is released to allow the device output to turn on in response to input signals. Other Recommended Components The application circuit in Figure 36 includes an output pull-down resistor. the DESAT protection is already active. IGBTs typically require gate voltages of 15 V to achieve their rated VCE(ON) voltage. especially at higher currents. a 100 ohm resistor should be inserted in series with the DESAT diode. a DESAT pin protection resistor. The clamp is disabled when the LED input is triggered again. Output Pull-Down Resistor During the output high transition. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula. the UVLO clamp is released.5V typ for a Miller current up to 1100mA. the VCE(ON) voltage increases dramatically. The clamp voltage is VOL+2. To limit the output voltage to VCC2-3(VBE). If the output current then drops to zero due to a capacitive load. the gate voltage is monitored and the clamp output is activated when gate voltage goes below 2V (relative to VEE). As VCC2 is further increased (above VUVLO+). Capacitor on FAULT Pin for High CMR Rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. DESAT pin protection. During turn-off. the output voltage will slowly rise from roughly VCC2-3(VBE) to VCC2 within a period of several microseconds. the IGBT may operate in the linear region and quickly overheat. Once VCC2 exceeds VUVLO+ (the positive-going UVLO threshold). a FAULT pin capacitor. Therefore. DESAT Pin Protection Resistor The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. over-current ) to alert the microcontroller.HVDC Figure 40. external booster. over-temperature. Large IGBT drive with negative gate drive. * indicates component required for negative gate drive topology 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 0.1μF 0.Pull-up Resistor on FAULT Pin The FAULT pin is an open collector output and therefore requires a pull-up resistor to provide a high-level signal. external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used) VCLAMP is used as secondary gate discharge path.1μF 12 Optional R1 11 Q1 10 RPULL-DOWN 9 R3 RG Optional R2 + _ + HVDC + VCE - + _ * Q2 3-PHASE AC + VCE - .g. IGBT drive with negative gate drive. overvoltage. Other Possible Application Circuit (Output Stage) 1 2 3 4 5 6 7 8 VS VCC1 FAULT VS CATHODE ANODE ANODE CATHODE VE VLED DESAT VCC2 VEE VOUT VCLAMP VEE 16 0.1μF 12 Optional R1 11 Q1 10 RPULL-DOWN 9 RG Optional R2 + _ + HVDC + VCE - + _ * Q2 3-PHASE AC + VCE - .HVDC Figure 41. VCLAMP control secondary discharge path for higher power application.1μF 0.1μF 15 14 13 0. 22 . Also the FAULT output can be wire ‘OR’ed together with other types of protection (e.1μF 15 14 13 0. 12 + θ9. their exact number may not be available. the only other limitation to the amount of power one can dissipate is the absolute maximum junction temperature specification of 125°C. In order to achieve the power dissipation specified in the absolute maximum specification. it is imperative that pins 5. please go to our web site: www. 4.October 11. Data subject to change. a more accurate method of calculating the junction temperature is with the following equations: Tji = Pi θi5 + TP5 Tjo = Po θo9.12A = pin 9 and 12 to ambient thermal resistance *The θ5A and θ9.12 = pin 9 and 12 temperature at package edge θI5 = input side IC to pin 5 thermal resistance θo9. the pin temperature for pins 9 and 12 should be measured (at the package edge) under worst case operating environment for a more accurate estimate of the junction temperatures. for this purpose. pins 9 and 12. This value may increase or decrease by a factor of 2 depending on PCB layout and/or airflow. Therefore. AV02-0120EN . Avago Technologies. 12 temperatures be measured with a thermal couple on the pin at the ACPL-332J package edge.com Avago. 5 & 8 for the input IC and pins 9 & 12 for the output IC. 2011 .Plastics Optocoupler Product ESD and Moisture Sensitivity For product information and a complete list of distributors.12 These equations.avagotech. Figure 42. Tji = junction temperature of input side IC Tjo = junction temperature of output side IC TP5 = pin 5 temperature at package edge TP9. The junction temperatures can be calculated with the following equations: Tji = Pi (θi5 + θ5A) + TA Tjo = Po (θo9.) Heat flow through other pins or through the package directly into ambient are considered negligible and not modeled here.12A) + TA where Pi = power into input IC and Po = power into output IC.Desaturation Fault Detection AN5315 – “Soft” Turn-off Feature AN1043 – Common-Mode Noise : Sources and Solutions AN02-0310EN . require that the pin 5 and pins 9. Copyright © 2005-2011 Avago Technologies. All rights reserved.12 + TP9. (There are two VEE pins on the output side. however.12A are dependent on PCB layout and airflow. As long as the maximum power specification is not exceeded.12 = output side IC to pin 9 and 12 thermal resistance θ5A = pin 5 to ambient thermal resistance θ9.Thermal Model The ACPL-332J is designed to dissipate the majority of the heat through pins 1. and the A logo are trademarks of Avago Technologies in the United States and other countries.12A values shown here are for PCB layouts with reasonable air flow. and 12 have ground planes connected to them. If the calculated junction temperatures for the thermal model in Figure 42 is higher than 125°C. Since θ5A and θ9. ACPL-332J Thermal Model Related Application Notes AN5314 – Active Miller Clamp AN5324 . 9.