VLSI ArchitectureAssignment-2: MIPS Single-Cycle Processor Note: Total credits 30 points. More than 30% similarity with other students will receive 00 points [matching software will be used for comparing]. Introduction In this assignment you will build the MIPS single-cycle processor using Verilog. You will combine your ALU from assignment-1. Then you will load a test program and check that the instructions work. By the end of this assignment, you should thoroughly understand the internal operation of the MIPS single-cycle processor. Please read and follow the instructions for this assignment carefully. You may drop points for silly errors like not printing all the signals requested. Before starting this assignment, you should be very familiar with the single-cycle implementation of the MIPS processor described in the textbook. The single-cycle processor schematic from the lecture is repeated in Figure 1 for your convenience. This version of the MIPS single-cycle processor can execute the following instructions: add, sub, and, or, slt, lw, sw, beq, addi, and j. Our model of the single-cycle MIPS processor divides the machine into two major units: the control and the datapath. Each unit is constructed from various functional blocks. For example, as shown in the figure, the datapath contains the 32-bit ALU that you designed in assignment-1, the register file, the sign extension logic, and five multiplexers to choose appropriate operands. 1. MIPS Single-Cycle Processor The Verilog single-cycle MIPS module [the mips module], should instantiate two submodules, controller and datapath. The controller module contains two submodules: maindec and aludec. The maindec module produces all control signals except those for the ALU. The aludec module produces the control signal, alucontrol[2:0], for the ALU. Make sure you thoroughly understand the controller module. After you have thoroughly designed the controller module, design the datapath Verilog module. The datapath will have quite a few submodules. The highest-level module, top, includes the instruction and data memories as well as the processor [the mips module]. top is the complete module which has mips module and instruction and data Page 1 of 6 Each of the memories is a 64-word × 32-bit array. $0. $5. end $7. $6. 5 3 0xc $2 $4 $4 end $4 around 10 $2 $5 $2 0($0) 71($2) # # # # # # # # # # # # # # # # 20020005 20070003 2003000c 00e22025 00642824 00a42820 10a70008 0064302a 10c00001 2005000a 00e2302a 00c53820 00e23822 0800000f 8c070000 ac470047 ALP 1. $5. $6. top. Notice that only a subset of the PC bits (PC7:2) will be used to address the memory. The other signals are there for verification purposes only.asm To use this test code. There should be no errors or warnings (you can confirm this by looking at the errors tab at the bottom of the screen). $7. resynthesize. $0. #Assembly Code main: around: end: addi addi addi or and add beq slt beq addi slt add sub j lw sw # Machine Code $2. 3. If it does not look as you expected. It would be nice to be able to write Verilog code for a memory with some initial values (the test program). $7. The instruction memory needs to contain some initial values representing the program. $3. MIPS assembly program: test1.memories. View the synthesis report. $3. it must be loaded into the MIPS instruction memory. $7. Be sure you understand thoroughly why only these bits are used. $5. $6. $7. 2. $7. $7. $4. The instruction memory. View the RTL schematic. $5. will be constructed as a ROM that will hold the program (the instructions) to execute. $0. Synthesis Synthesize the highest level module. A Test Program We will use the following simple program to test that basic instructions work: # test1. $3. $5. Notice that the only necessary inputs to the highest level module are clk and reset. $7. $0. $6. imem. fix the errors and Page 2 of 6 . $7. $0.asm # For Assignment-2 MEL G642 # # Test MIPS instructions. You may use any method to load the test code into the memory. and readdata. clearly labeled and in the following order: 1. if you don’t know what to expect the answer should be. pc.v for test1. Use several pages as necessary. instr. What to Upload Please upload each of the following items.asm The simulation waveforms should give the signal values in hexadecimal format and should be in the following order: clk. Your feedback Page 3 of 6 . Please indicate how many hours you spent on this assignment. What address will the final sw instruction write to and what value will it write? Write the testbench module. top. This will not affect your grade. Testing the single-cycle MIPS processor To test the processor.asm on the Verilog code. Complete the chart in Table 1 at the end with your predictions. It generates clock and reset inputs for the module under test. print out your final waveform. After you have fixed any bugs. Simulation waveforms of: top. However. Do these match your expectations from your code analysis in Table 1? During debug. but will be helpful for calibrating the workload for next assignment.4. aluout. A completed version of Table 1. Check that the waveforms are zoomed out enough that the grader can read your bus values. aluout. on the final waveform that you turn in. you are unlikely to get the right answer. 2. Do not display any other signals in the waveform. It also checks for a memory write and verifies the address and data being written. 5. you will simulate running test1. Your Verilog code for your MIPS computer 4. writedata. writedata. pc. memwrite. you’ll likely want to view several internal signals. reset. and readdata. 3. Unreadable waveforms will receive no credit. instr. reset. Begin by predicting what should happen on each cycle when running the program. Be sure the waveforms match your expectations. All the values need to be output in hexadecimal and must be readable to get full credit. In a complex system. memwrite. show ONLY the following signals in this order: clk. pdf Example: 2011A1PS102G_A2.pdf Less credit for mistake in file name Improper content. Page 4 of 6 .All the above five items should be in a single file with file name “yourid_A2”. Uploaded it in pdf format with file name yourid_A1. 3 20070003 addi $3. is low (0) when nextpc should be pc+4. pcsrc.$0. pcsrc is high (1) when the nextpc should be the branch target address (pcbranch). You will notice that all of these signals are not available from the top-level module (mips). First fourteen cycles of executing assembly program test1. Page 5 of 6 . For debugging. zero is high (1) only if aluout is 0. a signal in the datapath. branch is asserted (1) when the instruction is a branch (beq) instruction. aluout is the output of the ALU at each cycle.asm Remember.$0.0xc 2003000c 0 0 12 12 0 0 4 0 0C write data x mem write 0 read data 0 0 5 6 7 8 9 10 11 12 13 14 Table 1. you might want to look at these signals and others.Cycle reset pc instr branch srca srcb aluresult zero pcsrc 1 1 00 0 0 5 5 0 0 2 0 04 0 0 3 3 0 0 3 0 08 addi $2.5 20020005 addi $7.$0. Jump 31:26 5:0 MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst PCSrc RegWrite CLK 0 1 0 PC' PC 1 A RD Instr Instruction Memory 25:21 20:16 A1 A2 A3 WD3 CLK WE3 RD2 0 SrcB 1 Register File 20:16 PCJump + 15:11 15:0 ALUResult WriteData 0 1 ImmExt Sign Extend <<2 + 4 WriteReg4:0 PCPlus4 Zero SrcA RD1 ALU CLK 27:0 31:28 25:0 <<2 Figure 1: Single-cycle MIPS processor Page 6 of 6 PCBranch WE A RD Data Memory WD ReadData 0 Result 1 .