LẬP TRÌNH THỐNG NHÚNG TRÊNVI XỬ LÝ ARM (Programming the ARM Microprocessor for Embedded Systems) Nguyễn Tấn Thịnh
[email protected] ARM Architecture and ARM Core Overview I. GIỚI THIỆU KIẾN TRÚC ARM 1.1 Introduction to ARM Ltd. 1.2 The ARM Architecture. 1.2.1 Example ARM based system: 1 ARM Architecture and ARM Core Overview 1.2.2 Which architecture is my processor? Processor core ARM7TDMI family Architecture v4T ARM720T, ARM740T ARM9TDMI family v4T ARM920T,ARM922T,ARM940T ARM9E family v5TE, v5TEJ ARM946E-S, ARM966E-S, ARM926EJ-S ARM10E family v5TE, v5TEJ ARM1020E, ARM1022E, ARM1026EJ-S ARM11 family v6 ARM1136J(F)-S v6 ARM1156T2(F)-S v6T2 ARM1176JZ(F)-S v6Z Cortex family ARM Cortex-A8 v7A ARM Cortex-R4 v7R ARM Cortex-M3 v7M More information is available at arm.com 1.2.3 Data Sizes and Instruction Sets. ARM is a RISC architecture Many instructions execute in a single cycle ARM is a 32-bit load / store architecture When used in relation to the ARM: Halfword means 16 bits (two bytes) Word means 32 bits (four bytes) Doubleword means 64 bits (eight bytes) 2 2. 1. The ARM has seven basic operating modes: Each mode has access to Its own stack space and a different subset of registers. 1.2.4 Processor Modes. 3 .ARM Architecture and ARM Core Overview Most ARMs implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set Latest ARM cores introduce a new instruction set Thumb-2 Provides a mixture of 32-bit and 16-bit instructions Maintains code density with increased flexibility Jazelle cores can also execute Java bytecode.5 The ARM Register Set. Some operations can only be carried out in a privileged mode. ARM Architecture and ARM Core Overview 1.6 Register Organization Summary. 4 .2. 2. Condition code flags T Bit N = Negative result from ALU T = 0: Processor in ARM state Z = Zero result from ALU T = 1: Processor in Thumb state C = ALU operation Carried out Introduced in Architecture 4T V = ALU operation oVerflowed Mode bits Sticky Overflow flag . IT [abcde] IF THEN conditional execution of Thumb2 instruction groups. I = 1: Disables the IRQ GE[3:0] used by some SIMD instructions.8 Program Counter (r15).7 Program Status Registers. F = 1: Disables the FIQ 1. E bit controls load/store endianness.ARM Architecture and ARM Core Overview 1. A bit disables imprecise data aborts.Q flag Architecture 5TE and later only Specify the processor mode New bits in V6 Indicates if saturation has occurred J bit Architecture 5TEJ and later only J = 1: Processor in Jazelle state Interrupt Disable bits. When the processor is executing in ARM state: All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).2. When the processor is executing in Thumb state: 5 . ARM Architecture and ARM Core Overview All instructions are 16 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instructions cannot be byte aligned. 1.2.9 Exception Handling. When an exception occurs, the core: Copies CPSR into SPSR_<mode> Sets appropriate CPSR bits Change to ARM state Change to exception mode Disable interrupts (if appropriate) Stores the return address in LR_<mode> Sets PC to vector address To return, exception handler needs to: Restore CPSR from SPSR_<mode> Restore PC from LR_<mode> This can only be done in ARM state. 1.2.10 Data Alignment. Memory accesses must always be appropriately aligned for size of access Unaligned addresses will produce unexpected/undefined results. 6 ARM Architecture and ARM Core Overview Detect invalid unaligned data accesses with ‘Data Abort’ exception. External logic required, or use MMU when available Beware that instruction fetches may appear unaligned Unaligned data can be accessed using aligned access combined with shift/mask operations. 1.2.11 Endian Configuration. Endianness determines how contents of registers relate to the contents of memory. ARM registers are word (4 bytes) width ARM addresses memory as a sequence of bytes ARM processors are little-endian. But can be configured to access big-endian memory systems Little-endian memory system Least significant byte is at lowest address Big-endian memory system Most significant byte is at lowest address ARM support three models of endianness. LE Little-Endian BE-32 Word Invariant Big-Endian BE-8 Byte invariant Big-Endian (introduced in architecture v6). 7 ARM Architecture and ARM Core Overview 1.3 ARM Instruction Set. All instructions are 32 bits long / many execute in a single cycle. Instructions are conditionally executed. A load / store architecture. Example data processing instructions SUB r0,r1,#5 ADD r2,r3,r3,LSL #2 ANDS r4,r4,#0x20 ADDEQ r5,r5,r6 Example branching instruction B r0 = r1 - 5 r2 = r3 + (r3 * 4) r4 = r4 AND 0x20 (set flags) IF EQ condition r5 = r5 + r6 Branch forwards true or backwards relative to current PC (+/- 32MB range) <Label> Example memory access instructions LDR r0,[r1] Load word at address r1 into r0 STRNEB r2,[r3,r4] IF NE condition true, store bottom byte of r2 to address r3+r4 STMFD sp!,{r4-r8,lr} Thumb Instruction Set: Thumb is a 16-bit instruction set Optimized for code density from C code (~65% of ARM code size) Improved performance from narrow memory Subset of the functionality of the ARM instruction set Switch between ARM and Thumb state using BX instruction For most instructions generated by compiler: Conditional execution is not used Source and destination registers identical Only Low registers used Constants are of limited size Inline barrel shifter not used 8 ARM Architecture and ARM Core Overview Thumb-2 Instruction Set: Thumb-2 is a major extension to the Thumb ISA Adds 32-bit instructions to implement almost all of the ARM ISA functionality Retains the complete 16-bit Thumb instruction set Supported by the ARM1156T2-S and Cortex Family Cortex-M3 supports only Thumb-2 Cortex-M1 supports a subset of Thumb-2 Design objective: ARM performance with Thumb code density No need to manually select instruction set split Reduces need to profile code and understand execution patterns Compiler can automatically select mix of 16 and 32 bit instructions Gives access to ARM state behaviour Exceptions may be handled directly Coprocessors can be accessed Advanced data handling of v5TE & v6 can be done Conditional Execution via If-Then (IT) instruction 1-4 following instructions conditionally executed Thumb 2 Performance / Density: 9 . 3.1 ARM Branches and Subroutines. LR will have to be stacked BX <register> Branch to address in register . ±32 MB range BL <subroutine> Stores return address in LR Returning implemented by restoring the PC from LR For non-leaf functions.ARM Architecture and ARM Core Overview Jazelle: Jazelle-enabled ARM cores execute 8-bit Java bytecode 95% of bytecodes executed in hardware (typical) Significantly more power-efficient 1. B <label> PC relative.with optional state change Used in this context as a return instruction 10 . 4 ARM Processor Cores.2 Coprocessors.1 The ARM7TDMI Processor Core.ARM Architecture and ARM Core Overview 1.4. 1.3. ARM7TDMI features T D M I 3 stage pipeline Von Neumann architecture CPI ~1.9 Thumb instruction set support 32-bit ARM instructions 16-bit Thumb instructions Debug support Enhanced multiplier (32x8) with instructions for 64-bit results EmbeddedICE Logic 11 . 1. Up to 16 coprocessors can be defined Expands the ARM instruction set ARM uses them for “internal functions” so as not to enforce a particular memory map (eg cp15 is the ARM cache controller) Usually better for system designers to use memory mapped peripherals Easier to implement. rather than serially. The PC points to the instruction being fetched. Optimal Pipelining. In this example it takes 6 clock cycles to execute 6 instructions. not the instruction being executed.ARM Architecture and ARM Core Overview The Instruction Pipeline. All operations here are on registers (single cycle execution). The ARM7 family uses a 3 stage pipeline in order to increase the speed of the flow of instructions to the processor. Clock cycles per Instruction (CPI) = 1 LDR Pipeline Example. 12 . Allows several operations to be undertaken simultaneously. 13 .ARM Architecture and ARM Core Overview Branch Pipeline Example. Interrupt Pipeline Example. 5 Improved maximum clock frequency Harvard architecture Increases available memory bandwidth Instruction memory interface Data memory interface Simultaneous access to instruction and data memory can be achieved Normally supplied with caches attached ARM922T (pictured) 2 x 8K caches Memory Management Unit (MMU) Write Buffer ARM920T As ARM922T but with 2 x 16K caches ARM940T Has a Memory Protection Unit (MPU) 14 .4. Architecture v4T 5 stage pipeline Improves CPI to ~1.2 ARM9TDMI.ARM Architecture and ARM Core Overview 1. MPU – Memory Protection Unit Controls memory access permissions Controls cacheable and bufferable attributes for memory regions MMU – Memory Management Unit Has all the features of an MPU Also provides Virtual to Physical address translation Cache Fast local memory Holds copies of recently accessed memory locations TCM – Tightly Coupled Memory Fast local memory Located at particular address range Write buffer Decouples writes to external 15 .ARM Architecture and ARM Core Overview Pipeline changes for ARM9TDMI. Cached Processor Terminology. 4.4 ARM10E Family Overview.4.ARM Architecture and ARM Core Overview 1. 1. 16 .3 ARM9E Processor Core. ARM Architecture and ARM Core Overview 1.6 ARM Cortex-M3 Processor. 17 . 1.5 ARM1136J(F)-S Overview.4.4. not instructions Interrupts automatically save/restore state Exceptions programmed in C No Coprocessor 15 All registers are memory-mapped Interrupt controller is part of Cortex-M3 macrocell 1.4.ARM Architecture and ARM Core Overview ARMv7M Architecture No ARM instruction set support Thumb-2 only No Cache . 18 .7 ARM Cortex-A8 Processor.No MMU Debug is optimized for microcontroller applications Vector table is addresses. 9 across 150+ ARM and industry benchmarks Custom / synthesizable design ARMv7 instruction set Integrated NEON media processor Unified level 2 cache 19 . dual-issue.ARM Architecture and ARM Core Overview Processor highlights High frequency. superscalar microprocessor Advanced dynamic branch prediction Average IPC of 0. high efficiency. low power In-order. 5 AMBA Advanced Microcontroller Bus Architecture aims to: Make life easier for systems designers Standardize the bus interface Reduce the support required From ARM Between internal design teams Allows increased re-use of IP in designs Enable the creation of upgrades and families of devices AMBA 2.0: AHB. Advanced High Performance Bus High performance: Full clock cycle to provide wait response Burst signals for optimal memory interface Split transaction for high access latency memory 20 .ARM Architecture and ARM Core Overview AXI interface 1. ARM Architecture and ARM Core Overview No overhead for arbitration or at start of bursts Single Cycle Bus Master Handover Data width extendable for high bandwidth Synthesis friendly Uses only rising edge of clock No combinatorial input to output paths STA and test insertion friendly No bias towards tri-state implementation No requirement for latches No state dependent timing parameters AHB Structure. 21 . More AMBA: Advanced Peripheral Bus (APB) Reduces loading on main system bus Low power.0) Design Objectives: Suitable for high-bandwidth & low-latency design High frequency without bridges Flexibility in interconnection architecture Good performance with long initial latency peripherals Backwards-compatibility with AHB & APB Features Separate address/control & data phases Support for unaligned data transfers Burst transaction based on start address issue only Separate read & write channels Multiple outstanding addresses Out-of-order transaction completion AXI Multi-Master System Design.0: AXI (AXI is the “AHB” component of AMBA3. with no requirement for a clock Suitable for synthesizable design 22 .ARM Architecture and ARM Core Overview AMBA 3. ARM Architecture and ARM Core Overview Robust with set-up and hold ensured by protocol Suitable for D-type or transparent latch based design Advanced System Bus Based on the original ARM bus interface Uses both clock edges Low silicon / interconnect overhead Interface used by ARM7x0T and ARM9x0T cores 1.6 Writing Software for ARM Processors.reduces space required in ROM Linker feedback mechanism .6.informs compiler of unused functions which can be eliminated in subsequent builds 23 . v7A and v7M) Support for Thumb-2 instruction set Data compressor . Full ISO C++ support (including exceptions) ABI compliant (see later) Support for latest architectures (v6. Tools: ADS (CodeWarrior).2 RealView Compilation Tools (RVCT) 3. RVDS. GNU. Keil. … 1.1 Keil uVision4. IAR.0 includes Highly optimising single ISO C/C++ compiler Ongoing code density and performance improvements with each release. armasm Linker .armar C and C++ libraries 24 .fromelf Librarian .armlink Format converter .ARM Architecture and ARM Core Overview Other Compilation Tool Components ARM / Thumb assembler . 2 Application Code and Data Size: 25 .ARM Architecture and ARM Core Overview 1.6. contain code and data whilst the application is executing One or more execution regions will be created from each load region during application startup The details of the memory map used by a scatterloaded application are contained in a description file which is passed as a parameter to armlink eg: armlink program.ARM Architecture and ARM Core Overview 1.o --scatter scatter. you will not want to load and execute your code at the default address Most embedded systems have memory devices spread across the memory map Scatterloading provides a way of placing your code and data into the appropriate locations in memory Scatterloading defines two types of memory region Load Regions .3 Introduction to Scatterloading: In a real application. Scatterloading (Simple Example): RO code and data stays in ROM C library initialization code (in __main) will : o copy RW data from ROM to RAM o initialize to zero the ZI data in RAM Scatter Description Files 26 .contain application code & data at reset/load time (typically ROM) Execution Regions .scat -o program.axf.6. For our example. support on the target By default uses semihosted SWI’s to access host debugger facilities e. Note that the linker placement rules discussed earlier apply to each execution region individually. In the RAM region. string. the following syntax describes our single load region. In this example. You must specify the contents of each execution region with the curly braces. There is an optional length parameter which can follow the address parameter. ANSI C library: Full file handling. the first is located in ROM.ARM Architecture and ARM Core Overview To explain the syntax of a scatter-file : In our scatter file we need to give both our load and execution regions a name.. In the EXEC_ROM region. We also need to specify a start address. maths. As you can see from the execution region names. The header syntax for execution regions is very similar to the header syntax for load regions. we make use of the wildcard (*) syntax which collects all sections with a given attribute. we collect all sections with the RO attribute. and the second is located in RAM. we collect all sections with either RW or ZI attributes. ¾ The best discussion of scatter file syntax can be found in the “RVCT Linker and Utilities Guide”. 1. file I/O 27 .6. (As shown in the diagram).g. etc.4 Supplied Libraries. so all RW code and data will be located before all ZI data. maths. etc. etc. low-level I/O provided by host debugger User provides replacement implementations of specific functions for embedded use Retargeting the C Library (1): You can replace the C library’s device driver lever functionality with an implementation that is tailored to your target hardware e. printf() should go to LCD screen. not debugger console 28 . support on the target The linker will automatically link in the correct library variants for your application Depending on endianess.. position independence.ARM Architecture and ARM Core Overview Retargetable without rebuilding whole library Automatic selection of the correct library variant C++ library includes: Libraries and Semihosting: Full file handling. string.g. By default “semihosting” is used to access host debugger facilities Library code runs on ARM target. floating point requirements. com/documentation 29 .ARM Architecture and ARM Core Overview To ‘Retarget’ the C library. simply replace those C library functions which use semihosting SWIs with your own implementations. the printf() family of functions (except sprintf()) all ultimately call fputc() The default implementation of fputc() uses a semihosting SWI Replace this with: extern void sendchar(char *ch).2nd edition edited by David Seal ARM DDI 0100E is latest.arm. application notes. write a character to an LCD */ char tempch = ch. } See retarget. sendchar(&tempch). FILE *f) { /* e. covering v5TE DSP extensions ISBN 0-201-737191 (Addison-Wesley) Steve Furber “ARM system-on-chip architecture” . white papers) http://www. int fputc(int ch. datasheets.2nd edition ISBN 0-201-67519-6 (Addison-Wesley) Sloss. ARM “Architecture Reference Manual” . return ch. Symes & Wright – “ARM System Developer's Guide” ISBN: 1-55860-874-5 (Morgan Kaufman) Documentation (TRMs. user guides. to suit your system For example.g.c in the examples directory for further examples of retargeting 1.5 Reference Material. . 9 1 Bộ điều khiển truyền nhận USB-A (host) on-chip. 9 4 kênh ADC 10 bit. SLC NAND Flash with ECC.Tốc độ 180MHz. 9 2 SRAM on-chip tốc độ cao.Ngoại vi. Static memories. 601/656 image sensor giao tiếp CMOS camera. 9 8 Kbytes bộ nhớ chương trình và 8 KBtytes bộ nhớ dữ liệu và MMU.AT91SAM9260 Sumary II. 9 1 Giao diện giao tiếp I2C (two wire interface . 9 1 Giao diện Memory Card Host tốc độ cao (SD/MMC card interface). CompactFlash. 9 1 Bộ điều khiển truyền nhận USB-B (device) on-chip. 30 . 9 4 USARTs. 9 Một ROM on-chip 32-kbyte.TWI). 9 1 bộ điều khiển nối tiếp đồng bộ (synchronous serial controller). AT91SAM9260 Đặc điển chính: .Bộ nhớ.Hệ thống (System). 9 Giao diện bus 32 bit hỗ trợ 4 bank SDRAM/LPSDR. 9 22 kênh DMA (direction memory access). (2 kênh cho QFP. 9 2 SPI hỗ trợ 2 chế độ Master/Slaver. bộ xử lý ARM926EJ-S hỗ trợ tập lệnh Thumb và ARM. 9 1 Bộ điều khiển 10/100 Mbps Ethernet MAC. và 4 kênh cho BGA). 9 1 Giao diện ITU-R BT. . . 9 2 UARTs. được nhúng sẵn bootstrap (level 1). mỗi SRAM 4-kbyte. 31 . 9 Bộ điều khiển ngắt cao cấp (AIC) và debug. 9 3 bộ điều khiển xuất nhập song song 32 bit. 9 Một PLL cho hệ thống. 9 Cho phép chọn tần số tiết kiệm năng lượng 32. 9 Cho phép cài đặt chế độ timer. 9 Hai tín hiệu xung đồng hộ ngoài có thể lập trình được. 9 Tích hợp bộ giao động nội RC 32 kHz năng lương thấp.1 Sơ đồ khối AT91SAM9260. DataFlash hoặc serial DataFlash.768 Hz và bộ giao động chính 3-20 MHz. 9 Bộ điều khiển reset (reset controller). .AT91SAM9260 Sumary 9 Khởi động (boot) từ NAND Flash. watchdog timer. 9 Ma trận bus AHB 6 lớp 32 bit hoạt động tần số 90MHz.Khối xuất nhập (I/O). 9 96 đường I/O đa mục đích. và một cho USB. 2. real time timer. SDCard. Bảng 2-1: Các tín hiệu không có trên kiểu chân PQFP. Bảng 2-3: Đặc tả các tín hiệu: 32 .AT91SAM9260 Sumary Bảng 2-2: Sơ đồ khối AT91SAM9260. 2.2 Bảng đặc tả các tín hiệu. AT91SAM9260 Sumary 33 . AT91SAM9260 Sumary 34 . AT91SAM9260 Sumary 35 . 3 Bảng đặc tả các chân.AT91SAM9260 Sumary 2.pdf) Bảng 2-4: Bảng mô tả chân 208-PQFP 36 . (page 10 of doc6221. VDDCORE pins: Power the core. VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface. voltage ranges between 1.65V to 1.8V nominal.0V and 3. voltage ranges from 1. voltage ranges from 3. voltage ranges from 1. VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers.0V and 3. The expected voltage range is selectable by software. 1. 2.65V and 1.8V typical) or between 3. VDDANA pin: Powers the Analog to Digital Converter.1 Power suplies.AT91SAM9260 Sumary 2.95V.8V nominal. VDDBU pin: Powers the Slow Clock oscillator and a part of the System controller. 3. 1.95V (1. voltage ranges from 1. voltage ranges from 1. 3V or 3.6V. 1.5V. including the processor.65V and 1.3V nominal. 37 .95V.4 Power considerations.8V.65V and 1.6V.0V and 3. voltage ranges from 3.4. 2. VDDIOM pins: Power the External Bus Interface I/O lines.95V.3V nominal. VDDPLL pin: Powers the Main Oscillator and PLL cells.8V nominal.3V nominal. the embedded memories and the peripherals.6V.65V and 3.3V nominal). 1. 3V or 3.6V (3. VDDPLL and VDDANA. VDDIOP0 and VDDIOP1 pins power supplies. • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration. – Write-through and Write-back Operation. GNDPLL and GNDANA. – Eight words per line.AT91SAM9260 Sumary The power supplies VDDIOM.768 Hz startup delay is 1200 ms whereas it is 240 µs for the internal RC oscillator. ARM926EJ-S Processor. VDDIOP0 and VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. – ARM High-performance 32-bit Instruction Set. • Two Instruction Sets. OSCSEL Slow Clock Startup Time 0 Internal RC 240 µs 1 External 32768 Hz 1200 ms16 The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. 2. The 32. • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 8-Kbyte Data Cache. – Thumb High Code Density 16-bit Instruction Set.5 Processor and architecture. Ground pins GND are common to VDDCORE. • DSP Instruction Extensions.768 Hz crystal or the on-chip RC oscillator. – Pseudo-random or Round-robin Replacement. Separated ground pins are provided for VDDBU. 38 . The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the device. VDDIOM. Slow Clock Selection: The AT91SAM9260 slow clock can be generated either by an external 32. These ground pins are respectively GNDBU. 8-Kbyte Instruction Cache: – Virtually-addressed 4-way Associative Cache. – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory. • Bus Interface Unit (BIU). – Arbitrates and Schedules AHB Requests. The Bus Matrix of the AT91SAM9260 manages six Masters. • Standard ARM v4 and v5 Memory Management Unit (MMU). Bus Matrix: has a 6-layer Matrix. handling requests from 6 masters Boot Mode Select. all the masters have the same decodings. – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset Remap Command. – 16 embedded domains. – Allows Handling of Dynamic Exception Vectors. – Access Permission for large pages and small pages can be specified separately for each quarter of the page. – Separate Masters for both instruction and data access providing complete Matrix system flexibility. data can be 8-bit (Bytes). – On Address and Data Buses. – Separate Address and Data Buses for both the 32-bit instruction interface and the 32bit data interface. which means that each master can perform an access concurrently with others. 39 . 16-bit (Half-words) or 32-bit (Words).AT91SAM9260 Sumary • Write Buffer. – Access Permission for Sections. In order to simplify the addressing. Each Master has its own decoder that can be defined specifically for each master. according the slave it accesses is available. Peripheral DMA controllers: Twenty-two channels. such as allowing access from the Ethernet MAC to the Internal Peripherals. these paths are forbidden or simply not wired. and shown “-” in the following table. 40 . – Two for the Debug Unit. some paths do not make sense. – One for Analog-to-Digital Converter. – Two for each USART. However. Prefer to the datasheet for details of informations. thus allowing a different arbitration per Slave to be programmed. Master to Slave Access: All the Masters can normally access all the Slaves. – Two for each Serial Peripheral Interf. – One for Multimedia Card Interface.AT91SAM9260 Sumary Each Slave has its own arbiter. Thus. – Two for each Serial Synchronous Co. 41 .AT91SAM9260 Sumary 2.6 Memories. thus allowing a different memory mapping per Master. Regarding Master 0 and Master 1 (ARM926 Instruction and Data). and a second level of decoding provides 1 Mbyte of internal memory area.7 Peripherals.AT91SAM9260 Sumary Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. 2. one after remap. three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot. 2. However. one for external boot. Each Master has its own bus and its own decoder. 42 . The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. all the masters have a similar address decoding. Bank 0 is reserved for the addressing of the internal memories.7.1 Identifiers A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. in order to simplify the mappings. UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect.7. All external interrupt signals. • the Power Management Controller. • the Real-time Timer.7.2. However.2 External interrupts. i.7.7. 2.3 Peripheral signal multiplexing on I/O lines. 43 . SYSC. there is no clock control associated with these peripheral IDs. • the Reset Controller. The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller. 2. • the Debug Unit..e. use a dedicated Peripheral ID.1 System interrupt. the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2. The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. • the Periodic Interval Timer.2 Peripheral interrupts and clock control. 2. 2. • the Watchdog Timer.2.AT91SAM9260 Sumary Setting AIC.2. AT91SAM9260 Sumary 44 . AT91SAM9260 Sumary 45 . AT91SAM9260 Sumary 46 . write protect | I/O[7:0] or I/O[15:0] – data bus 47 . Chính vì thế rất nhiều vi xử lý có thể sử dụng NOR flash như vùng nhớ thực thi chương trình (execute place memory). nghĩa là chương trình lưu trong NOR flash có thể thực hiện trực tiếp từ NOR flash mà không cần copy lên RAM để chạy. thẻ nhớ.write enable | WE# .command latch enable – A[20:0] .write enable R/B# .1 Flash Overview. MP3 players và solid-state drives với mục đích chung là lưu trữ và truyền dữ liệu giữa máy tính với các thiết bị số khác. đối với các NOR flash cũ không hỗ trợ chức năng này mà software or device driver sẽ làm công việc này. v.data bus | CLE . Each page are a few bytes (typically 1/32 of the data size) that can be used for storage of an ECC (error correcting code) checksum. NOR: đọc bộ nhớ NOR flash giống như đọc bộ nhớ RAM và có giao diện data bus và address bus giống RAM. California. NAND Flash: được truy xuất giống như block devies như ổ đĩa cứng. Quản lý bad block là một đặc điểm mới của NOR flash. có thể xóa và lập trình lại bằng điện.chip enable WP# .ready / busy – OE# . The pages are typically 512.output enable | RE# . Flash là bộ nhớ không bay hơi (non-volatile storage chip).chip enable | CE# . Each block consists of a number of pages.address latch enable – WP# .write protect – WE# . NOR | NAND – CE# . Bộ nhớ Flash được sử dụng nhiều trong memory card.NAND Flash Support in AT91SAM9 Microcontrollers III. Điển hình là EEPROM (electrically erasable programmable read-only memory). 4096 bytes in size.v… Lịch sử bộ nhớ Flash (both NOR and NAND) được phát minh bởi tiến sĩ Fujio Masuoka năm 1980 khi đang làm việc cho TOSHIBA và được trình bày tại hội nghị điện tử quốc tế IEEE năm 1984 tại San Francisco. NAND Flash Support in AT91SAM9 Microcontrollers 3. 2048.read enable PRE – power on RE – D[15:0] . USB Flash drives.address bus | ALE . 1 8-bit NAND Flash on AT91SAM9260. 3.2. (256MB) Bảng cấu hình hệ thống: 3.NAND Flash Support in AT91SAM9 Microcontrollers 3. 48 .2. NAND Flash được điều khiển bởi SMC của AT91 ở tầm địa chỉ NCS3 (0x40000000 – 0x4FFFFFFF).2 NAND Flash Connection on AT91SAM9260.2 16-bit NAND Flash on AT91SAM9260. NAND Flash Support in AT91SAM9 Microcontrollers 49 . gọi tắt "Rambus".pdf của atmel. mỗi bit nhớ được thiế kế bởi cổng logic với 6 transistor MOS.1 RAM Overview.bộ nhớ truy xuất ngẫu nhiên. 64-bit.Using SDRAM on AT91SAM9 Microcontrollers IV. 4. Using SDRAM on AT91SAM9 Microcontrollers tham khảo doc6256. gọi tắt DDR. Do vậy sau mỗi lần đọc một ô nhớ. gọi tắt SDR. sử dụng kỹ thuật MOS. DDR III SDRAM (Double Data Rate III SDRAM): DDR3. 4. DDR2 và DDR3. gọi tắt DDR2. 1. DDR SDRAM (Double Data Rate SDRAM). DDR2 SDRAM (Double Data Rate 2 SDRAM). DDR. Mỗi bit nhớ gồm một transistor và một tụ điện. Đặc tính: RAM (random access memory) . Việc ghi nhớ dữ liệu dựa vào việc duy trì điện tích nạp vào tụ điện và như vậy việc đọc một bit nhớ làm nội dung bit này bị hủy.2 SDRAM Controller on AT91SAM9 Overview. + RDRAM ( Rambus Dynamic RAM). 50 . SDRAM hiện có các loại: SDR. Phân loại: SRAM (Static RAM): được chế tạo theo công nghệ ECL (CMOS or BiCMOS). Có một số loại DRAM sau: + SDRAM ( Synchronous Dynamic RAM) .5V. cần tham khảo thêm XDR memory architecture. RAM còn được hiểu là bộ nhớ RW (read/write memory) và khác với bộ nhớ ROM. bộ phận điều khiển bộ nhớ phải viết lại nội dung ô nhớ đó. tốc độ cao và giao diện kết nối đơn giản. Lưu chương trình và dữ liệu trong suốt quá trình thực thi. Vì thế giao diện kết nối DRAM có thêm tín hiệu Autorecharge (auto-refresh). DRAM (Dinymic RAM). - SDR SDRAM (Single Data Rate SDRAM).DRAM đồng bộ. AT91 cung cấp một tín hiệu output SDA10 chuyên dụng cho phép hệ thống kích hoạt tính năng tự động precharge mà không ảnh hưởng bus địa chỉ. Kích thước memory page từ 2048 .4. 16 và 32 bit data. Tự làm tươi (self . giao diện 16-bit or 32-bit SDRAM. 4. AT91 cung cấp NCS1 trong không gian bộ nhớ để kết nối với 16-bit hoặc 32bit SDRAM ngoài. NBS[3:0]: tín hiệu mặt nạ dữ liệu tương ứng truy xuất 8. SDRAMC_A[12:0] quản lý địa chỉ lên tới 11 columns và 3 row. SDRAMC_A[12:0]: các đường địa chỉ của SDRAMC tương ứng với [A2:A14] của vi xử lý ngoại trừ SDRAMC_A10 (SDA10). DW bit trong thanh ghi cấu hình SDRAMC sẽ chọn 16-bit hoặc 32-bit bus width.4192 và số column là 256 2048. half-word (16-bit) và word (32bit). 4. Giao diện 32-bit SDRAMC có thể kết nối với một 32-bit SDRAM hoặc hai 16-bit SDRAM. SDA10: làm việc như là một đường địa chỉ SDRAM nhưng cũng được sử dụng như là auto-precharge command bit.3 SDRAM Controller Signals Definition. SDRAMC cho phép truy xuất word burst (no byte or half word bust).1 SDRAM 16-bit Connection.refresh). 51 . 4.Using SDRAM on AT91SAM9 Microcontrollers SDRAMC là bộ điều khiển mở rộng bộ nhớ của 1 chip. SDRAMC cho phép truy xuất byte (8-bit).4 SDRAM Connection on AT91SAM9. Using SDRAM on AT91SAM9 Microcontrollers 4.4. 8-word burst access.5 ARM926EJ-S Access. Single access. 52 .2 SDRAM 32-bit Connection 4. 4-word burst access. Schematic of SAM9260-EK 53 .Schematic of SAM9260-EK V. .31] PA9 SERIAL SERIAL MCI EEPROM DATAFLASH DATAFLASH DAC 5VDC POWER SUPPLY TXD3 TXD2 TXD1 TXD0 TX_EN PA19 E TXC K/RE F C LK PA11 PA10 PA13 PA12 PA16 E TX3 E TX2 E TX1 E TX0 E TXE N PA26 PA25 PA15 PA14 E RX3 E RX2 E RX1 E RX0 PA27 PA17 E RXC K E RXD V PA22 PA18 E TXE R E RXE R PA29 PA28 EC O L E C RS PA20 PA21 PA7 EMDC E M D IO P IO SDCK SDCKE CFWE_NWE_NWR0 RXD3 RXD2 RXD1 RXD0 RX_CLK RX_DV TX_ER RX_ER COL CRS MDC MDIO MDINTR NRST 03 .31] PB[0.31] PB[0.31] RMII_MII ETHERNET TX_CLK 10/100 Mbps FAST ETHERNET A[0.....31] A[0.RMII_MII ETHERNET NBS1 NBS3 CFOE_NRD NANDOE NANDWE NCS0 NRST PA[0.31] A[0.22] SDCK SDCKE SDCK SDCKE NBS1 NBS3 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 A16 A17 PB[0..Schematic of SAM9260-EK D[0.AT91SAM9260 RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 CFOE_NRD NANDOE NANDWE NCS0 NRST PA[0...14] SHDN PC1 PB18 PB17 PB16 PCK0 TD0 TF0 TK0 PB0 PB1 PB2 PB3 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 NRST RAS CAS SDA10 SDWE SDCS_NCS1 RAS CAS SDA10 SDWE SDCS_NCS1 PC[0...22] 05 .15] NRST PA[0.15] VREFP AVDD AGND NRST 02 .14] SDRAM POWERLED MEMORY AT91SAM9260 PIO NANFLASH PA[0.15] MCLK SDIN LRFS BCLK D[0...31] A[0..31] A[0..15] USBCNX DDM DDP PC5 PA0 PA5 PA4 PA3 PA8 PA1 PA2 PC11 NRST PIO TWCK TWD DDM DDP DEVICE USB A22 A21 NANDOE NANDWE PC14 PC13 HOST A HDMA HDPA HDMA HDPA HOST B HDMB HDPB HDMB HDPB PA24 PA23 RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 BA0 BA1 CLE ALE NANDOE NANDWE NANDCS RDY BSY D[0.31] PC[0.31] PC[0...22] SHDN AT73C213 DOUT DIN CLK CS NRST D[0.31] RS232 SERIAL INTERFACES DBGU DTXD DRXD COM0 TXD0 RXD0 RTS0 CTS0 DTR0 DSR0 DCD0 RI0 COM1 TXD1 RXD1 RTS1 CTS1 PB15 PB14 NANDOE NANDWE D BG U _TXD D BG U _RXD PIO PIO PB4 PB5 PB26 PB27 PB24 PB22 PB23 PB25 D[0..COMMUNICATION RAS CAS SDA10 SDWE SDCS_NCS1 PA[0...15] DAT0 DAT1 DAT2 DAT3 CLK CMD CARD READER SCK CS NRST SCL SDA 03 .31] PC[0...EXPANSION CONNECTORS 54 ..31] 01 ...15] SPI0_MISO MCDB0 MCDB1 MCDB2 SPI0_NPCS0 MCDB3 MCCK SPI0_MOSI MCCDB PB6 PB7 PB28 PB29 SPI0_SPCK SPI0_NPCS1 PC[0...15] VREFP AVDD AGND 06 .31] PB[0.POWER SUPPLY PB[0.MEMORY EXPANSION & User's Interf aces D[0. Schematic of SAM9260-EK Power Suppy. C10 10PF 1 3 5 7 9 11 DS1 2 4 6 8 10 12 J4 MCLK SDIN LRFS BCLK NRST 5V POWER LED 5V U3 3 S8 REGULATED C15 10µF 1 2 2 C11 10µF C12 10PF 5V_USB 3 J1 2 1 2 1 5V ONLY Output 4 1 S7 Vout Input Ajd/Gnd 5V 1V8 L1117_1V8 5.1. SSC Connector 5V R3 100K U2 L1117_3V3 Input + C1 330µF Vout C8 10µF Output AUDIO DAC INTERFACE 1k 4 DOUT DIN CLK 3V3 CS 2 C9 10µF 1 CR1 5V R1 3V3 3 Ajd/Gnd 5. 55 .2. AT91SAM9260 (PQFP package). 432MHz C24 10PF 2 R23 10K N.31] PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 D[0..15] NRST R24 100K 3V3 NRST R25 100K 55 54 DDP DDM 51 50 HDPA HDMA J5 1 3 5 7 9 11 13 15 17 19 ICE_NTRST PC13 PC14 PC15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 56 59 127 128 129 130 131 134 135 136 137 138 139 140 141 142 143 144 145 S1 ICE_RTCK NRST HDPA HDMA 0R 30 31 34 37 29 43 NTRST 35 R13 3V3 S2 TDI TMS TCK RTCK TDO JTAGSEL RAS CAS NTRST SDWE SDA10 SDCKE SDCK S3 152 JTAG R15 C19 10NF C20 1NF SDCS/NCS1 NCS0 PLLRCA CFOE/NRD 148 1V8 C21 100NF 151 155 C22 100NF 153 150 C23 10PF CFWE/NWE/NWR0 CFIOR/NBS1/NWR1 CFIOW/NBS3/NWR3 VDDPLLB GNDPLLB NANDOE NANDWE VDDPLLA NRST C25 10PF 45 1 149 106 107 108 109 110 111 112 118 119 120 121 122 123 124 125 126 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 99 98 97 96 95 94 93 92 89 88 87 86 85 84 83 82 81 80 79 76 75 74 73 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 105 104 XOUT BMS TST 69 VREFP XOUT32 VDDIOP1 169 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 199 187 52 32 24 VDDIOP0 VDDIOP0 13 5 VDDIOM VDDIOM VDDIOM VDDIOM 132 114 90 65 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 6 14 25 33 39 53 66 78 91 113 133 146 170 173 188 200 204 VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE 203 174 147 77 38 VDDBU GNDBU 44 48 OSCSEL SHDN XIN32 47 41 WAKE UP 3V3 BP2 R16 1K CFOE_NRD 70 102 101 71 72 CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 BP1 NANDOE NANDWE RESET 36 NRST 40 100K 3V3 J7 R19 42 BOOT M ODE SELECT OPENED :EMBEDDED ROM CLOSED : EBI_NCS0 1K XIN WKUP 46 3V3 SDCS_NCS1 NCS0 R17 49 32.Schematic of SAM9260-EK PC[0.C 1K 154 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NBS0/A0 NWR2/NBS2/A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0/A16 BA1/A17 A18 A19 A20 A21 A22 AT91SAM9260 DDP DDM A[0.31] 160 156 C49 100NF R21 C48 100NF AVDD 0R L2 C29 10µF 10V 3V3 4.768 kHz SDWE SDA10 SDCKE SDCK 103 68 R26 100K AVDD AGND VREFP 157 Y2 C26 10PF RAS CAS 116 100 117 115 GNDPLLA Y1 18...7µH C30 100NF C31 10µF 10V 0R R22 AGND 1V8 C37 10µF C50 100NF C51 C53 C55 100NF 100NF 100NF C52 C54 100NF 100NF C38 10µF C56 C58 C60 C62 C64 C66 100NF 100NF 100NF 100NF 100NF 100NF C57 C59 C61 C63 C65 100NF 100NF 100NF 100NF 100NF C67 100NF 56 .22] NCS6/FIQ/PC13 IRQ2/NCS3_NANDCS/PC14 IRQ1/NWAIT/PC15 SPI0_NPCS2/D16/PC16 SPI0_NPCS3/D17/PC17 SPI1_NPCS1/D18/PC18 SPI1_NPCS2/D19/PC19 SPI1_NPCS3/D20/PC20 EF100/D21/PC21 TCLK5/D22/PC22 D23/PC23 D24/PC24 D25/PC25 D26/PC26 D27/PC27 D28/PC28 D29/PC29 D30/PC30 D31/PC31 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 62 67 63 64 61 60 58 57 SPI1_NPCS2/A23/PC4 SPI1_NPCS1/A24/PC5 CFCE1/TIOB2/PC6 CFCE2/TIOB1/PC7 RTS3/NCS4_CFCS0/PC8 TIOB0/NCS5_CFCS1/PC9 CTS3/A25_CFRNW/PC10 SPI0_NPCS1/NCS2/PC11 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 21 22 23 26 27 28 163 164 165 166 167 168 171 172 175 176 177 178 158 PC0 159 PC1 SCK3/AD0/PC0 PCK0/AD1/PC1 PA0/SPI0_MISO/MCDB0 PA1/SPI0_MOSI/MCCDB PA2/SPI0_SPCK PA3/SPI0_NPCS0/MCDB3 PA4/RTS2/MCDB2 PA5/CTS2/MCDB1 PA6/MCDA0 PA7/MCCDA PA8/MCCK PA9/MCDA1 PA10/MCDA2/ETX2 PA11/MCDA3/ETX3 PA12/ETX0 PA13/ETX1 PA14/ERX0 PA15/ERX1 PA16/ETXEN PA17/ERXDV PA18/ERXER PA19/ETXCK PA20/EMDC PA21/EMDIO PA22/ADTRG/ETXER PA23/TWD/ETX2 PA24/TWCK/ETX3 PA25/TCLK0/ERX2 PA26/TIOA0/ERX3 PA27/TIOA1/ERXCK PA28/TIOA2/ECRS PA29/SCK1/ECOL R27 100K R28 100K 2 4 6 8 10 12 14 16 18 20 179 180 181 182 183 184 185 186 189 190 191 192 193 194 195 196 197 198 201 202 205 206 207 208 1 2 3 4 7 8 DRXD/PB14 DTXD/PB15 TCLK3/TK0/PB16 TCLK4/TF0/PB17 TIOB4/TD0/PB18 TIOB5/RD0/PB19 ISI_D0/RK0/PB20 ISI_D1/RF0/PB21 ISI_D2/DSR0/PB22 ISI_D3/DCD0/PB23 ISI_D4/DTR0/PB24 ISI_D5/RI0/PB25 ISI_D6/RTS0/PB26 ISI_D7/CTS0/PB27 ISI_PCK/RTS1/PB28 ISI_VSYNC/CTS1/PB29 ISI_HSYNC/PCK0/PB30 ISI_MCK/PCK1/PB31 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 TIOA3/SPI1_MISO/PB0 TIOB3/SPI1_MOSI/PB1 TIOA4/SPI1_SPCK/PB2 TIOA5/SPI1_NPCS0/PB3 TXD0/PB4 RXD0//PB5 TCLK1/TXD1/PB6 TCLK2/RXD1/PB7 TXD2/PB8 RXD2/PB9 ISI_D8/TXD3/PB10 ISI_D9/RXD3/PB11 MN6 PA[0.31] 9 10 11 12 15 16 17 18 19 20 161 162 PB[0... 3. 57 . Memories.Schematic of SAM9260-EK 5. C N.C N.Schematic of SAM9260-EK SDRAM D[0.C N.C N..7] MN6B1 16 17 8 18 9 CLE ALE NANDOE NANDWE NANDCS CLE ALE RE WE CE S6 7 19 R33 470K 3V3 RDY BSY 3V3 R35 1K R41 470K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 R/B WP N.C N.C N.C N.C N...14] 23 24 25 26 29 30 31 32 33 34 22 35 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 20 21 BA0 BA1 36 40 A14 37 SDCKE 38 SDCK N BS 0 A0 CFIOR_NBS1_NWR1 17 18 CAS RAS 3V3 R29 470K 15 39 16 19 SDWE A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C N.C N.15] 3V3 MN7 A[0.C N.C N.C VDD VDD CKE VDD VDDQ VDDQ CLK VDDQ VDDQ DQML DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ SDCS_NCS1 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 R44 10K R45 10K MN10 6 5 SCL SDA 8 3V3_Memory C86 100NF 4 SCL SDA A0 A1 NC 1 2 3 VCC GND WP 7 SERIAL EEPROM 3V3 3V3 R37 470K C68 C70 C72 C74 100NF 100NF 100NF 100NF C69 C71 C73 100NF 100NF 100NF 3V3 MN9 S5 8 1 2 4 SCK CS 256 Mbits 3 NRST D[0.C N.C PRE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VCC VCC 29 30 31 32 41 42 43 44 D0 D1 D2 D3 D4 D5 D6 D7 GND RESET WP C82 100NF 7 5 3V3 48 47 46 45 40 39 38 35 34 33 28 27 37 12 R43 10K J13 DAT1 DAT0 CLK 3V3_Memory CMD DAT3 DAT2 3V3 C84 100NF VSS VSS VCC SERIAL DATAFLASH 8-bit bus width I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 SO SI SCK CS 6 36 13 C83 100NF C85 100NF FPS009 8 7 6 5 4 3 2 1 9 SD CARD / MMC CARD DATAFLASH CARD INTERFACE NANDFLASH 58 . C 742792093 C93 10V 10µF R53 49R9 1% R54 49R9 1% C101 10µF 10V 13 TX- 2 3 RD+ RX+ 3 RX- 6 C102 100NF 75 75 75 7 NC 4 5 GND_ETH 1nF 75 8 7 C95 100NF 8 J00-0061NL GND_ETH GND_ETH 3V3 47 48 31 11 12 13 14 VCCA C94 100NF 5 6 46 DVDD DGND DGND DGND 2 TD- 6 RDL3 AVDDR AVDDR MDC MDIO MDINTR 1 5 CT TX_ER/TXD4 RX_ER/RXD4/RPTR COL/RMII CRS/PHYAD4 TX+ VCCA RX_CLK/10BTSER RX_DV/TESTMODE 3V3 10K J14 1 TD+ 7 4 CT TX- RXD3/PHY AD3 RXD2/PHY AD2 RXD1/PHY AD1 RXD0/PHY AD0 R52 49R9 1% R58 6. MII_Ethernet.Schematic of SAM9260-EK 5.80K 1% 9 RX_CLK RX_DV TX+ R51 49R9 1% 10 34 37 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK/ISOLATE 43 11 26 27 28 29 RXD3 RXD2 RXD1 RXD0 XT1 12 17 18 19 20 21 22 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK REF_CLK/XT2 14 MN11 42 3V3 3V3 R103 1K R102 1K Yellow R101 1K Green 3V3 45 C99 10µF 10V R64 0R RJ45 ETHERNET CONNECTOR R65 0R GND_ETH 59 . C88 22PF C89 22PF Y4 25MHz 1 2 C90 100NF GND_ETH 16 38 TX_ER RX_ER 3V3 R127 10K 36 35 COL CRS 24 25 32 MDC MDIO MDINTR 39 R56 3V3 C96 100NF C97 100NF 30 C98 100NF 23 41 15 33 44 10 NRST 40 8 RX+ 3 RX- 4 DISMDIX DVDD 1 VCCA DM9161AEP AVDDT AGND AGND AGND BGRESG DVDD PWRDWN RESET C91 100NF C92 100NF 2 9 BGRES LEDMODE LED0/OP0 LED1/OP1 LED2/OP2 CABLESTS/LINKSTS N.4. 60 . 5V J16 USB-A F2 6 5 A 4 3 2 500 mA USB HOST INTERFACE 1 C110 47pF Female C111 47pF 39R R66 39R R67 HDMA HDPA COM_DEBUG 3V3 R71 15K R70 15K C109 100NF J13 1 3 5 R79 100K N OT POPU LATED J11 2 4 6 5 2 3 R68 100K MN12 DRXD DTXD 5V_USB U S B_C N X USBCNX 6 C104 100NF 2 39R R89 4 3 39R R90 5 R1IN T1OUT R2OUT T2IN R2IN T2OUT C105 100NF 15 C107 100NF C1+ VCC C1V+ C2+ VC2- 13 14 8 7 COM_USER Debug:1-3. 6-4 4 5 C106 100NF GND MAX3232 USB DEVICE INTERFACE C119 33PF 1 6 16 2 R87 1.Schematic of SAM9260-EK 5. 2-4 1 3 C103 100NF User:5-3.6. Serial Interfaces.5. Expansions and User’s Interfaces.5K R1OUT T1IN 3V3 R84 22K 3V3 N OT POPU LATED J19 9 10 RXD0 TXD0 15K R81 C120 100NF 12 11 C123 15PF DDM DDP C124 15PF Female 5. .Schematic of SAM9260-EK PA[0.31] PA0 PA2 PA4 PA6 PA8 PA10 PA12 PA14 PA16 PA18 PA20 PA22 PA24 PA26 PA28 PA30 PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 PB1 PB3 PB5 PB7 PB9 PB11 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 PC[0..31] PB[0..15] PB0 PB2 PB4 PB6 PB8 PB10 PB12 PB14 PB16 PB18 PB20 PB22 PB24 PB26 PB28 PB30 PC5 PC7 PC9 PC11 PC13 PC15 PC0 PC2 PC4 PC6 PC8 PC10 PC12 PC14 PC1 PC3 PC5 PC7 PC9 PC11 PC13 PC15 J25 5V AVDD AGND PC4 PC6 PC8 PC10 PC12 PC14 1 3 5 7 9 11 13 PC0 PC15 PB9 PB11 2 4 6 8 10 12 14 PC1 PB8 PB10 PB16 3V3 VREFP COM IRQ1 ADC 3V3 J24 3V3 1V8 C130 100NF C131 10V 10µF C133 100NF SPI1_MISO SPI1_SPCK SPI1_NPCS1 GPIO C132 10V 10µF PIO_CNTRL1 TWCK ISI_DATA[1] ISI_DATA[3] ISI_DATA[5] ISI_DATA[7] ISI_DATA[9] ISI_DATA[11] PC4 PA24 PB21 PB23 PB25 PB27 PB11 PB13 R108 0R R109 0R PB1 PB3 PC4 PC7 SPI1_MISO SPI1_NPCS0 SPI1_NPCS2 GPIO LEDS & USER INTERFACE 3V3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 4 6 8 10 SPI Expand J28 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 1 3 5 7 9 PB0 PB2 PC5 PC6 PB19 PA23 PB31 PB29 PB30 PB28 PB20 PB22 PB24 PB26 PB10 PB12 IMAGE SENSOR CONNECTOR PIO_CNTRL2 TWD ISI_MCK ISI_VSY NC ISI_HSY NC ISI_PCK ISI_DATA[0] ISI_DATA[2] ISI_DATA[4] ISI_DATA[6] ISI_DATA[8] ISI_DATA[10] GREEN R118 220R PA6 DS5 PC15 BP3 R187 PB20 LED1 R188 220 PB21 LED2 R189 220 PB22 LED3 R190 220 PB23 LED4 220 61 . 3. 62 . 32MB SDRAM. Expansion Connector. Five LEDs.36. Angstrom. USB host.Development Tools VI. JTAG connector. SAM9260-EK Descriptions Features: - MCU AT91SAM9260. Ethernet 10/100 base RJ45 connector. U-Boot-2010.4. Micro SD/MMC card slot. 256MB NAND FLASH.30. Debian rootfs…. … Buildroot 2010.1. 512kB SPI serial dataflash. device connector. RS232 connector: user + debug.27. Three buttons: RST. Softwares: - - AT91BootStrap-1. 16/32 bit ARM926EJ-S 180Mhz.09. WAKEUP. U-Boot-2009. Linux-2. 5 VDC power supply from adapter or USB-B conector.6.6. Appication: Standalone (firmware). IRQ1.6.1 U-Boot-1. Linux-2.09 Linux-2. application in Embedded linux. 2-4: to select COM debug 5-3.3. Header comments S1 S2 S3 S5 S6 Default Open Open Open Open Close Close J13 Option S7 S8 Option Option J7 Close Boot from EBI_NCS0 CS data flash CS nand flash 1-3.2. Serial DataFlash: Items Bootstrap code Offset Comments 0x0 <= 4 KByte Environment 0x4200 U-Boot 0x8400 To end of capacity NandFlash: Địa chỉ offset 0x00000000 0x00300000 Kernel Rootfs (JFFS2) 6. Map of Memories In SAM9260-EK. NANDFLASH: 63 . Partition in The System. 6.1.Development Tools 6.3.3. 6-4: to select COM user Power supply from the 5Vdc adaptor Power supply from the USB-B cable Open Boot from embedded rom disconnect CS data flash disconnect CS nand flash 6.DataFlash SPI0_NPCS1 0xD0000000 Logical Capacity 6. Items Chip Select Address Comments Part number SDRAM nCS1 0x20000000 Physical MT48LC16M16A2 32MB NANDFLASH nCS3 0x40000000 Physical K9F2G08UOM 256MB AT45DB041D-SU 512KB Se.2 The second level bootstrapcode in NandFlash.1 The second level bootstrapcode in serial DataFlash. Development Tools Địa chỉ offset 0x00000000 0x00020000 0x00008400 0x00200000 0x00500000 Bootstrap U-boot Environments Application Standalone Kernel Rootfs (JFFS2) 64 . 1> Open S7&S8 after pluging the USB cable in the board. Software Development Tools 7. 2> Open S5 (if bootstrapcode in AT45DB041D-SU) or Open S6 (if bootstrapcode in NAND). 6> Running the SAMBA Step 1: select the board and protocol for connection.Development Tools VII.1. o Chép thư mục “ATMEL Corporation” đè lên thư mục C:\Program Files\ ATMEL Corporation\ đây là bước custom AT91-Board theo thiết kế của mình o Quá trình cài đặt SAMBA thành công. Click ‘Connect’ 65 . o Install AT91-ISP v1. 3> Close S8 to supply the power by the USB-B cable.exe.9\drv 7.13\sam-ba 2.1. SAM-BA (phần mềm nạp code).13. 5> Close S5. Nạp Bootloader vào board bằng SAM-BA.1.1. 4> Installation driver of SAM-BA for the system.. Chú ý: driver của USB-B của các device AT91 của hãng atmel nằm trong thư mục C:\Program Files\ATMEL Corporation\AT91-ISP v1. Bước 4: Trong text box "Send File Name".bin (đính kèm trong đĩa CD). ấn nút Execute để khởi động AT45DB041D SPI serial dataflash. ấn nút browse và trỏ đến file u-boot. ấn nút Execute. Bước 3: Trong list box "script" chọn "Send Boot File". browse đến thư mục chứa AT91BootStrap. 66 . Ấn nút reset và hệ thống có thể boot bình thường.bin (đính kèm theo đĩa CD) và chọn file này. Ấn nút "Send File" để hoàn tất việc nạp u-boot vào SPI serial dataflash. trong list box "script" chọn "Enable Dataflash (SPI0 CS1)". Chương trình SAMBA sẽ tự động nạp AT91BootStrap vào SPI dataflash tại địa chỉ offset 0.Development Tools Flash the bootloader into serial Dataflash: Step 2: Chọn tab DataFlash AT45DB/DCB. Trong text box "Address" gõ vào địa chỉ 0x8400.