1OfSARINC 429 DATA CONCENTRATOR C. PITOT C.C-VAUBOIS M. PROST L. POT SEXTANT Avionique - B.P. 59 - 78140 Velizy-Villacoublay - FRANCE Abstract - This paper presents the hardware architectural concept of ARlNC 429 Data concentrators which are used by SEXTANT Avionique Company for both the A320 and A3401330 commercial transport airplanes. in respect to these guidelines, a family of inter-compatible clrcuits were designed in order to tit a very wide ARlNC 429 application panel. Then, we present their features and the methodology used during their design. 1. INTRODUCTION Third : High level new functions were needed such as : . ARlNC data timing control and message dating . Multiword message management in fifo-like files. Fourth : An implicit need was of course to lead to a good system safety from the failure mode analysis point of view. Eiflh : The use of formerly designed circuits was greatly expected in order to minimize the conception work and non recurrent costs. Up lo 64 Arinc danels The AIRBUS A320 program introduced the "fly by wire" concept in commercial transport airplanes. Within this plane, for flight management and guidance systems integration, a communication problem had risen, because of the great number of ARlNC 429 lines which a computer had to listen to in order to perform its function. This constraint had led to the need for and the design of very compact and powerful ARlNC 429 reception units, all of them based on a common architecture using extensively a gate-array-based Asic called "SR8A". This gate array was describted in a previous paper presented at the specific Circuits Conception Conference in GRENOBLE in 1988. This circuit has the following properties : - 8 channels cascadable up to 64. - Automatic speed recognition and control. - Programmable message selection and storage address computation by means of an external E*PROM array common to all the SR8As connected on the same bus. - Structured data array management in an external ram common to all the SR8A connected on the same bus. - 8-bit micro interface with 32-bit word integrity management through a 32-bit embedded cache register. Since the A330-A340 program was launched, we have been faced with a new problem, because a new generation ARlNC 429 Data Concentrator was needed. First : We had to provide more than 64 channels on a single printed circuit board. S e c o n d : For computation load reasons new generation 32-bit microprocessors were used and the 8-bit interface appeared to be inappropriate in this respect. UDt 8 SR8A o Control Address FIG. 1 A SRIA based typical architecture 2. "CAMELIA" : A CIRCUIT FOR EXTENDED ADDRESS MANAGEMENT The two main problems we had to overcome in order to increase the number of channels in an SR8A based architecture, is the arbitration protocol which is limited to eight circuits. This problem can be solved by using two groups of up to eight SR8A connected to an addon state machine performing the inter-group arbitration. This solution allows up to 128 channels. The second one is the 15-bit indexing address capability available in the standard SR8A architecture. M0316-0/90/0000/0066/$01 (9 1990 IEEE .OO 68 2 of 5 This capability was more than sufficient in our A320 application, but was greatly limiting the upgrade to more powerfull systems. The solution to both these problems was founded in the Camelia Concept, the letters C.A.M.E.L.I.A. standing for "Adaptive Indexation Link for Extended Memory Allocation Circuit". This circuit allows : up to 128 ARlNC 429 channel concentration up to 18 address bits for indexing management 2 indexing algorithm are available. The A. algorithm specially designed to optimize the E2PROM size when the number of channels is high and the number of useful extended labels per channel is small compared to 1024 (the maximum number of extended labels possible on one channel). The C algorithm is specially designed to minimize the E2PROM size when the number of channels is less than 64 and the number of useful extended labels is close to the maximum. GROUP A up t 8 SR8A o up lo 64 Arinc chanels Address Data "A Algorlthm" (SDI Not decoded) SWH I C h m d N r I XV 1 I 0 0 0 I I UBEL INDEX1 IO S W H I C h a n l N r I XV 0 0 I UBEL INDEX3 I Chu*INr I NOEX2 I WDEX I 1I "A Algorllhm" (SDI decoded) GROUP E up IO 8 SRBA up to 64 Arinc chanels 3. "ACACIA" A CIRCUIT FOR EXTENDED FEATURES As we can see in fig 2 the "CAMELIA is located from a data transfer point of view between the "SR8A" groups and the common memory. It strobes both the A and B group buses, and performs arbitration between the two groups. From the close observation of the bus protocol signals, the CAMELIA internally mirrors the machine state of the active SR8A on which it synchronizes all its specific actions. - It manages its specific address bits during SR8As indexation transfer phases. - During first SR8A indexation, it performs a private indexation in order to be able to extend to addressing range. - It returns modified index to the SR8A (see fig.3/4 A algorithm). - In fig. 2 the CAMELIA writes directly ARlNC Data in a dedicated ram which is, through the Master SR8A and CAMELIA, mapped into the microprocessors's addressable range. Unfortunately the interface is 8 bits wide in that case, which is a little bit time consuming in very heavy applications and in some cases, can compromise good data management by common bus overloading. - If a more efficient interface is needed associated with new features a post processor can be added on the common bus which leads to an architecture as shown in fig 5. In that architecture, the main micro interface is 16 or 32 bits depending on microprocessor and backplane choice. An 8 bit interface toward SR8A may still remain in order to achieve programming and self test features but is not supposed to cause overhead acces on the common bus in normal operation configuration. In this configuration the common bus is dedicated to indexation algorithm and transfer and has a granted throughput of 500 000 ARlNC words per second which is sufficient even for 128 high speed channels. (The max throughput of an ARlNC channel is 2778 words per second which corresponds to one word every 360 microseconds). 69 3 Of 5 The post processor observes very closely the indexation and transfer cycles, interprets indexation constants as an instruction and the data as an operand. It manages to store the operand with respect to the instruction and to a predefined Data array structure. On the other hand, it receives requests from the microprocessor interface and answers as quickly as possible with respect to data integrity. The data transfer bus between post processor and data array structure is 32 bits wide and is capable of a 5 million 32 bits access per second max throughput which allows a quite sophisticated data array structure management. In appliance of that architectural concept, a dedicated post processor named ACACIA has beed designed. The letters ACACIA are approximately standing for ARlNC Information Chronology and Acquisition Control post processor. Its perfwmance can be roughly described though the explanation of fig. 6. which shows the data array format. 6 object types are manipulated. 5 are variable type : single word data fifo-like files for multi word data control word associated with single word - control word associated with fifo words - fifo descriptors 1 is of constant type : constraints. A single word data is a 32-bit ARlNC word as receivedthough the SR8A CAMELIA path. - A fifo-like file is a 15 word max sequence of ARlNC words sharing the same label and channel processor and identified during indexation phases as a multi word data. - Control word associated with single word is a 16-bit variable formated as the concatenation of a 4 bits Hamming code key "HE" associated to the record and a 12 bits datation. - Control word associated to fifo-words is a 32 bits word formated as the concatenation of : . a 4-bit "HE" Hamming code key as above. . a 12-bit datation. . a 4-bit "HL" Hamming code associated with the label. . a 12-bit dating associated with the preceding word inside the fifo. Both control words are used during the restitution on microprocessor request in order to perform : - Controls on internal coherence based on "HE" Hamming code. - Controls on data refreshment based on : . recorded dating versus actual time in respect to refreshment constraints for single word records. . Recorded dating versus preceaing wuiu U ~ L I I I Y respect to refreshment constraints for multiple word files. . Global dating versus actual time in respect to refreshment constraints for empty fifos. Fifo descriptors are 32-bit variables associated with one of each of 256 manageable fifo-like files and are formated as the concatenation of : GROUP A GROUP B - U FIG. 5 post processor architecture . 4-bit writing pointer . 4-bit reading pointer . 4-bit control field for test purposes . 4-bit fifo threshold N which is the number of words stacked inside the fifo for which an interrupt is sent to the processor. . 4 bits HL Hamming code which is a Hamming code key associated with the ARlNC label (adequation of label and HL is checked before writing the word in data array structure). . a global date previously mentioned which is the dating of the last word entered inside the fifo. Constraints are constant type 16-bit words which are formated as the concatenation of : - a 4-bit HL Hamming code key and a 12-bit refreshment constraint which is the maximum allowed time between two consecutive words in the same ram location or in the same fifo. This contraint is checked during the restitution of the corresponding word on a microprocessor request. A special background task is performed with a frequency equal to the half time coding dynamic in order to prevent time coding ambiguity due to time folding. When such an ambiguity is about to be possible a special alteration of the corresponding record's HE Hamming code is performed which allows a later warning to the microprocessor. 70 4 Of 5 / HE HE I I I Datalion I I Datatlon I HL HL Precedm! Word Date [Precedent Word Dale 1 I I Control I HE I Datation 1 Hi ECR ILECllCTRLI N Conlrol Space I 1 Slandard Arinc Word Control Space 12K Word I HL I ]Precedent Word Dale Global Dale RAM ) I same \N_, I Data Space HE I Datamn I HL I L. Refresh - - - - - I I I Amc Word as Received Slandard Arinc Word Space 12K Word Aiinc Word a5 Rece(ved A m c Word as Received Fit0 Space Up lo 256 15 Word Fit0 32 Bit RAM 16 Bit ROM - FIG. 6 Data array format FIG.7 RamlRom superposition 4. FAILURE MODE ANALYSIS and control bits, associated with the fact that datdcontrol word addresses are obtained one from the other by all address bit inversion. 5. FIFO MANAGEMENT The first control performed on the ACACIA'S CAMELIA side is to check the coherence of instructions and data. This check is based on : - Data panty - Address label parity - Address format coherence. - During the storing phase, the ACACIA checks the acceptability of ram modification versus HL constraint and calculates the HE key associated with the record it performs. - During the restitution phase, it controls the internal coherence of records and its status versus HE, word parity and refreshment constraint. In case of any problem, a non-ambiguous error word is sent to the microprocessor. - All these controls associated with the data array format make the probability of a non detected failure in the data structure integrity very unlikely to happen because such an event requires two or more distinct devices simultaneously and compatible failure. Undetected common cause failure by addresddata bit sticking or short circuit are made very unprobable because of scattering in the 32-bit data field of record The most sophisticated function performed by the ACACIA circuit is the management of up to 256 fifo-like data files inside the ram, each of them associated with a mirror control space, containing the fifo status descriptor. Each fifo has a unique address from a storing and reading point of view. This address is named as the fifo base, in respect to which the 4-bit writing and reading pointers must be considered as offsets. When the size of a fifo's content reach a preprogramed threshold, an interrupt is sent to the microprocessor, and the fifo number is pushed inside an interrupt fifo in order to permit interrupt stacking up to 16 levels. This fifo is mapped inside a register file internal to the ACACIA. Fifo's exception status as overflow causes also an interrupt associated with a special format interrupt vector. The same remark can be made for error detection during instruction acquisition and data storage. 71 5 Of 5 6. CONCLUSION Such an architecture has been successfully implemented on a single printed board gathering : - 9 SR8A allowing 72 channels concentration - 1 CAMELIA, - 1 ACACIA; 18 ceramic macromodules for ARlNC demodulation and protections. EPLD's and transceiver for Address decoding and micro interface management. 4 x 32 K 8-bit Ram 4 x 32 k 8-bit E2PROM Special system oriented test features allow a CPU initiated test to be performed during the power-on check sequence with very efficient controllability observability path. Especially incoherent data structure or inacceptable instructions can be initiated to check the ACACIA'S ability to react properly in such exceptional cases. SR8A is a 4000-gate 2p MHS Gate array including a 72 X 8-bit compiled ram. CAMELIA is a 2700-gate 2p MHS Gate Array. ACACIA is a 9000-gate equivalent 1,5p V L S I Technology Inc Sea of gate. The last two ones were designed in a Mentor Graphic environment using a hardware modelizer on which a SR8A first, then a CAMELIA were plugged in order to allow complex interaction simulation and system level validation. Such a methodology was possible because of the pre-existence of the SR8A during the CAMELIA's design and of the CAMELIA during the ACACIA'S design. These conditions seem to be very infrequent as well as incompatible with planning constraints in the case of an "ex nihilo" system design. But in our case, we took benefit from an existing family of circuits associated with an important ARlNC System design background which allows us to focus on architecture problems and design proof demonstration and finally led to a first good silicon multi asic system design. 12