International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013Architecture and Component Selection for SDR Applications Shameem Shaik #1, Suresh Angadi*2 # B.Tech Final Year Student, Department of Electronics & Communications, K L University Vaddeswaram, Andhra Pradesh, India-522502 * Assistant Professor,Department of Electronics & Communications, K L University Vaddeswaram, Andhra Pradesh, India-522502 II. GENERIC REQUIREMENTS ABSTRACT: In wireless communications, particularly the military space, software-defined radio (SDR) is the goal. The basic concept of SDR is to position the digital-to-analog separation as close as possible to the antenna. This is accomplished by implementing many functions traditionally performed by analog circuits using reconfigurable digital circuits. Successfully implemented, this can deliver an obsolescence-proof radio product which can support many existing and future air-interfaces and modulation formats. These objectives can be difficult to achieve, particularly for smaller, battery-powered applications. ■ Low power consumption, particularly while in standby mode ■ Reconfigurable baseband, with sufficient processing resources to implement many waveform types, such as frequency shift keying (FSK), quadrature amplitude modulation (QAM), Code Division Multiple Access (CDMA), and orthogonal frequency division multiplexing (OFDM). ■ Multiple antennas ■ Small form factor ■ Video display of information Keywords: Software defined radio, Base band, DSP processors, Sub Sampling I. INTRODUCTION Software-Defined Radio (SDR) is defined as "radios that provide software control of a variety of modulation techniques, wide-band or narrow-band operation, communications security functions (such as hopping), and waveform requirements of current & evolving standards over a broad frequency range.” In a nutshell, Software-Defined Radio (SDR) refers to the technology wherein software modules running on a generic hardware platform consisting of DSPs and general purpose microprocessors are used to implement radio functions such as generation of transmitted signal (modulation) at transmitter and tuning/detection of received radio signal (demodulation) at receiver[1]. ■ Common external interfaces to other equipment, such as Ethernet and USB ■ Wide operating temperature range without active cooling ■ Wide operating frequency band ■ Multiple frequency band support ■ Moderate cost ■ High manufacturing yield A critical design parameter, which has a major impact in meeting any set of requirements, is the location of the digitalanalog separation in the radio chain, both for receive and transmit. The SDR methodology dictates that this conversion should take place as close to the antenna as possible. ISSN: 2231-5381 http://www.ijettjournal.org Page 691 International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013 Recently, intermediate frequency (IF)-subsampling analogto-digital converters (ADCs) operating at over 100 MSPS at 12+ bits with analog input bandwidths up to 1 GHz have become available. The current offerings by leading vendors require as little as 200 mW of power consumption per channel. This makes IF frequencies above 500 MHz practical. It still will not allow direct sampling of a 2-GHz signal, but it will allow for a single conversion radio to sample multiple signals over a wide bandwidth. Increasing the sampling rate also increases the effective signal-to-noise ratio (SNR) as the signal of interest is decimated to baseband processing rates, improving the sensitivity and dynamic range of the radio receiver. Interfacing at these levels of IF frequencies is a bit more challenging on the transmit side. Most baseband circuits have difficulty producing transmit samples at rates much higher than 200 MHz, which limits the transmit IF to about 40 percent of the rate, or about 80 MHz. But some digital-toanalog converter (DAC) vendors have addressed this issue by incorporating interpolation into their parts, and adding circuitry to allow the DAC to selectively output in higher Nyquist zones (thereby eliminating the 40 percent requirement). Another option is to integrate interpolation, digital mixer, and the DAC. This also can permit high transmit IF frequencies, on the order of 400 MHz. However, these approaches can be expensive, both in terms of cost and power consumption. If lower transmit IFs are acceptable, then a much less costly and lower power solution can be implemented. Architecture and Component Selection for SDR Applications. For baseband processing, there is a plethora of possible solutions and architectures. For SDR applications, one of the key requirements is configurability and flexibility. This eliminates the lowest cost and power consumption solution, which is purpose-built baseband ASICs such as those used in commercial cell phones. The most flexible digital signal processing (DSP) solution is to use both a DSP processor and a FPGA. This approach has the following advantages: ■ The DSP processor provides the ideal platform for implementation of very complex algorithms ■ The FPGA provides very high processing rates and bit resolution required for certain functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), CDMA RAKE receiver, Turbo decoders, and numerous other functions Figure 1: Block diagram of Generic digital Transceiver ■ FPGAs can act as an effective co-processor for DSP processors, provided suitable high-bandwidth connections are available; this approach allows algorithms to be split across DSP devices and FPGAs in an optimal fashion ■ Both DSP and FPGA vendors offer extensive vendor or third-party intellectual property (IP) for many complex but standardized functions ■ Mature and well known development tool environments are available ■ Can later migrate latest devices within DSP/FPGA product families, which will continue to add capability while preserving initial investment of in-house development, IP, tools, and design methodology ■ DSP processors can incorporate protocol and packet processing functions, either with dual processors, or by using single convergent processor architecture ■ DSP processors can incorporate the BT656 video interface to the user display[3]. III. ARCHITECTURE This section gives a brief overview of a basic conventional digital radio system and then explains component selection for SDR applications. It then explains the software architecture of SDR. Generally L-band antenna, capturing GNSS signals, noise and possible interference are used. The various functional blocks in a generic digital radio transceiver (transmitter/receiver) system is depicted in figure 1. The digital radio system consists of three main functional blocks: RF section, IF section and baseband section. ISSN: 2231-5381 http://www.ijettjournal.org Page 692 International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013 A. RF section (RF front –end): The RF section consists of essentially analog hardware modules. The RF section (also called as RF front-end) is responsible for transmitting/receiving the radio frequency (RF) signal from the antenna via a coupler and converting the RF signal to an intermediate frequency (IF) signal. The frontend typically down-converts, filters, amplifies and digitizes the incoming signals. B. IF Section: The ADC/DAC blocks perform analog-to-digital conversion (on receive path) and digital-to analog conversion (on transmit path), respectively. ADC/DAC blocks interface between the analog and digital sections of the radio system. DDC/DUC blocks perform digital-down conversion (on receive path) and digital-up-conversion (on transmit path), respectively. DUC/DDC blocks essentially perform modem operations, i.e., modulation of the signal on transmit path and demodulation (also called digital tuning) of the signal on receive path. C. Base band Section: The baseband section performs baseband operations (connection setup, equalization, frequency hopping, timing recovery, correlation) and also implements the link layer protocol (layer 2 protocol in OSI protocol model). Baseband signal processing gathers all the algorithms to find and follow a visible GNSS signal, by means of synchronization to the known PRN code, and removing errors as best as possible. This process is built around the principle of signal correlation the incoming signal is repeatedly correlated with a replica of the expected PRN code, which is known a priori. The correlation principle is first used to search for the satellites in view. After a receiver starts operating, it first needs to know which satellites are in view and can be tracked for extracting measurements. This process is known as acquisition, and it is based on several correlations between the incoming signal and multiple replicas of the possible "expected" signals, generated for different code delays and Doppler frequencies. Figure 2: Example of an acquisition process, showing the Doppler / code delay search space and correlation peak that indicates presence of a signal with code delay of 650 chips and Doppler frequency of 1750 Hz. The DDC/DUC and baseband processing operations require large computing power and these modules are generally implemented using ASICs or stock DSPs. Implementation of the digital sections using ASICs results in fixed-function digital radio systems. If DSPs are used for baseband processing, a programmable digital radio (PDR) system can be realized. In other words, in a PDR system baseband operations and link layer protocols are implemented in software. The DDC/DUC functionality in a PDR system is implemented using ASICs[3]. A software-defined radio (SDR) system is one in which the baseband processing as well as DDC/DUC modules are programmable. Availability of smart antennas, wideband RF front-end, wideband ADC/DAC technologies and ever increasing processing capacity (MIPS) of DSPs and generalpurpose microprocessors have fostered the development of multi-band, multistandard, multi-mode radio systems using SDR technology. In an SDR system, the link-layer protocols and modulation/demodulation operations are implemented in software. If the programmability is further extended to the RF section (i.e., performing analog-to-digital conversion and vice-versa right at the antenna) an ideal software radio systems that support programmable RF bands can be implemented. However, the current state-of-the-art ADC/DAC devices cannot support the digital bandwidth, dynamic range and sampling rate required to implement this in a commercially viable manner [4]. ISSN: 2231-5381 http://www.ijettjournal.org Page 693 International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013 IV. Component Selection for SDR Applications D. FPGA Selection A. ADC Selection: The receive technique of IF sub-sampling is commonly used in SDR designs. This can allow for very high receive IF. Theoretically, the receiver IF is only limited by the analog bandwidth of the ADC. Practically, a very high receive IF can degrade ADC performance, and also impose tight requirements on the jitter of the ADC clock. For these reasons, it is important to compare both the analog bandwidth of the ADC as well as the maximum characterized receive signal in the manufacturer data sheets. ADC performance at higher IF rates than characterized in the data sheet should be verified with the device manufacturer. In Table 1, only ADCs with > 100 million samples per second (MSPS) capability and < 500 mW per channel were considered. A 12-bit resolution is usually sufficient to meet the requirements of most modern radio requirements, and 12- to 14-bit ADCs were considered. Dual ADCs are attractive, as most SDR receivers will require diversity. B. DAC Selection: The power and cost penalties make a very high transmit IF unattractive, unless there is a compelling reason for this approach. Since a 400-MHz transmit IF is still far too low for most frequency bands, an analog up conversion stage will be required in nearly all cases. For typical SDR applications where the signal bandwidth is less than 25 MHz, a sub 100MHz transmit IF frequency coupled with a single mixer stage to RF is more practical. Table 2 summarizes the comparison results among several competitive DACs. A 14-bit resolution is usually sufficient to meet the performance requirements of modern radio modulations C. DSP Selection: The FPGA represents another important architectural component choice. FPGAs have evolved beyond just programmable hardware, as the FPGA manufacturers offer extensive IP cores, microcontroller soft cores, reference designs, system-on-chip design methodology, and comprehensive design environments. The digital up and down conversion chains, pulse shape filtering, CDMA bit level processing, OFDM FFT processing, Transmit Crest Factor Reduction, and Turbo, Viterbi, and Reed Solomon decoding are all very good candidates for FPGA implementation. Both manufacturers offer IP cores and reference designs for most if not all of these functions. FPGAs also come in various densities, which are often pin compatible. This allows larger devices to be used, and allows for more processing margin for future radio protocols[5. V. Conclusion Current market drivers such as future-proof equipment, seamless integration of new services, multi-mode equipment and over-the-air feature insertion in commercial wireless networking industry have resulted in widespread interest in SDR technology. The technology can be used to implement wireless network infrastructure equipment as well as wireless handsets, PDAs, wireless modems and other end-user devices. However, factors like higher power consumption, increased complexity of software and possibly higher initial cost of equipment vis-à-vis the benefits offered by the technology should be carefully considered before using SDR technology to build a radio system. Summarizing, SDR is a promising technology that facilitates development of multi-band, multiservice, multi-standard, multi-feature consumer handsets and future-proof network infrastructure equipment. REFERENCES The choice of DSP processor is the one to get right the first time, as it is difficult to change later. The following list of requirements was used to narrow the field to two vendor families. ■ Established product family, well received in marketplace, expected to be well supported and increase in capability in future ■ Good options for operating system: vendor supplied, Linux, third party ■ Able to support packet processing tasks (media access control (MAC) layer) ■ Able to support radio upper layer protocol layers ■ Mature development environment ■ 500-MHz core performance ■ Low-power architecture (less than 1 W) ■ Support for Ethernet and/or high-speed USB ■ External DDR (or SDRAM) memory interface ■ High-bandwidth interfaces suitable to interface to FPGA ■ Able to drive video display interface[4] [1] Software Defined Radio: Enabling Technologies By Walter H.W. Tuttlebee[1] [2] Implementing Software Defined Radio By Grayver.[2] Eugene [3] Architectures, Systems and Functions' by Markus Dillinger, Kambiz Madani, and Nancy Alonistioti, published by John Wiley & Sons, 2003.[3] [4] Putting FPGAs to Work in Software Radio Systems, Fifth Edition Rodger Hosking (Pentek, Inc)[4]. [5] Software Defined Radio Handbook (EighthEdition) ISSN: 2231-5381 http://www.ijettjournal.org Page 694
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