ADC-DAC-PPT

Lecture 9Today: Basics of A/D and D/A. Spartan-3 analog I/O and DDS. Digilent family boards. Printed copy of today’s lecture slides. VHDL materials on handouts web page Pedroni, data sheets, etc. Please keep the lab clean and organized. Last one out should close the lab door!!!! Handouts: Read: References: Nothing is more difficult, and therefore more precious, than to be able to decide. — Napoleon I. EECS 452 – Fall 2009 Lecture 9 – Page 1/59 Mon 9/28/2009 This week’s reminders ◮ ◮ ◮ HW 3b due this Wednesday. HWs 2 and 3 due this Friday. Project team formation and topic selection next Wed night. EECS 452 – Fall 2009 Lecture 9 – Page 2/59 Mon 9/28/2009 ADC and DAC ADC (analog to digital converter) and DAC (digital to analog converter) are two critical elements in most digital systems. ◮ ◮ ◮ We will take a look at the basic idea behind these. We will introduce the A/D and D/A on S3-SB and other related IO. You will get to practice these in Lab 4. Discretize it in time: sampling or time quantization. Discretize it in value/amplitude: quantization or amplitude quantization. Reverse quantization: assign real value to each quantile Reverse sampling: interpolation (reconstruction) What do you do when you have an analog waveform? ◮ ◮ What do you do when you have a sequence of discrete numbers? ◮ ◮ EECS 452 – Fall 2009 Lecture 9 – Page 3/59 Mon 9/28/2009 Visualize sampling & reconstruction Analog waveform 1 amplitude 0.5 0 −0.5 −1 0 1 amplitude 0.5 0 −0.5 −1 0 1 amplitude 0.5 0 −0.5 −1 0 0.2 0.4 0.6 0.8 x 10 1 −3 Analog waveform. Time quantized waveform 0.2 0.4 0.6 0.8 1 −3 x 10 Reconstructed time quantized waveform Discretize in time: sampling using ADC. 0.2 0.4 0.6 time in seconds 0.8 x 10 1 −3 Reconstruct: order hold. zero- EECS 452 – Fall 2009 Lecture 9 – Page 4/59 Mon 9/28/2009 Comments on sampling ◮ Given a real valued lowpass spectrum with bandwidth BW (zero to null), the sampling frequency 2BW is often called the Nyquist sampling rate/frequency. ◮ ◮ There is good reason behind this. You may recall from 216 and/or 451. We will take another more realistic look at this in another two lectures. ◮ In practice one often should sample at a rate of at least two or three times the Nyquist sampling rate. It is also common practice to take the analog signal through an anti-alias filter before sampling. ◮ ◮ ◮ We will see more details on this later, but this is basically a low pass filter to get rid of high frequency components in the analog signal. The AIC23 used on the C5510 DSK has built in anti-alias filters. The cutoff frequencies change with the selected sampling rate. Lecture 9 – Page 5/59 Mon 9/28/2009 EECS 452 – Fall 2009 27.5 Hz.5 Hz (A0) to 4816 Hz (C8). female fundamental about 200 Hz. soprano high C is 1. Telephone nominally passes range 300 Hz to 3200 Hz.Interesting audio frequencies Many waveforms can have energy beyond a band of interest.4 Hz.000 Hz. overtones to about 5 kHz.046. bass low E is 82. Piano: Normal young adult hearing range is 20 Hz to 20. male fundamental about 120 Hz. EECS 452 – Fall 2009 Lecture 9 – Page 6/59 Mon 9/28/2009 . Voice: fundamental around 150 Hz. Common sampling rates Common sampling rates: standard telephone system wideband telecommunications home music CDs professional audio DVD-Audio instrumentation. RF. video 8 kHz 16 kHz 44.1 kHz 48 kHz 192 kHz extremely fast EECS 452 – Fall 2009 Lecture 9 – Page 7/59 Mon 9/28/2009 . EECS 452 – Fall 2009 Lecture 9 – Page 8/59 Mon 9/28/2009 . Delta-sigma (DSP systems in their own right). Successive approximation. Pencil and paper. R-2R resistive ladders. Flash.Most common A/D techniques There are several additional ways in which the conversion of an analog waveform into a series of numbers can be implemented. charge redistribution. Dual slope integration. Successive approximation converters can also be pipelined to develop a few bits at a time as values pass through the pipeline. Quantization: uses a local voltage reference bits of a D/A converter. High speed. Figure from Atmel AD023 data sheet.Successive approximation A/D Sampling: uses a track and hold to capture a voltage on a capacitor. This provides high speed at the cost of a small of delay. Common accuracies range from 8 to 16 bits. EECS 452 – Fall 2009 Lecture 9 – Page 9/59 Mon 9/28/2009 . they are successively switched so as to match the D/A output to the captured voltage. high MHz is possible. Flash A/D (1/2) Multiple comparators: determine all bits at the same time. VERY fast. What is the output for reference 4V and input 2. but the comparators are controlled by clock tics.5? How many possible output values? EECS 452 – Fall 2009 Lecture 9 – Page 10/59 Mon 9/28/2009 . Note that there is no explicit sampling. Flash A/D (2/2) CLK CLK ° ° VRT Analog Input Preamp Comparator 256 CLOCK BUFFER DEMUX CLOCK BUFFER 255 DRB (DATA READY) D8 (OVR) D7 (MSB) D6 D8B D7B DRB (DATA READY) D8B (OVR) D7B (MSB) 152 D6B D5B D4B 256 TO 8 Bit Decoder With Metastable Error Correction D5B ECL Output Buffers And Latches 151 D3B D2B D4B D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) 128 1:2 DEMULTIPLEXER D5 D1B D0B VRM 127 D4 D8A D7A D6A D5A D4A D3A 64 D3 63 D2 D5A D4A D3A D2A D1A D0A (LSB) 2 D1 D2A D1A 1 D0 (LSB) D0A VRB Figure from Fairchild Semiconductor SPT7750 data sheet. EECS 452 – Fall 2009 Lecture 9 – Page 11/59 BANK A D6A BANK B D6B Mon 9/28/2009 . Delta-sigma A/D ¢. §    Σ  ¡¢£¤¥¦§¨ ¤¨¢£. Exploits the cheap availability and small size of today’s digital logic.¥ ¥ £ ¥£ ¥£¤§©¨¢¤ ¨  ¥£¤§©¨¢¤ ¨ Basic idea is to save bandwidth by sending the changes (often encoded using a single bit) in a waveform rather than the full waveform. EECS 452 – Fall 2009 Lecture 9 – Page 12/59 Mon 9/28/2009 . Samples very fast. More details to come in a later lecture. Two’s Complement.Going from voltages to numbers Consider a B -bit A/D converter. Two common mappings from voltages to numbers are: Offset Binary. To convert between the two formats. Most positive value is 2B − 1. invert the most significant bit. EECS 452 – Fall 2009 Lecture 9 – Page 13/59 Mon 9/28/2009 . Most negative value is −2B −1 . Most positive value is 2B −1 − 1. Most negative value is 0. Usually place zero volts mid input step.Two’s complement scaling Given a B -bit A/D output value: most positive value is 2B −1 − 1. Assume a maximum input voltage excursion of ±Vp Assign voltage −Vp to −2B −1 . EECS 452 – Fall 2009 Lecture 9 – Page 14/59 Mon 9/28/2009 . Note that these limits are slightly asymmetric. This will be seen to give zero DC offset with a zero DC input. most negative value is −2B −1 . Often write ∆V simply as ∆ and refer to it as a quanta. That is. Voltage step size per count change is ∆V = Vp /2B −1 for uniform quantization. the voltage change required for a increment of one in the A/D converter output value. 5 0.Uniform quantization Converts analog voltages into B-bit numbers. EECS 452 – Fall 2009 Lecture 9 – Page 15/59 Mon 9/28/2009 4−bit linear quantizer input to output transfer function 8 6 Quanizer integer output 4 2 0 −2 −4 −6 −8 −1 −0. One quanta change ↔ one ∆ voltage change. Plot’s x-axis is normalized.75 Quantizer analog input level 1 . Change in number by 1 is one quanta.25 0 0.75 −0. ∆ = Vp /2B −1 Usually place A/D bits into computer word most significant bits.25 0.5 −0. Note the placement of the zero input relative to the output count. 711. Why? What if you have a weak signal? ◮ Idea: progressive taxation ◮ ◮ EECS 452 – Fall 2009 Lecture 9 – Page 16/59 Mon 9/28/2009 .Non-uniform quantization: mu-law companding COMpression and exPANDing of digitized waveforms (companding). use smaller steps for small input values. ◮ Originally developed for use in digital parts of the telephone system. Instead of using equal step sizes. ◮ International Telecommunication Union ITU-T Recommendation G. µ -law transfer function How to implement? ◮ ◮ Idea one: come up with unequal step sizes for the entire range. This has an equivalent effect of assigning small steps when input is small. µ = 255. Lecture 9 – Page 17/59 Mon 9/28/2009 EECS 452 – Fall 2009 . idea two: let’s skew the signal instead. Now apply a uniform quantizer. y = Qµ sgn(x) ln(1 + µ |x |/V ) ln(1 + µ) . characteristic and 4-bit mantissa (8-bit code word). 3-bit. ◮ ◮ ◮ Implemented as logarithmic fixed-point number sign. V normalizes the input signal. ◮ ◮ ◮ “stretch” the small values and “compress” the large values. Performance roughly equivalent to 14-bit uniform (linear) encoding. and large steps when input is large. A/D converter worries The real world seems to always get in the way. Offset Error Gain Error Differential Nonlinearity (DNL) Error Integral Nonlinearity (INL) Error Absolute Accuracy (Total) Error Aperture Error A good reference is TI’s Understanding Data Converters. EECS 452 – Fall 2009 Lecture 9 – Page 18/59 Mon 9/28/2009 . July 1995. SLAA013. EECS 452 – Fall 2009 Lecture 9 – Page 19/59 Mon 9/28/2009 . Common A/D word sizes are 8. 14. ◮ ◮ ◮ ◮ ◮ Digital values are most often represented using binary words. A word having B bits can represent 2B numeric values. The more A/D bits the greater the quality of the sampled data. details to come later. analog values (uncountably infinite) are converted into a finite number of values.Errors introduced in A/D Now let’s take a look at the amount of error we introduce in the process of A/D. 16 and 24 bits. ◮ We know if we don’t sample fast enough we get into trouble. 12. Information is lost. 10. In quantization and encoding. The statistics of the quantization errors are wide sense stationary. A wide sense stationary random process is one whose first and second moments are time invariant and whose autocorrelation function is invariant to time shift. The quantization errors are independent of the waveform being quantized. This leads to the concept of a white spectrum. Quantization error values are independent of each other.Quantizer model and assumptions ◮ The quantization errors are uniformly distributed over the range from −∆/2 to ∆/2. Mon 9/28/2009 ◮ ñxåz nì~åíáòÉê nE=F ñxåz=Z nEñxåzF ◮ ◮ ñxåz ñxåz=Z ñxåz=H Éxåz Éxåz EECS 452 – Fall 2009 Lecture 9 – Page 20/59 . 5 Quanta 0 −0.5 −1 0 0.5 0.6 Sinewave period 0.5 0.9 1 EECS 452 – Fall 2009 Lecture 9 – Page 21/59 Mon 9/28/2009 .4 0.2 0.7 0.1 0.8 0.6 Sinewave period 0.3 0.2 0.7 0.1 0.3 0.8 0.9 1 Sinewave quantization error using 4−bit quantizer 1 0.5 Amplitude 0 −0.5 −1 0 0.Uniformly quantized sinewave and error Sinewave quantized using 4−bits 1 0.4 0. They forget that the theory is only an approximation to reality. Systems designed based on them often work as expected. On occasion. But you do have to start somewhere and these provide a relatively simple starting point.Really? Do You Really Expect Me to Believe Those Assumptions? No. Don’t forget this! EECS 452 – Fall 2009 Lecture 9 – Page 22/59 Mon 9/28/2009 . In actual practice these assumptions have proven to give surprisingly good results. when designers run into problems they often think it is because of something they did. 2 Vp ∆2 = 12 12 · 22B −2 Signal-to-noise ratio: SQNR SQNR(dB) = = = EECS 452 – Fall 2009 12 · 22B Px Px = Px = 3 2 2 2B 2 Pe 3Vp Vp 10 log10 SQNR = 10 log10 constant given Px + 6B Lecture 9 – Page 23/59 Mon 9/28/2009 3Px 2B 2 + 10 log10 2 Vp .Quantization noise model Éxåz ñxåz H H ñxåz=Z ñxåz=H Éxåz The noise mean and variance are: µe 2 σe = = 0. For example working with a music selection with soft passages and loud passages. EECS 452 – Fall 2009 Lecture 9 – Page 24/59 Mon 9/28/2009 . This means using an rms level somewhat reduced from the maximum safe sine wave value. Choosing a maximum safe level is often done in a somewhat hand wavy manner. OFDM (orthogonal frequency division multiplexed) communication systems generally have a significant peak-to-rms dynamic range problem.Peak to RMS worries Most signals are much more unstructured than is a sinusoid and one has to worry about the peak-to-rms ratio in order to minimize clipping. Basically one need to set the “normal” level and allocate some “head room” for when the signal is large. . . One of many ways: voltage divider. What’s the input-output mapping? Is there anything wrong with this scheme? EECS 452 – Fall 2009 Lecture 9 – Page 25/59 Mon 9/28/2009 .Now onto D/A . Reversing the quantization is easy. 3 0.Reversing the sampling process . Using a zero-order hold D/A converter. The dashed line shows the effects of the zero-hold on the spectrum magnitude. .2 0. . It possesses images of the baseband spectrum.5 Magnitude 0. EECS 452 – Fall 2009 Lecture 9 – Page 26/59 Mon 9/28/2009 . 1000 Hz.4 0. and 3500 Hz. Example D/A output: ◮ ◮ ◮ Three tones: 200 Hz.1 0 −3 −2 −1 0 1 Frequency (Hz) 2 3 x 10 4 ◮ ◮ Theoretically we can perfectly reconstruct if we sample fast enough. In practice sampling itself is imperfect. Spectrum of the reconstructed waveform 0. fs = 8000 Hz. Filter may be solely analog or switched capacitor analog cascade. Low pass cutoff will nominally be somewhat below fs /2. Might correct for the zero-order hold amplitude shading. May have concerns about phase distortion. Low pass filter needed to attenuate/remove the images.Anti-image filter Zero-order hold has weighted (shaded) the spectrum. EECS 452 – Fall 2009 Lecture 9 – Page 27/59 Mon 9/28/2009 . EECS 452 – Fall 2009 Lecture 9 – Page 28/59 Mon 9/28/2009 . A/D: sampling and quantization.Quick summary of A/D and D/A ◮ ◮ ◮ ◮ Basics of converting an analog signal to digital form. D/A: the reverse of the above processes. Next: the ADC and DAC on Spartan-3 and their use in Lab 4. Four digit seven segment display. S3. paged and so on. extra and/or different off board connectors. Eight slide switches. DRR2. Size of the FPGA used. A special board (MIB) is needed for the S3SB in order to add these. Four push buttons.Digilent Spartan-3 family boards Digilent sells a variety of design platforms based on Spartan-3 variants. These differ in terms of ◮ ◮ ◮ ◮ ◮ ◮ Spartan-3 sub-family. Connectors used to connect off board devices to the FPGA. The type of external memory. The over voltage protection included on the FPGA lines. static RAM. Lecture 9 – Page 29/59 Mon 9/28/2009 These boards have in common ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 . At least four 6-pin PMod connectors. S3E. A1. Lecture 9 – Page 30/59 Mon 9/28/2009 ◮ ◮ EECS 452 – Fall 2009 . Signal lines are NOT 5 Volt tolerant!!!! Three 40-pin connectors. Cable supported by IMPACT and ExPort. Connector A2 cabled to C5510 External Peripheral Interface connector. Supplied with Parallel Port JTAG programming cable. Regulated voltage : 3. A2 and B1. Module Interface Board on B1 is used to convert 40-pin connector to 8 6-pin PMod connection positions.3 Volts.Spartan-3 Starter Board used by EECS 452 ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ FPGA : XC3S1000 (106 gates) Package : FT256 (a ball grid package) Speed: -4 (not the fast part) EPROM : XCF04S (larger than on base board) Board powered by 5 Volt supply. Some available PMod boards ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ Dual 12-bit A/D converter. DIN1. ENC. AMP1. EECS 452 – Fall 2009 Lecture 9 – Page 31/59 Mon 9/28/2009 . Rotary encoder. Dual 12-bit D/A converter. SWITCH. Dual BNC. Digital input. CON2. AD1. and many more. Four slide switches. Speaker/headphone amplifier. DA2. Given sufficient lead time we can create our own project specific boards. J3→pmod_b. J5.Digilent D/A. J5→pmod_c and J7→pmod_d. J3. J7 and pins in the other positions. We have modified our MIB boards to have sockets in positions J1. The UCF naming is J1→pmod_a. A/D and MIB P1: CS P2: Data1 J1 Connector ADC 1 Filter P1 J2 Connector P2 P3: Data 2 P4: Clk P5: GND P6: Vcc AD1 Circuit Diagram ADC 2 P3 P4 P5 P6 Filter From Digilent data sheets. EECS 452 – Fall 2009 Lecture 9 – Page 32/59 Mon 9/28/2009 . Pmod. Use socket-socket cables to connect pins. (Actually is connected to memory bus which is used by the XVGA entity. MIB goes here ! The Spartan-3 Starter Boards has provision for lots of connections. Lecture 9 – Page 33/59 Mon 9/28/2009 On the S3SB: ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 . This is the primary reason we chose it. MIB and other connectors ◮ ◮ ◮ ◮ ◮ Pins on MIB connect to pins on PMod modules. Make sure VB on MIB connects to VCC on PMod! Make connections with power OFF! For now connector A1 is “not” being used. We have installed sockets on alternate positions. B1 is left for use by other devices.) A2 is reserved for connecting to DSK peripheral interface bus to the Spartan-3 Starter Board. EECS 452 – Fall 2009 Lecture 9 – Page 34/59 Mon 9/28/2009 . never use any voltage other than 3. Please try very hard to connect V to the V pin on the PMod being plugged in. GND — Names used on individual boards vary with the board.3 volts. ◮ ◮ ◮ ◮ ◮ ◮ IO1 IO2 IO3 IO4 V — — — — — general I/O general I/O general I/O general I/O power ground. Things will often work better that way.PMod pins PMod pin names used on the MIB. D/A PMod goes J7 (PMod D). A/D and D/A PMod boards as follows.EECS 452 “standard” PMod placement Our goal is to always place. J5 (PMod C). A/D PMod goes J3 (PMod B). available. one to all. the switch. ◮ ◮ ◮ ◮ Four slide switch PMod goes J1 (PMod A). It makes life a bit simpler having some predictability. EECS 452 – Fall 2009 Lecture 9 – Page 35/59 Mon 9/28/2009 . S3SB electret microphone interface. EECS 452 – Fall 2009 Lecture 9 – Page 36/59 Mon 9/28/2009 . C5510 master. single supply level shifting. The exercise introduces the dual-channel A/D and D/A PMod modules. S3SB master. D/A out loop. simple A/D in. S3SB/C5510 link. metastability demonstration.Lab exercise 4 ◮ Demonstrates: ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ interfacing the PMod DA2 D/A converter. DDS using the S3SB. S3SB/C5510 link. interfacing the PMod AD1 A/D converter. bottom-up design The only real design effort was implementing the bit serial interfaces for the D/A and A/D devices. Attention was given on these would be used by higher levels. sync. clock.! 16-bit data frames are used. ◮ ◮ ◮ ◮ ◮ Two chips mounted per PMod board. Max clock rates of 30 (D/A) and 20 (A/D) MHz.Combined top-down. These might be considered device drivers written in VHDL. Low level entities were created first. One converter per chip. Tested using test VHDL. Four lines: data 1. EECS 452 – Fall 2009 Lecture 9 – Page 37/59 Mon 9/28/2009 . data 2. to learn how to make it work. Check the D/A data manual to determine ◮ ◮ ◮ how it works. Check the schematic and data sheet to ◮ ◮ ◮ determine the part number.Starting with the D/A A simple test is to run a counter and send the count values to the D/A and observe the waveform. the signal timings. About as basic test you can do. see how the part is designed into the board. Actually. EECS 452 – Fall 2009 Lecture 9 – Page 38/59 Mon 9/28/2009 . the mapping from digital input values to output voltages. find the PMod pin signal assignments. The Digilent PMod-DA2 module Analog Outputs D1 DAC121S101 D/A Converter J2 Connector Sync.5V. Clock DAC121S101 D/A Converter J1 Connector 2 D2 GND VCC The PMod-DA2 uses two National Semiconductor DAC121S101 12-bit digital-to-analog converters with rail-to-rail output. Maximum serial clock rate is 30 MHz. Uses a bit-serial interface. Operates using supply voltages in the range 2. Figure from the PMod Digilent data sheet. EECS 452 – Fall 2009 Lecture 9 – Page 39/59 Mon 9/28/2009 .7V to 5. The DAC121S101 D/A Max serial clock : 30 MHz Data uses offset binary. Analog output updates on 16th shift clock falling edge. 20114906 EECS 452 – Fall 2009 Lecture 9 – Page 40/59 Mon 9/28/2009 . From the National Semiconductor data sheet. After loading the DAC register the state machine waits for the next high to low transition on sync_n ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 Lecture 9 – Page 41/59 Mon 9/28/2009 . Possibly on the 16th falling edge of sclk. The start of a serial transfer is detected by sampling sync_n using the rising edges of sclk. ◮ sync_n can remain high between updates going low when a serial transfer is to start.How to make the D/A work Here are some observations/guesses about the control of the D/A. Data bits are sampled on the falling edges of sclk. There is a counter in the D/A that loads D/A holding register from the input shift register. Use of a state machine in the D/A control logic is assumed. These are based on the timing diagram and written signal descriptions contained in the data sheet. if counter = 15 then whatever end if.Going from now to next if rising_edge(clk) then what shall be <= depends upon what now is. end if. ------------------------------------------------------------------------------------------------------counter <= counter+1. What happens when entering this code segment with counter containing 14? Does whatever happen or not? EECS 452 – Fall 2009 Lecture 9 – Page 42/59 Mon 9/28/2009 . clear_goo) is begin if clear_goo = ’1’ then goo <= ’0’. signal mygoo : std_logic_vector(1 downto 0). pmod : out STD_LOGIC_VECTOR (3 downto 0). pmod(1) <= sr_a(15). pmod(2) <= sr_b(15). EECS 452 – Fall 2009 Lecture 9 – Page 43/59 Mon 9/28/2009 . signal counter : std_logic_vector(3 downto 0). type t_state is (s_idle. pmod(3) <= sclk. begin pmod(0) <= sync_n. clear_goo : std_logic := ’0’. s_run).D/A driver body entity pmod_dac0 is Port ( go : in STD_LOGIC. end process. signal sr_a. d_b : std_logic_vector(11 downto 0). clk : in STD_LOGIC). da_b : in STD_LOGIC_VECTOR (11 downto 0). end pmod_dac0. s_wait. da_a : in STD_LOGIC_VECTOR (11 downto 0). sclk : std_logic := ’1’.note go happened end if. architecture Behavioral of pmod_dac0 is signal sync_n. -. signal state : t_state := s_idle.main process goes here end Behavioral. elsif rising_edge(go) then d_a <= da_a. signal d_a.copy input values goo <= ’1’. d_b <= da_b. -. process(go. sr_b : std_logic_vector(15 downto 0). -. signal goo. sclk <= ’0’. -.hold DA clock high if mygoo = "01" then -.sample go signal case state is when s_idle => sclk <= ’1’. -. when s_run => if sclk = ’0’ then sr_a <= sr_a(14 downto 0) & ’0’.rising edge test sr_a <= "0000" & not d_a(11) & d_a(10 downto 0). EECS 452 – Fall 2009 Lecture 9 – Page 44/59 Mon 9/28/2009 .D/A driver main process process(clk. end if. end if. end if. clear_goo <= ’1’.generate clk/2 shift clock mygoo <= mygoo(0) & goo. end process. sr_b <= sr_b(14 downto 0) & ’0’. end case. end if. counter <= (others => ’0’). state <= s_run. sync_n <= ’0’. da_a. da_b) is begin if rising_edge(clk) then sclk <= not sclk. when s_wait => clear_goo <= ’0’. state <= s_idle. sr_b <= "0000" & not d_b(11) & d_b(10 downto 0). counter <= counter+1. state <= s_wait. -. if counter = 15 then sync_n <= ’1’. ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 Lecture 9 – Page 45/59 Mon 9/28/2009 . If the setup time on the register being used to latch the event is smaller than required. Metastable events cannot be avoided. the register can enter a metastable state.Initiating a conversion ◮ This entity is designed so that the go and the clk signal can exist in different clock domains. Moving a signal between clock domains usually involves a level in one domain whose change signals an event. and a clock in a second domain that samples the event signal. In theory this can take forever. but it can’t decide. A metastable state is one where the latch knows that a decision is needed about whether or not the event occurred. However there are things that one can do to minimize the probability of a metastable state becoming a problem. However. Loop changing state only when SCLK is low. EECS 452 – Fall 2009 Lecture 9 – Page 46/59 Mon 9/28/2009 . 25 MHz SCLK is generated unless explicitly held high. At the low to high transition. Only needs to be one 50 MHz clock period long. When GO is ’1’ then set four-bit counter to 0. ◮ ◮ ◮ ◮ Recall that the values to be updated are updated on the NEXT rising edge of the clk. Send sync_m and SCLK low.Walk through ◮ ◮ 50 MHz clock is assumed. Skip the low part of SCLK. copy 12-bit a and b values into 16-bit shift registers with “normal” flag bits. GO pulses are assumed to be spaced at least 1 µ s apart. 25 MHz is within the the D/A 30 MHz limit. if the counter is 15 then also set sync_m high and go back to idling state. increment the counter. shift data. D/A timing diagram êáëáåÖ=ÉÇÖÉë ëÅäâ ëóåÅ|ã ëÉêá~ä=Ç~í~ NR NQ NP NO NN NM Öç EECS 452 – Fall 2009 Lecture 9 – Page 47/59 Mon 9/28/2009 . led : out STD_LOGIC_VECTOR(7 downto 0). ramp_a : out STD_LOGIC_VECTOR (11 downto 0).Simple test using ramps entity rampgen is Port ( go : out STD_LOGIC. end rampgen. signal counter : std_logic_vector(5 downto 0). EECS 452 – Fall 2009 Lecture 9 – Page 48/59 Mon 9/28/2009 . b_ramp <= b_ramp+3. end Behavioral. clk : in STD_LOGIC). architecture Behavioral of rampgen is signal a_ramp. end process. begin ramp_a <= a_ramp. end if. go <= ’0’. process(clk) is begin if rising_edge(clk) then counter <= counter+1. if counter = 0 then go <= ’1’. end if. b_ramp : std_logic_vector(11 downto 0). ramp_b : out STD_LOGIC_VECTOR (11 downto 0). ramp_b <= b_ramp. a_ramp <= a_ramp+1. rampgen port map(go => go. da_a => ramp_a. clk <= mclk. end DACtest0top. ramp_a => ramp_a. ramper : entity work. clk => clk). ramp_b => ramp_b. dac : entity work. mclk : in STD_LOGIC). EECS 452 – Fall 2009 Lecture 9 – Page 49/59 Mon 9/28/2009 . -. go : std_logic. clk => clk). pmod : std_logic_vector(3 downto 0).reduce the clock when generating scope display ---clk <= dclk(3). da_b => ramp_b. -.normally a big no-no! led <= ramp_b(11 downto 4). ramp_b : std_logic_vector(11 downto 0). pmod => pmod. dclk : std_logic_vector(3 downto 0). ramp_a. end Behavioral.pmod_dac0 port map(go => go.D/A test top entity DACtest0top is Port ( pmod_d : out STD_LOGIC_VECTOR (3 downto 0). end process. clk. led : out STD_LOGIC_VECTOR (7 downto 0). process(mclk) is begin if rising_edge(mclk) then dclk <= dclk+1. architecture Behavioral of DACtest0top is signal signal signal signal begin pmod_d <= pmod. end if. Using the D/A to create a sine wave DDS Now that we have a D/A driver and know how to make a counter let’s make a sine wave direct digital synthesizer! The Xilinx CORE Generator provides modules for a sine/cosine lookup table and for a DDS. We could use these. For now we will go DIY (using the DDS VHDL code we showed in the previous lecture). To create a DDS we need a ROM and we need to program the ROM. Some other day. EECS 452 – Fall 2009 Lecture 9 – Page 50/59 Mon 9/28/2009 . Divided into parity and data sections. Initialized using 256 bit vectors. Word size is independently configurable for each port. RAM blocks are clocked. Can share a block RAM between ROM for a DDS and a delay memory used by a FIR filter. Not very difficult to work with. so one need to think a bit about what happens when. Use instantiation templates found in ISE.Working with block RAM Something like 24 18K bit blocks of dual port memory on the S-3/1000 boards. EECS 452 – Fall 2009 Lecture 9 – Page 51/59 Mon 9/28/2009 . Are initialized upon the FPGA is programmed. Becomes a ROM if one does not write to it. A simple DDS entity (1/2) Uses two processes. end process. end if. FTV0R <= FTV0R_next. FTV1R <= FTV1R_next. begin AC0 <= ACC0(31 downto 24). DAC_load <= DAC_load_next. AC1 <= ACC1(31 downto 24). reset) begin if reset = ’1’ then elsif rising_edge(clk) then counter <= counter_next. ACC1 <= ACC1_next. process(clk. EECS 452 – Fall 2009 Lecture 9 – Page 52/59 Mon 9/28/2009 . ACC0 <= ACC0_next. if FTV1_load = ’1’ then FTV1R_next <= FTV1. if FTV0_load = ’1’ then FTV0R_next <= FTV0. DAC_load_next <= ’0’. counter_next <= "000000". end if. FTV1R_next <= FTV1R. else counter_next <= counter+1. if counter = 49 then ACC0_next <= ACC0+FTV0R. ACC1_next <= ACC1. DAC_load_next <= ’1’. EECS 452 – Fall 2009 Lecture 9 – Page 53/59 Mon 9/28/2009 .A simple DDS entity (2/2) process(FTV0_load. end process. FTV0R_next <= FTV0R. FTV1_load) begin ACC0_next <= ACC0. end Behavioral. end if. end if. ACC1_next <= ACC1+FTV1R. X"5CB35ED760EB62F164E866CF68A66A6D6C236DC96F5E70E2725473B575047641". X"D1EFD4E1D7DADAD8DDDDE0E6E3F5E707EA1EED38F055F374F696F9B8FCDC0000". X"8AFC8C4B8DAC8F1E90A2923793DD9593975A99319B189D0F9F15A129A34DA57E". X"7FF57FD87FA67F617F097E9C7E1D7D897CE37C297B5C7A7C79897884776B7641". X"8895877C8677858484A483D7831D827781E3816480F7809F805A8028800B8001". X"A7BEAA0BAC65AECDB141B3C1B64CB8E4BB86BE32C0E9C3AAC674C946CC21CF05". X"33DF36BA398C3C563F1741CE447A471C49B44C3F4EBF5133539B55F558425A82". Primary thing to realize is that the least significant bit is on the right and the most significant bit is on the left. X"800B8028805A809F80F7816481E38277831D83D784A485848677877C889589BF". 256 values of 16-bits. X"750473B5725470E26F5E6DC96C236A6D68A666CF64E862F160EB5ED75CB35A82". X"776B788479897A7C7B5C7C297CE37D897E1D7E9C7F097F617FA67FD87FF57FFF". X"CC21C946C674C3AAC0E9BE32BB86B8E4B64CB3C1B141AECDAC65AA0BA7BEA57E". Used MATLAB to generate. X"A34DA1299F159D0F9B189931975A959393DD923790A28F1E8DAC8C4B8AFC89BF". X"FCDCF9B8F696F374F055ED38EA1EE707E3F5E0E6DDDDDAD8D7DAD4E1D1EFCF05".Address INIT_00 => INIT_01 => INIT_02 => INIT_03 => INIT_04 => INIT_05 => INIT_06 => INIT_07 => INIT_08 => INIT_09 => INIT_0A => INIT_0B => INIT_0C => INIT_0D => INIT_0E => INIT_0F => 0 to 255 X"2E112B1F2826252822231F1A1C0B18F915E212C80FAB0C8C096A064803240000". X"584255F5539B51334EBF4C3F49B4471C447A41CE3F173C56398C36BA33DF30FB".Sine table initialization -. EECS 452 – Fall 2009 Lecture 9 – Page 54/59 Mon 9/28/2009 . X"03240648096A0C8C0FAB12C815E218F91C0B1F1A2223252828262B1F2E1130FB". The PMod-AD1 uses two National Semiconductor ADCS7476 12-bit analog-to-digital converters supporting rail-to-rail input. Uses a bit-serial interface. EECS 452 – Fall 2009 Lecture 9 – Page 55/59 Mon 9/28/2009 .The Digilent PMod-AD1 module P1: CS P2: Data1 J1 Connector ADC 1 Filter P1 J2 Connector P2 P3: Data 2 P4: Clk P5: GND P6: Vcc AD1 Circuit Diagram ADC 2 P3 P4 P5 P6 Filter That was D/A. Operates using supply voltages in the range 2. Now let’s take a look at the A/D PMod. Figure from the PMod Digilent data sheet. Maximum serial clock rate is 20 MHz.7V to 5.25V. Input switches from track to hold on falling edge of the sync signal. From the National Semiconductor data sheet.The ADCS7476 A/D Max serial clock : 20 MHz Max sample rate: 1 MHz Data uses offset binary. EECS 452 – Fall 2009 Lecture 9 – Page 56/59 Mon 9/28/2009 . Most of today’s signal sources are voltage sources and DC coupled sources.Shifting the voltage: A/D input using a single supply oO oP îá oQ oN î~ J H îç oR îë Analysis of this is included in the lab write-up. EECS 452 – Fall 2009 Lecture 9 – Page 57/59 Mon 9/28/2009 . The problem is that the ADC expects voltages from 0 to Vcc. So we need to shift the signal voltage. A common problem we’ll encounter is that our signals are “zero referenced”: it is centered on zero and swing between positive and negative voltage levels. ad0. end process. s_convert). ad1 <= pmod(2). end pmod_adc0.A/D driver body entity pmod_adc0 is Port ( go : in STD_LOGIC. process(go. architecture Behavioral of pmod_adc0 is signal signal signal signal signal signal goo. signal state : t_state. EECS 452 – Fall 2009 Lecture 9 – Page 58/59 Mon 9/28/2009 . mygoo : std_logic_vector(1 downto 0). cs_n : std_logic := ’1’. clear_goo : std_logic := ’0’. pmod : inout STD_LOGIC_VECTOR (3 downto 0). end if. clk : in STD_LOGIC). ar_a. sclk. ad0 <= pmod(1). begin pmod(0) <= cs_n and (not goo). -. clear_goo) is begin if clear_goo = ’1’ then goo <= ’0’. pmod(3) <= sclk. elsif rising_edge(go) then goo <= ’1’. ad_b : out STD_LOGIC_VECTOR (11 downto 0). counter : std_logic_vector(3 downto 0). ar_b : std_logic_vector(11 downto 0). ad_a : out STD_LOGIC_VECTOR (11 downto 0). type t_state is (s_idle. ad1 : std_logic.main process goes here end Behavioral. A/D driver main process process(clk) is begin if rising_edge(clk) then sclk <= not sclk. mygoo <= mygoo(0) & goo. end if. end if. counter <= counter+1. end if. if mygoo = "01" then cs_n <= ’0’. ad_b <= not ar_b(10) & ar_b(9 downto 0) & ad0. state <= s_idle. ar_b <= ar_b(10 downto 0) & ad1. clear_goo <= ’0’. cs_n <= ’1’. end if. end process. if sclk = ’1’ then ar_a <= ar_a(10 downto 0) & ad0. counter <= (others => ’0’). case state is when s_idle => sclk <= ’1’. EECS 452 – Fall 2009 Lecture 9 – Page 59/59 Mon 9/28/2009 . end case. state <= s_convert. when s_convert => clear_goo <= ’1’. if counter = 15 then ad_a <= not ar_a(10) & ar_a(9 downto 0) & ad0.