AD633

aFEATURES 4-Quadrant Multiplication Low Cost 8-Lead Package Complete—No External Components Required Laser-Trimmed Accuracy and Stability Total Error within 2% of FS Differential High Impedance X and Y Inputs High Impedance Unity-Gain Summing Input Laser-Trimmed 10 V Scaling Reference APPLICATIONS Multiplication, Division, Squaring Modulation/Demodulation, Phase Detection Voltage Controlled Amplifiers/Attenuators/Filters X1 1 1 X2 2 1 10V Low Cost Analog Multiplier AD633 CONNECTION DIAGRAMS 8-Lead Plastic DIP (N) Package 8 +VS A 7 W Y1 3 6 Z Y2 4 1 5 –VS AD633JN/AD633AN 8-Lead Plastic SOIC (RN-8) Package PRODUCT DESCRIPTION Y1 1 The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead plastic DIP and SOIC packages. The AD633 is laser calibrated to a guaranteed total accuracy of 2% of full scale. Nonlinearity for the Y input is typically less than 0.1% and noise referred to the output is typically less than 100 µV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/µs slew rate, and the ability to drive capacitive loads make the AD633 useful in a wide variety of applications where simplicity and cost are key concerns. The AD633’s versatility is not compromised by its simplicity. The Z-input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications. The AD633 is available in an 8-lead plastic DIP package (N) and 8-lead SOIC (R). It is specified to operate over the 0°C to 70°C commercial temperature range (J Grade) or the –40°C to +85°C industrial temperature range (A Grade). 1 1 10V A 1 8 X2 Y2 2 7 X1 –VS 3 6 +VS Z 4 5 W AD633JR/AD633AR W= (X1 – X2) (Y1 – Y2) 10V +Z PRODUCT HIGHLIGHTS 1. The AD633 is a complete four-quadrant multiplier offered in low cost 8-lead plastic packages. The result is a product that is cost effective and easy to apply. 2. No external components or expensive user calibration are required to apply the AD633. 3. Monolithic construction and laser calibration make the device stable and reliable. 4. High (10 MΩ) input resistances make signal source loading negligible. 5. Power supply voltages can range from ± 8 V to ± 18 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 . 3 For supply voltages less than ± 18 V. . . . Y. . . . . . . . . R ≥ 2 k⍀) A S L Model TRANSFER FUNCTION Parameter MULTIPLIER PERFORMANCE Total Error TMIN to TMAX Scale Voltage Error Supply Rejection Nonlinearity.1 V rms VO = 20 V p-p ∆ VO = 20 V f = 10 Hz to 5 MHz f = 10 Hz to 10 kHz ؎11 RL = 0 Ω Differential Common Mode VCM = ± 10 V. . . . . . . . . Y = ± 10 V W = AD633J. . . 1000 V NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. . . . . . .1 ± 0. . . .AD633–SPECIFICATIONS (T = 25؇C. . 0°C to 70°C AD633A .8 1 90 ؎1 ؎0.4 ± 0. . . functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. . . .1 ±5 1 20 2 0. . . . . . . . . . . Indefinite Storage Temperature Range .4 ؎50 VO = 0. . . . . . . . X Nonlinearity. ± 18 V Output Short Circuit Duration . . . . . . . . . . . . . Y = +10 V Y = ± 10 V. . . .01 ± 0. . . Y ≤ +10 V SF = 10.3 ± 0. . . . . AD633A (X 1 − X 2 Y1 − Y2 10 V )( )+Z Max ؎2 Unit % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale mV MHz V/µs µs µV/√Hz mV rms µV rms V mA V V mV dB µA MΩ Min Typ ±1 ±3 ± 0. . . . . the absolute maximum input voltage is equal to the supply voltage. –65°C to +150°C Operating Temperature Range AD633J . . . . . . . . .8 10 ؎30 2. . This is a stress rating only. . . . . . . . . . . Y X Feedthrough Y Feedthrough Output Offset Voltage DYNAMICS Small Signal BW Slew Rate Settling Time to 1% OUTPUT NOISE Spectral Density Wideband Noise OUTPUT Output Voltage Swing Short Circuit Current INPUT AMPLIFIERS Signal Voltage Range Offset Voltage X. . . . . . . . Results from those tests are used to calculate outgoing quality levels. . . . . Model AD633AN AD633AR AD633AR-REEL AD633AR-REEL7 AD633JN AD633JR AD633JR-REEL AD633JR-REEL7 –2– REV. Y Bias Current X. . . . . . X = +10 V Y Nulled. . . . . . . . –40°C to +85°C Lead Temperature Range (Soldering 60 sec) . Z Differential Resistance POWER SUPPLY Supply Voltage Rated Performance Operating Range Supply Current Conditions –10 V ≤ X. . . . . ± 18 V Internal Power Dissipation2 . 2 8-Lead Plastic DIP Package: θJA = 90°C/W. . . . . . . . . . . . . . All min and max specifications are guaranteed. f = 50 Hz 30 ؎10 ؎10 60 40 ±5 80 0. . . . . . . . . . E . . . . . . . . X = ± 10 V X Nulled. . . . . . Specifications subject to change without notice.00 V Nominal VS = ± 14 V to ± 16 V X = ± 10 V. . . . . although only those shown in boldface are tested on all production units. .4 ؎1 ؎0. . . . . . . . .25% ± 0. . . . . . . . . . V = ؎15 V. .0 ؎8 Quiescent ± 15 4 ؎18 6 V V mA Specifications shown in boldface are tested on all production units at electrical test. . . ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Package Description Plastic DIP Plastic SOIC 13" Tape and Reel 7" Tape and Reel Plastic DIP Plastic SOIC 13" Tape and Reel 7" Tape and Reel Package Option N-8 RN-8 RN-8 RN-8 N-8 RN-8 RN-8 RN-8 Supply Voltage . . Y CMRR X. . . . . . . . . . . 300°C ESD Rating . 500 mW Input Voltages3 . . . 8-Lead Small Outline Package: θJA = 155°C/W. . . . . Input Bias Current vs. Noise Spectral Density vs. Frequency 700 1. CMRR vs.Y INPUTS –10 –20 NORMAL CONNECTION CMRR – dB CL = 0dB –30 10k 1M 100k FREQUENCY – Hz 10M 20 100 1k 10k FREQUENCY – Hz 100k 1M TPC 1. Temperature (X. Frequency Response TPC 4. Input and Output Signal Ranges vs. Y.5 NOISE SPECTRAL DENSITY – ␮V/ Hz 600 BIAS CURRENT – nA 1 500 400 0.5 300 200 –60 –40 –20 0 20 40 60 80 100 120 140 0 10 100 TEMPERATURE – ؇C 1k FREQUENCY – Hz 10k 100k TPC 2. or Z Inputs) TPC 5. RL 10 ALL INPUTS 8 2k⍀ P-P FEEDTHROUGH – mV 100 Y-FEEDTHROUGH X-FEEDTHROUGH 10 1 6 4 0 8 10 12 14 16 18 PEAK POSITIVE OR NEGATIVE SUPPLY – V 20 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 3.Typical Performance Characteristics– AD633 100 0dB = 0. RL = 2k⍀ 0 CL = 1000pF OUTPUT RESPONSE – dB 90 80 70 60 50 40 30 TYPICAL FOR X.1V rms. Frequency REV. Frequency 14 PEAK POSITIVE OR NEGATIVE SIGNAL – V 1000 12 OUTPUT. Supply Voltages TPC 6. E –3– . AC Feedthrough vs. 4% and 0. The Z input may be used to add a further signal to the output. power measurement. particularly if this is remote.1␮F E 1 2 3 4 ERROR SOURCES Multiplier errors consist primarily of input and output offsets. The X and Y inputs will normally have their negative nodes grounded. The product of these currents is generated by the multiplying core. Basic Multiplier Connections Squaring and Frequency Doubling Inspection of the block diagram shows the overall transfer function to be: W = (X 1 − X 2 Y1 − Y2 10 V )( )+Z (1) As Figure 4 shows. Figure 1 shows the functional block diagram. a buried Zener reference. Z) X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0. X2.AD633 FUNCTIONAL DESCRIPTION APPLICATIONS The AD633 is a low cost multiplier comprising a translinear core. and frequency doublers.1␮F –15V W= E2 10V AD633JN Figure 4. E. It uses the identity: cos θ sin θ = 1 sin 2 θ 2 ( ) (3) –4– REV. Z W= (X1 – X2) (Y1 – Y2) +Z Y1 3 6 Z Y INPUT AD633JN Y2 4 1 AD633 5 –VS Figure 1. convert the output voltage to a current. X2.. However. this squarer behaves as a frequency doubler. The input may have either polarity. Functional Block Diagram (AD633JN Pinout Shown) Figure 3.25% of full scale. +15V 0. which differs from the AD633JR pinout (8-lead SOIC). The input and output offsets can be eliminated by using the optional trim of Figure 2. is achieved simply by connecting the X and Y inputs in parallel to produce an output of E2/10 V. E . The differential X and Y inputs are converted to differential currents by voltage-to-current converters. and a unity gain connected output amplifier with an accessible summing node. respectively. voltage controlled amplifiers. E. +15V 0. The X and Y nonlinearities are typically 0. the output polarity may be reversed by interchanging the X or Y inputs. but they are fully differential. automatic gain control. A buried Zener reference provides an overall scale factor of 10 V. The high impedance Z input should always be referenced to the ground point of the driven system. the differential X and Y inputs should be referenced to their respective grounds to realize the full accuracy of the AD633.1% of full scale. Connections for Squaring When the input is a sine wave E sin ωt. and configure various analog computational functions. The amplifier summing node Z allows the user to add two or more multiplier outputs. but the output will be positive. squaring of an input signal. The sum of (X × Y)/10 + Z is then applied to the output amplifier. +VS ؎50mV TO APPROPRIATE INPUT TERMINAL (e. since 50k⍀ 300k⍀ 1k⍀ (E sin ωt ) 10 V 2 = E2 1 − cos 2 ωt 20 V ( ) (2) –VS Figure 2. +VS The AD633 is well suited for such applications as modulation and demodulation. and nonlinearity in the multiplying core. where an RC network is used to generate two signals whose product has no dc term.1␮F X INPUT 1 2 3 4 X1 1 1 A 1 10V 8 X2 2 7 W X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0. This scheme reduces the net error to scale factor errors (gain error) and an irreducible nonlinearity component in the multiplying core.g. This can be avoided using the connections shown in Figure 5. Multiplier Connections Figure 3 shows the basic connections for multiplication.1␮F –15V 10V OPTIONAL SUMMING INPUT. Optional Offset Trim Configuration Equation 2 shows a dc term at the output that will vary strongly with the amplitude of the input. Note that these applications show the pin connections for the AD633JN pinout (8-lead DIP). Likewise. Scale factor error is typically 0. and in many applications the grounded inputs may be reversed (to facilitate interfacing with signals of a particular polarity while achieving some desired output polarity) or both may be driven. scale factor error. The transfer function for the divider is W ' = −(10V ) E EX +15V 0.1␮F 0.9 ωo.1␮F X INPUT 1 2 (6) E = (sin 2 ω ot ) (40V ) which has no dc component. Connections for Square Rooting AD633JN Y INPUT 1k⍀ Figure 9. the response of the circuit will be (satisfying Equation 3): Figure 7. the X input leads the input signal by 45° (and is attenuated by √2). Generating Inverse Functions X1 X2 Y1 Y2 +VS 8 W 7 R1 6 W= (X1 – X2) (Y1 – Y2) 10V 1k⍀ R1. Current Output 0. Connections for Division W = (10V ) 2 1 E 2 (sin ω ot + 45°) E 2 (sin ω ot − 45°) (4) Likewise.5% too low at ω = 0. and the Y input lags the X input by 45° (and is also attenuated by √2). Connections for Variable Scale Factor Variable Scale Factor W = (10 E ) V +15V +15V 0. The amplitude of the output is only a weak function of frequency: the output amplitude will be 0.1␮F X INPUT 1 2 3 4 X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0. such as division and square rooting. it may be desirable to use a scaling voltage other than 10 V. can be implemented by placing a multiplier in the feedback loop of an op amp. Figure 6 shows how to implement a square rooter with the transfer function Figure 8. Figure 7 shows how to implement a divider using a multiplier in a feedback loop. The summing input. S.1␮F The AD633’s voltage output can be converted to a current output by the addition of a resistor R between the AD633’s W and Z pins as shown in Figure 9.1 ω o.1␮F –15V S Inverse functions of multiplication. R2 (R1 + R2) R1 100k⍀ +S AD633JN Y INPUT 3 4 Z R2 –VS 5 0. may be used to add an additional signal to the output or it may be grounded. The connections shown in Figure 8 increase the gain of the system by the ratio (R1 + R2)/R1.1␮F –15V R IO = 1 R (X1 – X2) (Y1 – Y2) 10V R 100k⍀ Figure 6. This ratio is limited to 100 in practical applications.1␮F AD633JN AD711 0.AD633 +15V 0.1␮F –15V R1 1k⍀ AD633JN C E R 10k⍀ +15V 0. In some instances. Current Output Connections REV.1␮F 1N4148 AD633JN 3 4 OP27 E 4 0. ”Bounceless” Frequency Doubler At ωo = 1/CR.1␮F 1 2 X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0.1␮F –15V 3 4 Figure 5.1␮F 7 (5) for the condition E < 0. and ω o = 1. Since the X and Y inputs are 90° out of phase.1␮F E R 1 2 3 4 R 10k⍀ +15V W= R2 3k⍀ E2 10V X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0. E –5– . Resistors R1 and R2 are included to restore the output amplitude to 10 V for an input amplitude of 10 V.1␮F EX 1 2 X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 –15V W' = –10V E EX 0. This arrangement forms +15V –15V 1N4148 –15V W= ( 10E )V 0. The 1N4148 diode prevents the output of A2 from going negative. Output B has an additional zero at 10 kHz (and can be loaded because it is the multiplier’s low impedance output). measures the rms value of the output signal. R3. form a voltage controlled amplifier. The diode bridge. AGC AMPLIFIERS –15V Figure 10. +15V 0. Its output drives A2. equals f2 = X1 X2 Y1 Y2 +VS 8 W 7 OUTPUTB +6dB/OCTAVE OUTPUTA OUTPUT B C OUTPUT A R AD633JN Z 6 (20 V )π RC EC –VS 5 (8) 0. E . Figure 14 shows an AGC circuit that uses an rms-to-dc converter to measure the amplitude of the output waveform. if R = 8 kΩ and C = 0. f1 = 1 2 π RC Figure 12.1␮F 0 –6dB/OCTAVE OUTPUTA OUTPUT B = f − X 2 Y1 − Y2 10 V )( ) (7) CONTROL INPUT EC SIGNAL INPUT ES 1 2 3 4 X1 X2 Y1 Y2 +VS 8 W 7 R C –VS 5 0. 1/2 of an AD712 dual op amp. Voltage Controlled Low-Pass and High-Pass Filters –15V Figure 11.AD633 the basis of voltage controlled integrators and oscillators as will be shown later in this Applications section. has same response up to frequency f1. Figure 10 shows the circuit. f2. The break frequency. varies the integrator gains with a calibration of 100 Hz/V. and Zener diode D5 provide economical temperature stabilization and amplitude stabilization at ± 8. R8. This output. Voltage Controlled Low-Pass Filter dB f1 f2 +15V 0. –6– REV.1␮F W = 1+ EM 10V ECsin ␻t AD633JN Figure 13 shows two multipliers being used to form integrators with controllable time constants in second order differential equation feedback loop. the control input. C2 (proportional to C1 and C3).5 V by degenerative damping. which is at a high impedance point.1␮F –15V and the rolloff is 6 dB per octave. D1 through D4 (1N914s). The circuit can be changed to a high-pass filter Z interchanging the resistor and capacitor as shown in Figure 12. The AD633 and A1. the natural breakpoint of RC filter. The carrier and modulation inputs to the AD633 are multiplied to produce a double-sideband signal. then output A has a pole at frequencies from 100 Hz to 10 kHz for EC ranging from 100 mV to 10 V.1␮F MODULATION INPUT ؎EM CARRIER INPUT ECsin ␻t 1 2 3 4 X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0. The break frequency is modulated by EC. ES. a 50 kΩ variable resistor. The out-put from the second integrator (10 V sin ω t) has the lowest distortion.1␮F CONTROL INPUT EC SIGNAL INPUT ES 1 2 3 4 0 f Figure 11 shows a single multiplier used to build a voltage controlled low-pass filter. EC. an AD736. The accuracy is limited by the Y input offsets. the direct output of the AD633. The voltage at output B. and R4 provide regenerative feedback to start and maintain oscillation.002 µF. R2 and R5 provide controlled current output operation. The frequency control input. The transfer function of this circuit has the form IO = 1 (X R 1 dB f2 f1 +15V 0. Linear Amplitude Modulator For example. and the resulting voltages at high impedance are applied to the X inputs of the “next” AD633.1␮F Z 6 OUTPUTB AD633JN Linear Amplitude Modulator 1 + T1P 1 + T2P 1 OUTPUT A = 1 + T2P T1 = 1 = RC W1 T2 = 10 1 = W2 ECRC The AD633 can be used as a linear amplitude modulator with no external components. may need to be buffered. sets the circuit’s output level. an integrator/comparator whose output controls the gain of the voltage controlled amplifier. Voltage Controlled High-Pass Filter Voltage Controlled Quadrature Oscillator (9) then levels off to a constant attenuation of f1/f2 = EC/10. The voltage at output A is a result of filtering. The rms-to-dc converter. Feedback around the loop forces the voltages at the inverting and noninverting inputs of A2 to be equal. connected to the Y inputs. The practical tuning range of this circuit is 100:1. The currents are integrated in capacitors C1 and C2. thus the AGC. The carrier signal is fed forward to the AD633’s Z input where it is summed with the double-sideband signal to produce a double-sideband with carrier output. 1␮F 4 1 +15V 0.02␮F 1/2 AD712 AD633JN E 3 4 1 CC COMMON 8 2 VIN 0. E –7– .1␮F R10 10k⍀ R9 10k⍀ 1/2 AD712 +15V OUTPUT R8 50k⍀ LEVEL ADJUST –15V Figure 14.2␮F A2 1N4148 0.1␮F 1 2 +15V 0.1␮F X1 X2 Y1 Y2 C2 0.1␮F C1 1␮F EOUT A1 R5 10k⍀ R6 1k⍀ +15V X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0.1␮F R2 16k⍀ 0. Voltage Controlled Quadrature Oscillator R2 1k⍀ R3 10k⍀ R4 10k⍀ AGC THRESHOLD ADJUSTMENT +15V 0.1␮F –15V C2 0.1␮F +VS 7 0.AD633 D5 1N5236 D1 1N914 D2 1N914 R1 1k⍀ EC 1 2 3 4 D3 1N914 (10V) cos ␻t D4 1N914 X1 X2 Y1 Y2 +VS 8 W 7 Z 6 –VS 5 0.01␮F R3 330k⍀ (10V) sin ␻t R5 16k⍀ EC f= kHz 10V C3 0.1␮F AD736 3 CF OUTPUT 6 4 –VS –15V C4 33␮F CAV 5 C3 0.1␮F –15V +15V 0. Connections for Use in Automatic Gain Control Circuit REV.1␮F +VS 8 W 7 Z 6 –VS 5 0.1␮F R4 16k⍀ AD633JN 2 3 AD633JN –15V Figure 13. . . .49) 0. . .0532) 0. . .25) 0.375 (9. . .19 (0. . .022 (0. .008 (0. . . . . . . . . . . .355 (9. . . . . . . .33 (0. . .S. . . .2284) 1. . . . . . .0500) 0. . . .62) 0. . . . . . . 2 Change to Figure 13 .41 (0. . . .27 (0.56) 0. . . . . .10 PLANE 1. . . .0099) 0. .0688) 1. .27 (0. . . . . . . . . . . . . . .80 (0.120 (3. . . . . . .0075) Revision History Location 10/02—Data Sheet changed from REV. COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS. . . .87) 0. . . . . .27) 0. . . . . . . .150 (3. .14) 0. . . . .018 (0.0040) COPLANARITY SEATING 0. . .015 (0. . . .365 (9.00 (0. . . . . .300 (7. .26) 0. . . .50 (0. . .110 (2.10 (0. . .98) 0. . . . . . .24) 0. .275 (6. . . . . .0500) BSC 0. . . . 1 Edits to ORDERING GUIDE . .79) 0. . . .52) 0. .050 (1. . .014 (0. . . . . .51 (0.81) 0. .0196) ؋ 45؇ 0. . . . .0130) 8؇ 0. . . . . . . . .180 (4.25 (0. . .130 (3. . . .53) 0. . . . . 8 –8– REV.20) COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES. .1497) 1 6. . . Page Edits to title of 8-Lead Plastic SOIC Package (RN-8) . . .0098) 0. .02) 8 5 1 4 0. .00 (0. . . . .A.75 (0. . . . . . .310 (7.325 (8. . .38) 0. . . . . . . . .285 (7. . . INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN C00786–0–10/02(E) . . . . . . . . . . . . MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8) Dimensions shown in millimeters and (inches) 5. . . . E.135 (3. . .54) BSC 0. .295 (7. . . . .0098) 0؇ 1.81) 0. . . . . .25 (0. .46) 0. .57) MAX 0. . . .0201) 0. .015 (0. . .27) 0. .38) MIN SEATING PLANE 0.80 (0.AD633 OUTLINE DIMENSIONS 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.010 (0. . .060 (1. . . . .1890) 8 5 4 4. . .2440) 5. . . . . . .1574) 3. . .045 (1. . . . 7 Updated OUTLINE DIMENSIONS . . .80 (0. . .100 (2. . . . . . . . . . . . . E PRINTED IN U. .20 (0. . . . . . . .1968) 4.35 (0.150 (3.30) 0. . . . . . . .0160) 0. D to REV.36) 0.05) 0. . . . . .43) 0. .25 (0. .