A Non-Inverting Buck-Boost DC-DC Switching

This article has been accepted for publication in a future issue of this journal, but has not beenfully edited. Content may change prior to final publication. IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010 1 A Non-Inverting Buck-Boost DC-DC Switching Converter with High Efficiency and Wide Bandwidth Carlos Restrepo∗ , Student Member, IEEE, Javier Calvente, Member, IEEE, Angel Cid-Pastor, Member, IEEE, Abdelali El Aroudi, Member, IEEE, and Roberto Giral, Senior Member, IEEE Abstract—A novel DC-DC switching converter consisting of a boost stage cascaded with a buck converter with their coils magnetically coupled is presented. The disclosed converter has the same step-up or step down voltage conversion properties than the single inductor non-inverting buck-boost converter but exhibits non-pulsating input and output currents. The converter control-to-output transfer function is continuous between operation modes if a particular magnetic coupling is selected. The addition of a damping network improves the dynamics and results in a control-to-output transfer function that has, even in boost mode, two dominant complex poles without right half plane zeroes. An example shows that an output voltage controller can be designed with the same well-known techniques usually applied to the second-order buck regulator. Details of a prototype and experimental results including efficiency, frequency and time domain responses are presented. The experimental results validate the theoretical expected advantages of the converter, namely, good efficiency, wide bandwidth and simplicity of control design. Index Terms—Non-inverting buck-boost converter, coupled inductors, right-half-plane (RHP) zero, high efficiency, widebandwidth, high-side driver. I. I NTRODUCTION I N many converter applications such as battery charging and discharging, power factor correction, fuel cell regulation, maximum power point tracking of solar panels, a DC-DC converter is used to obtain a regulated voltage from an unregulated source. When the regulated voltage is within the voltage range of the unregulated voltage source, a step-up/stepdown DC-DC converter is required [1]–[13]. Step-up/step-down DC-DC converters with a single active ´ switch, such as buck-boost, flyback, SEPIC and Cuk topologies, have high component stresses and low efficiencies in the same operating point than the boost or the buck converter if the output voltage is greater or smaller than the input voltage respectively [14]. It is possible to combine a buck with a boost to obtain a two independently controllable switch buck-boost converter with This work was supported by the Spanish Ministerio de Ciencia e Inovaci´ n o under the projects ESP2006-12855-C03-02, CSD2009-00046, TEC200913172, DPI2010-16481 and the FPU scholarship AP2008-03305. C. Restrepo, J. Calvente, A. Cid-Pastor, A. El Aroudi and R. Giral are with the Departament d’Enginyeria Electr` nica, El` ctrica i Autom` tica, Escola o e a T` cnica Superior d’Enginyeria, Universitat Rovira i Virgili, 43007 Tarragona, e Spain. ∗ Corresponding author. Email: [email protected]. Postal Address: Avda. Pa¨sos Catalans 26, Campus Sescelades, 43007, Tarragona, Spain. Fax: ı (+34)977559605. Telephone number: (+34)977297052. size and performance comparable to those of the simple buck or boost stages [15]. For example, combining a buck in cascade with a boost results in a single inductor non-inverting buckboost converter that exhibits high performance and it is widely used in low voltage applications [4]–[8]. These converters do not operate in buck-boost mode because it is more efficient to operate them either in buck mode if the output voltage is lower than the input one or in boost mode in the opposite case [2]. There are also high efficiency non-inverting buckboost converters at higher operational voltages [12], [13] with the drawback of a complex control. In [12], the authors state that the detailed modelling of the plant and the controller is an ongoing work. In [13], two different output voltage regulators are required depending on either boost or buck mode of operation. The single inductor non-inverting buck-boost converter is used in applications where it is important to have low size and cost of the magnetic elements. However, when the voltages are high, the size of the capacitors of this converter is also important. In that case, it can be interesting to use the cascade buck-boost power converter that has two inductors, one at the input and another at the output [1], [3]. With these inductors, the input and output currents are non-pulsating, the noise level is lower and the control and the limiting of the currents can be easier than in the pulsating case. Most of the converters mentioned above, when operating in continuous conduction boost mode, have a right-half-plane (RHP) zero that makes the controller design a difficult task, limits the bandwidth of the loop and penalizes the size of the output capacitor [6]. One possible solution to these problems is a topology named KY buck-boost converter [16]. This converter has a very fast transient response, which is achieved by using switched capacitors for energy transfer, and is advisable for low power applications. The tri-state boost converter reported in [17] eliminates the RHP zero but exhibits a poor efficiency, this technique having never been applied to the buck-boost topology. In [11] a two inductor boost superimposed with a buck converter solves satisfactorily the RHP zero problem but both active switches of the structure are floating, what requires complex drivers. Another solution to the problem of the RHP zeros adopted in the work here reported is using magnetic coupling between inductors [18] combined with damping networks [19], [20]. This solution has allowed the design of high-power boost converters with high efficiency and wide bandwidth [21]–[23]. Copyright (c) 2010 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing [email protected]. Operating modes of the buck-boost converter: (a) boost mode. no parasitic effects and a switching frequency much higher than the converter natural frequencies. It also presents a wide bandwidth and low current ripples that reduce the size of the input capacitor and especially that of the output one. but has not been fully edited. Fig. the last two sections present respectively simulated and experimental results. which are respectively the logic activation signals of switches Q1 and Q2 . 2(a). This converter can operate in boost mode. . 2(b). The current and voltage typical waveforms of this converter in steady state are depicted in Fig. Assuming a continuous conduction mode (CCM) of operation. and the conclusions of this work. the use of the state space averaging (SSA) method [25] to model the converter leads to the following set of differential equations diLm (t) dt diL (t) dt = = Lets us consider the unidirectional buck-boost converter with magnetic coupling between the input and output inductors shown in Fig. one for the buck mode and another one for the boost mode. 1. Both topologies have non-minimum phase transfer functions under certain parametric conditions and have been previously proposed for battery charge/discharge regulators for satellites [24]. 1. This allows to use the same transfer function to describe the converter in both modes and simplifies the controller design. In a typical design. (b) buck mode. be observed from Fig. which permits to use a small intermediate capacitor. 2. and buck mode. As it can dv C (t) dt dv o (t) dt = = vg (t) − v C (t)(1 − d1 (t)) Lm v C (t)d2 (t) + n(vg (t) − v C (t)(1 − d1 (t))) L v o (t) − L −iL (t)d2 (t) + (iLm (t) + niL (t))(1 − d1 (t)) C iL (t) v o (t) − (1) Co Ro Co where d1 and d2 are the duty cycles of the switches Q1 and Q2 respectively and the overline stands for averaging during one switching period. the converter control is simple in comparison with the state-of-the-art. Finally. 3. Finally. IEEE TRANSACTIONS ON POWER ELECTRONICS.org. X. A damping network is added in Section III where analytical expressions are obtained to design a minimum phase transfer function. As it will be seen. and using the principles of inductor volt-second and capacitor charge balance [14]. what could reduce design costs. the steady-state expressions of the inductor currents and capacitor voltages are Copyright (c) 2010 IEEE. 3 (c) and (d) represent current and voltage waveforms in buck mode. In boost mode u2 = 1 while u1 is switching whereas in buck mode u1 = 0 while u2 switches. 3 (a) and the corresponding voltages in Fig. X. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. In the same section. A circuital procedure to obtain equations (1) is by means of the replacement of the switches in the converter by their time averaged models [26]. the proposed converter exhibits high efficiency in the desired range of operation in spite of using diodes instead of synchronous rectification. and input voltage vg (t) = Vg . VOL. Assuming that the converter is in steady-state with constant duty cycles. the turns ratio n of the transformer that avoids the need of using two transfer functions. II. Section IV focuses on a complete circuit design for the buck-boost converter and its control. Personal use is permitted. d1 (t) = D1 and d2 (t) = D2 . 1. For any other purposes. The duty cycles of u1 and u2 have been adjusted to obtain a mean output voltage of 48 V. Content may change prior to final publication. A NALYSIS OF THE B UCK -B OOST C ONVERTER WITH MAGNETIC COUPLING BETWEEN INDUCTORS + Q2 + vg + − vC Ds2 − vo Ro − (b) Fig. as in Fig. with magnetic coupling between inductors. The remainder part of this paper is organized as follows: Section II presents the key waveforms of the converter and discusses the small-signal converter model. 3. The bottom traces of each plot correspond to u1 and u2 . the currents are shown in Fig. 4(a). (a) 1:n ig Lm iLm C L iL Co The purpose of this paper is to analyze the cascaded connection of a boost and buck converter. JANUARY 2010 2 1:n ig vg + − 1:n L iL Co ig vg + − Lm iLm Q1 Ds1 C Lm + Q2 + iLm Q1 Ds1 C + L iL Co + vC Ds2 − vo Ro − vC − vo Ro − Fig. namely.This article has been accepted for publication in a future issue of this journal. In boost mode. which leads to the large signal averaged circuit of Fig. is also determined. a common characteristic of the two operation modes is that currents ig and iL are non-pulsating with triangular-shaped ripple. 3 (b). NO. as in Fig. the ripple in the intermediate capacitor voltage vC is bigger than that of the output voltage. shown in Fig. Schematic circuit diagram of the buck-boost converter with magnetic coupling between inductors. 6 iQ1 [A] vQ1 [V ] 56. For any other purposes.9 4. The duty cycles D1 and D2 are related to the new variable u as D1 = max(0. IEEE TRANSACTIONS ON POWER ELECTRONICS. u2 1 0 0 T 2T 3T (c) (d) Fig. ILm IL VC Vo = = = = Vg D2 (D2 − n + nD1 ) Ro (1 − D1 )2 Vg D 2 Ro (1 − D1 ) Vg 1 − D1 Vg D 2 1 − D1 u1 .2 54. D2 ) is given by M (D1 . the derivatives are zero or. In the border between the two modes of operation u = 1. from the DC circuit of Fig 4(b).7 6.6 53. (d) currents and voltages in buck mode with Vg = 55 V. Fig. v C and iL do not depend on the transformer turns ratio n. the DC voltage conversion ratio M (u) is continuous between the boost and buck modes of operation. u2 1 0 0 T 2T 3T (a) (b) 1 0 −1 5. It is worth noting that the DC values of the state variables v o . Personal use is permitted. X.1 0 5.org. equivalently.9 4. NO. X.8 vC [V ] i g [A] 49. u − 1) (5) (2) These equations could be also derived from (1) by noting that. u) 1 − max(0. From the output capacitor voltage Vo in (2) the voltage conversion ratio M (D1 . . 5(a).This article has been accepted for publication in a future issue of this journal.4 0 48. (c). JANUARY 2010 3 2.1 u1 .9 2.3 vQ1 [V ] iQ1 [A] 10. D2 ) ≡ Vo D2 = Vg 1 − D1 (3) With this control input.2 iQ2 [A] iL [A] vo [V ] vQ2 [V ] 48 47. as depicted in Fig.8 vC [V ] i g [A] 55.4 56. so that D1 = 0 and D2 = 1.2 54. u) (4) The new voltage conversion ratio can be expressed as follows M (u) = min(1. in steady-state.1 0 6.4 44. Let us define a single control variable u that can take the values between 0 and 2 (0 < u < 2).3 3. 3. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. Typical waveforms of the Fig 1 converter for Vo = 48 V: (a).7 10.3 3.8 1 0 0 T 2T 3T u1 . and that it could switch from one mode to another in a smooth form. Logic signals u1 (in black) and u2 (in white) indicate switch Q1 and Q2 states respectively. u2 Our goal is that the converter could operate in both boost (0 < D1 < 1 and D2 = 1) or buck (0 < D2 < 1 and D1 = 0) modes. u − 1) D2 = min(1.2 iL [A] vo [V ] vQ2 [V ] iQ2 [A] 48 47. 5(b) shows how to generate the switch activation signals u1 (t) and Copyright (c) 2010 IEEE. u2 1 0 0 T 2T 3T u1 .5 3. but has not been fully edited. VOL.1 5. Content may change prior to final publication. (b) currents and voltages in boost mode with Vg = 39 V.3 50 0 10 0 −10 48. but has not been fully edited. NO. .6 2 M(u) 1. and a symmetric triangular wave of amplitude Vramp = 1 V. VOL. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee.. the following dynamic model is obtained dx = Ax + B1 d1 + B2 d2 (9) dt where A is the state matrix and B1 and B2 are respectively the input vectors corresponding to d1 and d2 . iL (t) = IL + iL (t) v C (t) = VC + vC (t) v o (t) = Vo + vo (t) (7) u2 (t) from the control signal u. the averaged inductor currents and capacitor voltages can also be expressed in terms of their corresponding steady-state values plus some superimposed small AC variations. 4.2 1.4 0.This article has been accepted for publication in a future issue of this journal. (a) DC conversion ratio M (u) of the buck-boost converter. in the boundary between the two modes of operation. Schematic circuit diagrams of the buck-boost converter with magnetic coupling between inductors: (a) large-signal averaged model and (b) DC model.2 0. the small-signal control-to-output transfer function with respect to the duty cycle d1 is Gvod1 (s) u=1 ≡ vo (s) d1 (s) u=1 = N1 (s) D(s) (10) (b) Fig.org.6 0. Personal use is permitted. X. The small signal state-space vector x is defined as x= iLm iL vC vo T (8) 2. IEEE TRANSACTIONS ON POWER ELECTRONICS.    A=  0. X. (b) activation signal generation: comparison of control signals with a triangular signal to obtain the MOSFETs binary activation signals u1 (t) and u2 (t). iLm (t) = ILm + iLm (t) (ILm + nIL)D1 VC − Vo Ro − (b) Fig. JANUARY 2010 4 1:n ig vg + − Lm − + iLm v C d1 C + iL d2 L iL + − plus some superimposed small AC variations d1 (t) and d2 (t) respectively. Content may change prior to final publication.8 1 1. it is possible to linearize the set of differential equations (1).4 1.5 1 0. 5. + (iLm + niL)d1 vC − v C d2 Co v o Ro − vg (t) d1 (t) d2 (t) = Vg = D1 + d1 (t) = D2 + d2 (t) (6) (a) 1:n Ig Vg + − − + ILm VC D1 + ILD2 + − IL VC D2 + After these inputs are considered. where N1 (s) = Vg (Ro nCLm s2 + (Lm n − Lm )s + Ro ) D(s) = Lm CLRo Co s4 + Lm CLs3 + (LmRo Co − 2Lm nRo Co + Lm CRo + LRo Co + Lm n2 Ro Co )s2 + (Lm − 2Lm n + Lm n2 + L)s + Ro To obtain a small-signal model around a steady-state operating point.5 Linearizing (1) around the equilibrium point (2) and separating the dynamic AC small-signal terms from the DC steadystate component. 3 With the assumption that the AC variations are much smaller than the steady-state values. For any other purposes.5 0 0 1−D1 C 0 0 n(1−D1 )−D2 C 1 Co V nV D1 −1 Lm D2 +n(−1+D1 ) L 0 0 0 0 0 V D 2 0 1 −L 0 − Ro1Co 0      T u (a) B1 = − Lm (Dg1 −1) B2 = 0 − L(D1 g −1) V g − CRo (D12−1)2 g − L(D1 −1) Vg D2 CRo (D1 −1) 0 T Hence. we assume that the input voltage is constant and the duty cycles d1 (t) and d2 (t) are equal to D1 and D2 Copyright (c) 2010 IEEE. associated to the variables iLm and vc . damping the dynamics of iLm and/or vc by adding a passive network could transfer the RHP zeroes to the left half-plane (LHP). the buck-boost converter with the damping network included. 6. Coupled inductor buck-boost converter with RC type damping network and turns ratio 1:1 (n = 1). With this damping network included.[19]. Therefore.. will be analyzed. the dynamics of the zeroes of our converter in boost mode is of second order. . As it can be expected from (2). a passive network has been connected to the Copyright (c) 2010 IEEE.g. The presence of these RHP zeroes tends to destabilize feedback loops with wide bandwidth making the converter prone to oscillation [15]. This damping network can be seen as a low frequency snubber. the transfer functions Gvod1 (s) and Gvod2 (s) are coincident. and Gvod1 (s) u=1. JANUARY 2010 5 In the same way. Content may change prior to final publication. d2 (t) = D2 . Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. The dynamics of the zeroes is the inner behavior of the system when the control is regulating the output without error. X. X. e. the converter operating point for constant duty cycles d1 (t) = D1 . which is depicted in Fig. For any other purposes. the small-signal control-to-output transfer function with respect to the duty cycle d2 is Gvod2 (s) u=1 ≡ vo (s) d2 (s) u=1 = N2 (s) D(s) intermediate capacitor. n=1 2 = Gvod2 (s) u=1. The damping network consists of a series connection of a resistor Rd and a capacitor Cd connected in parallel with the converter intermediate capacitor C. GiL d1 (s) u=1. Thanks to the magnetic coupling. but has not been fully edited. the poles are attracted by the zeroes.n=1 where N3 (s) = Vg ((Lm CRo − Lm CRo D1 )s − LmD1 s +(Ro + RoD1 2 − 2Ro D1 )) (15) (D1 − 1)2 (LmCLRo Co s4 + LmCLs3 +(Lm D1 2 Ro Co + Lm CRo + LRo Co −2D1 LRo Co + D1 2 LRo Co )s2 ) + (Lm D1 2 + L 2 −2D1 L + D1 2 L)s + (Ro − 2Ro D1 + Ro D1(16) )) vg + − + Q2 Rd + + vC − Ds2 vo Ro − Cd vCd − D3 (s) = Fig. n=1 Vg R o = (12) LRo Co s2 + Ls + Ro A similar procedure can be used to determine the small-signal control-to-output transfer functions GiL d1 (s) and GiL d2 (s). n=1 = = Gvo d1 (s) GiL d2 (s) u=1.org. III. VOL. These transfer functions are also identical between the two modes of operation if n = 1. with n = 1 and the steady-state behavior of VCd . the SSA model in CCM is diLm (t) dt diL (t) dt dv C (t) dt = = = vg (t) − v C (t)(1 − d1 (t)) Lm v C (t)d2 (t) + vg (t) − v C (t)(1 − d1 (t)) − v o (t) L −iL (t)d2 (t) + (iLm (t) + iL (t))(1 − d1 (t)) C v C (t) − v Cd (t) − CRd iL (t) v o (t) − Co CRo v C (t) − v Cd (t) (17) Cd Rd 1:1 ig Lm iLm Q1 Ds1 C L i L Co (11) where N2 (s) = Vg (Ro CLm s + (Lm n − Lm )s + Ro ) If the turns ratio n is equal to 1. Gvo d1 has two RHP zeroes. 6. n=1 Vg (Ro Co s + 1) LRo Co s2 + Ls + Ro = N3 (s) D3 (s) 2 (13) (14) dv Co (t) dt dv Cd (t) dt = = D2 =1. Personal use is permitted. Following a similar procedure to the one reported in [18]. In a converter with an ideal regulation of the output voltage. NO. the inner dynamics is usually associated to the input filter.This article has been accepted for publication in a future issue of this journal. we obtain the small-signal SSA model (19) ILm = dx = Ax + B1 d1 + B2 d2 dt (19) According to (15). The modified procedure to calculate the parameter values of the passive damping network will be given in the next section. and input voltage vg (t) = Vg is Vg D2 (D2 + D1 − 1) Ro (1 − D1 )2 Vg D 2 IL = Ro (1 − D1 ) Vg VC = 1 − D1 Vg VCd = 1 − D1 Vg D 2 Vo = (18) 1 − D1 Linearizing the set of equations (17) around the operating point (18). Note that the zeroes in (15) depend on the parameters Lm and C. in a high gain closed-loop linear system. A NALYSIS OF THE COUPLED INDUCTORS B UCK -B OOST C ONVERTER WITH DAMPING NETWORK In this section. IEEE TRANSACTIONS ON POWER ELECTRONICS. Ro = 9. u = 1). are: Lm = 14 µH. NO. 8. The resulting expressions of the damping network parameters are Fig.This article has been accepted for publication in a future issue of this journal. . Co = 110 µF. the maximum frequency plotted corresponds to 50 kHz. L = 30 µH. where u = 1. With this choice.6 µF. Cd = 22 µF. The duty cycles have been chosen to have a steady state output voltage Vo = 48 V. u > 1). X.65 Lm C (25) 0 0 1−D2 −D1 C 0 1 Co V D1 −1 Lm D2 +D1 −1 L 1 − Rd C 1 Rd Cd 0 − Rd1Cd 0 V D 2 Rd C 0 1 −L 0 0 − Ro1Co 0 T B1 = − Lm (Dg1 −1) B2 = 0 g − L(D1 −1) V g − CRo (D12−1)2 0 T g − L(D1 −1) V Vg D2 CRo (D1 −1) 0 0 The transfer functions Gvod1 (s) and Gvod2 (s) have now a third order numerator and a fifth order denominator with two dominant complex poles. To test the validity range of the smallsignal model. C = 2. Circuit diagram corresponding to the PSIM simulation used to calculate the frequency response of the control-to-output transfer function. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. it is possible to design its control loop compensator in the same well-known way if the internal dynamics corresponding to the cancelled poles is sufficiently damped. Rd = 1. ζ = 1 is selected as a trade-off between the size of the capacitor and a sufficient and robust damping of the internal dynamics. but has not been fully edited. In both cases. Personal use is permitted. Vg = 48 V (border. where p(s) = Lm Rd CCd s3 + (Lm Cd + Lm C)s2 + Rd Cd s + 1 (21) Equating the coefficients of (21) to a third degree polynomial in the following factorized form p(s) = (ατ s + 1)(τ 2 s2 + 2ζτ s + 1) (22) yields the expression of the damping network capacitor (see Appendix) 2ζC(1 + 2αζ + α2 ) (23) α Since it is desired to minimize the size of the capacitor Cd . JANUARY 2010 6 where the small signal state vector x. The waveforms depicted in Fig. IEEE TRANSACTIONS ON POWER ELECTRONICS. there is a triple zeropole cancellation and the two transfer function correspond to expression (12). In the border between buck and boost operation modes. the expression of the damping resistance Rd is given by √ (1 + 2ζ) 1 + 2ζ Lm Rd = (24) 4ζ(ζ + 1) C Cd = Finally. The Bode plots of both frequency responses obtained from PSIM (switched) and MATLAB (small-signal) are superimposed for the three different values of the input voltage and are depicted in Fig. the parameters. the state matrix A and the input vectors B1 and B2 of the system are now given by x=     A=   0 0 1−D1 C iLm 0 0 iL vC vCd vo 0 0 1 T Cd = 8C.org. In this figure. Copyright (c) 2010 IEEE. a value of α = 1 is selected. whose selection will be explained in the next section. Content may change prior to final publication. and Vg = 55 V (step-down. VOL. Since this control-to-output transfer function is identical to that of a second order buck converter. We conclude that our buck-boost converter can be modelled and controlled as a buck converter for the input voltage range considered in the example. For any other purposes. The poles of the internal dynamics are the roots of the cancelled polynomials in Gvod1 (s) u=1 = Gvod2 (s) u=1 = p(s)(vg Ro ) p(s)(LRo Co s2 + Ls + Ro ) (20) In the previous section it was concluded that the small-signal control-to-output transfer functions Gvod1 (s) and Gvod2 (s) have the same expression at u = 1. this expression corresponds to the small-signal control-to-output transfer function of a buck converter. which is half of the switching frequency. X. The frequency responses are very similar in shape to a second order system with two complex poles and no zeroes. a PSIM frequency response simulation has been carried out using the switched model schematic circuit diagram shown in Fig. u < 1) have been considered. 7.5 Ω. Moreover. Three different input voltages Vg = 39 V (step-up.        Rd ≈ 0.6 Ω. 7 and compared with the MATLAB calculated frequency response corresponding to the SSA model (12). 3 were obtained for the previous list of component values. C IRCUIT DESIGN A. Capacitors that must absorb high pulsed current are ceramic. and also expression (25). TABLE I P EAK TO PEAK RIPPLE OF THE CONVERTER VARIABLES iL . VOL. Buck-boost control circuit Once the model (12) has been verified in the previous section. For any other purposes. where an estimation of the switching delays has been included. Buck-boost converter power stage The buck-boost converter is designed as a battery discharge regulator (BDR) of 13 in-series Lithium-ion battery cells. . Ds2 IV. The expressions used to calculate the ripples of iL . the power loss in Rd is vCpp (26) 12Rd The maximum output impedance in closed loop can be calculated approximately as P Rd = Zomax = 1 2πfc Co (27) a b Type IRFB4110PbF 40CPQ080GPbF Core: 77083A7 Magnetics Lm Wire size: 15 AWGb Number of turns: 13:13 C Ceramic Capacitor 3 × 2.org. The parameter values of the buck-boost converter of Fig.5 Ω.6 µF. TABLE II C OMPONENTS OF BUCK . ig CCM Ripple Buck mode (Vg − Vo )Vo T Vg L (Vg − Vo )Vo T Vg L 2 (Vg − Vo )Vo T 2R C Vg o AND vC IN Magnitude [dB] 40 v =55 V 20 iLpp igpp vCpp 10 4 0 −20 Boost mode Vg (Vo − Vg )T Vo L Vg (Vo − Vg )T (L + Lm ) Vo LLm (Vo − Vg )T Ro C −40 3 10 0 10 5 Frequency [Hz] vg=39 V vg=48 V −50 vg=55 V vg=39 V −100 vg=48 V v =55 V g −150 After performing a worst case analysis in both buck and boost modes to get the specifications at the nominal power. The output voltage Vo regulates a DC bus of 48 V. X. The maximum power output is 480 W corresponding to a load resistance Ro = 9. Description Power MOSFET Schottky Rectifier Coupled inductors B. The circuit diagram of the compensator and the PWM implemented in PSIM is presented in Fig. ig and vc are listed in Table I. Component Q1 . Multifilar equivalent. To achieve a good efficiency. If a triangular shaped vc ripple is assumed. 8 has been designed following classical rules [27]. maximum output impedance of Zomax = 150 mΩ. X. the finally selected components of the buck-boost converter power stage are the ones listed in Table II. so that an input voltage Vg range of 39 V to 55 V is considered. Personal use is permitted. 4 W Cd MKT Capacitor 22 µF The capacitance depends on the operating voltage. The third order compensator transfer function is Gc = u (τ3 s + 1)(τ4 s + 1) =K vo s(τ1 s + 1)(τ2 s + 1) (28) where the compensator parameters has been selected as follow: τ1 = 1 µs. maximum power dissipation in the damping resistor PRd = 4 W. and K = 210 s/V. Q2 Ds1 . For Vc = 48 V the equivalent capacitance is 2. Kool Mµ core inductors have been chosen by their low-cost and availability. the next step is to design the control loop compensator. 7) while the white lines correspond to MATLAB simulation of the linear small signal model (12). 8. τ3 = τ4 = 1/(2π) ms. but has not been fully edited. IEEE TRANSACTIONS ON POWER ELECTRONICS. The ESR (Equivalent Series Resistance) of Cd is much smaller than Rd . All components are rated up to 100 V. Frequency response of the small-signal control-to-output transfer function. The black lines correspond to the simulation of the switched model using PSIM (Fig. Content may change prior to final publication. JANUARY 2010 7 80 vg=39 V 60 vg=48 V vg=55 V vg=39 V v =48 V g g where fc is the crossover frequency of the voltage loop. N-channel MOSFETs with low on-resistance and fast Schottky diodes have been selected.This article has been accepted for publication in a future issue of this journal. Permission must be obtained from the IEEE by emailing [email protected] CONVERTER Phase [deg] −200 −250 3 10 10 4 10 5 Frequency [Hz] Fig. 6 have been selected according to specifications of input and output peak to peak current ripples of igpp = 12 A and iLpp = 4 A.6 Ω and the switching frequency is 100 kHz.2 µFa X7R dielectric Co MKT Capacitor 5 × 22 µF Core: 77083A7 Magnetics L Inductor Wire size: 15 AWGb Number of turns: 20 Rd Damping Resistor 1. τ2 = 2 µs. A compensation network for the buck converter-like transfer function plotted in Fig. 9(a). NO. The existence of delays impedes having extreme duty cycles and causes a nonlinearity in the transitions between boost and Copyright (c) 2010 IEEE. i. a third mode of operation is permitted in an adjustable small vicinity zone between buck and boost modes [7].7 V and a DC offset of 1. 10.7 + overlapping adjustment) in the manner presented in Fig. The most critical operation of the driver occurs in pure boost mode because the bootstrap capacitor CB must be sufficiently charged to keep Q2 ON for as long as needed.org. DC . permitting that CBaux charges to 15 V through DA . In addition to the Copyright (c) 2010 IEEE. For any other purposes. When TD turns OFF. The circuit schematic diagram of the buck-boost control experimental stage is shown in Fig. Scheme of the buck-boost driver with a modified bootstrap circuit and auxiliary supplies. The experimental response of the buck-boost regulator to a low-frequency triangular input voltage going from 36. Buck-boost driver with modified bootstrap An IR2110 integrated driver has to switch the low side NChannel MOSFET in the boost stage Q1 . The new operation mode is called buck-boost mode because the previous two modes overlap in interleaving-like manner. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. DB . 9(c). Since the source of Q2 is always at a level higher than 15 V. To mitigate these problems. 11 shows pictures of the power stage and the control circuit of the buck-boost regulator prototype. A similar charge pump driver that refreshes the bootstrap capacitor with the use of the boost control pulses is shown in Fig. A couple of cascaded linear regulators provide the supply voltages (15 V and 5 V) of the driver and control circuit from the input voltage. and the other one is used to get the signal (u − 0.4 V. The overlapping adjustment is achieved by reducing the displacement between the signals that generate u1 and u2 when compared with the triangular signals. In these circumstances.e. 10. an amplitude of 0. C.8 V to 55. has been added to recharge CB . TD . an adjustable oscillator. DC and TD . In buck operation. and an additional bootstrap circuit made of CBaux . the capacitor of conventional bootstrap circuits could be insufficiently charged. JANUARY 2010 8 buck modes [28].8 V is depicted in Fig. Fig. where a charge pump topology with an external clock signal is used. A solution of this problem is presented in [29]. One of the error amplifiers is used to implement the compensator (28) to obtain the signal u. Fig. but has not been fully edited. The main component of the control system is the dual PWM controller integrated circuit TL1451A that generates the switch activation signals u1 (t) and u2 (t). The boost pulses turn on the auxiliary Darlington transistor TD . E XPERIMENTAL RESULTS (c) Fig.5 V.This article has been accepted for publication in a future issue of this journal. and dual common-emitter output transistor circuits.. This single monolithic chip has two error amplifiers. NO. IEEE TRANSACTIONS ON POWER ELECTRONICS. it is then necessary to refresh the capacitor charge. X. [28]. X. To avoid the malfunction of the converter in boost mode. the usual bootstrap path through diode DA will be cut OFF. This figure shows an example of the driving signals u1 and u2 generation. In these two previous modes a classical bootstrap circuit would operate correctly. (a) (b) Fig. (b) buck-boost control circuit diagram. In buck-boost mode both Q1 and Q2 are switched in the same period. 9(b). a reference voltage of 2. TC starts conducting providing through DB a current path to recharge CB from CBaux . both MOSFETs can switch in the same period but their switching instants are almost π rad out of phase. The triangular signal oscillator has been adjusted to have a frequency of 100 kHz. (c) an example of driving signals generation. 9. and the high side N-Channel MOSFET of the buck stage Q2 . V. and a couple of resistors. VOL. Content may change prior to final publication. Schematic of: (a) the compensator Gc and the dual PWM simulated in PSIM. The direct polarization of DC keeps TC OFF. . Q1 should be always OFF while Q2 switches.12 where the waveform of the output voltage could be compared with its corresponding simulation. A bootstrap circuit is needed to supply the floating voltage to drive Q2 . Personal use is permitted. TC . 9(b) shows a variable resistor that permits the empirical overlapping adjustment that guarantees a proper charging of the bootstrap capacitor by switching the high side MOSFET when the boost driving pulses are narrower than 2%. IEEE TRANSACTIONS ON POWER ELECTRONICS. ranging from 0 V to 1 V. VOL. X. 15. NO. The input voltage range ensures that in both simulation and experimental measurements the converter works in its three operation modes. 14(b). (a) 97. (b) buck-boost control. Energy conversion efficiency for Vo = 48 V as: (a) a function of the output current iRo for different input voltage vg levels.5 iR = 4 A i =5A R η [%] 96 95. (d) Power analyzer. Experimental configuration of the measurement of efficiency: (a) buck-boost converter. A Voltech PM6000 Power Analyzer with calibrated precision shunt resistors is used to measure the input and output currents.5 95 94. 14. 14(a). The frequency measurements have been obtained using Copyright (c) 2010 IEEE.5 vg= 39 V v = 43 V g η [%] 96 95. The output voltage is well regulated and exhibits a smooth behavior in all the transitions between modes. The oscillogram on the right shows the equivalent signals that correspond to the outputs of the dual PWM controller that are in the 0 V to 5 V range. whereas in Fig. The efficiency measurements take into account the consumption of the drivers and control stages. JANUARY 2010 9 97. but has not been fully edited. (b) dual PWM control stage. the simulated logic signals u1 and u2 .5 97 iR = 2 A o o o o o o input and output voltages. The sampling capabilities of the digital oscilloscope have permitted to capture the switching noise in the output voltage waveform.5 iR = 6 A iR = 8 A iR = 10 A 40 45 vg [V] 50 55 (b) Fig. TABLE III C ROSSOVER FREQUENCY (CF) AND PHASE MARGIN (PM) FOR DIFFERENT INPUT VOLTAGES Simulated Fig. (c) DC power supply. an estimation of delays and loses have been taken into account.5 95 94. For any other purposes. These good results are due to the use of the same controller in all the operation modes. Since some switching losses penalty is paid in buck-boost mode. (b) a function of the input voltage vg for different output current iRo levels. Regulator prototype (a) buck-boost power stage. Permission must be obtained from the IEEE by emailing [email protected]. Vg [V] 39 48 55 CF [kHz] 13 18 17 PM [deg] 54 62 65 Experimental CF [kHz] 11 18 16 PM [deg] 51 61 65 Figure 13 shows the experimental setup for measuring the efficiency of the hard-switching buck-boost converter. In the simulations. X. for a given current the maximum efficiencies are attained in boost and buck modes when the input voltage is close to the desired output level. efficiencies as a function of the output current iRo for different input voltage vg levels are shown in Fig. are also depicted on the left. 11.5 2 vg= 47 V v = 48 V g vg= 51 V vg= 55 V 4 (a) (b) iR [A] o 6 8 10 Fig.This article has been accepted for publication in a future issue of this journal.5 97 96. 96. There is less switching noise in boost mode because it is attenuated at the output by a third order filter while the buck stage has only a second order filter between its switches and the output. the horizontal axis is the input voltage and the output current is the parameter of the set of curves. . The energy conversion PSIM-simulated and experimental Bode plots of the regulator loop gain are illustrated in Fig. (e) oscilloscope. Other techniques like multiphase and ZVS [12] or dynamic adjustment of the switching frequency [13] are also possible. 13. (f) DC electronic load. Content may change prior to final publication. The maximum efficiency obtained of about 97% would be improved if the diodes could be substituted by synchronous rectifier MOSFETs [12]. Personal use is permitted. [13]. near buck-boost and buck modes respectively. the buck stage MOSFET is continuously ON. which has required a specially built bootstrap driver for the buck stage high-side N channel MOSFET. 12. Content may change prior to final publication. 17(a) and 17(b). whereas in boost mode. Furthermore. For a given specification of output impedance and voltage ripple. AC coupling). the parameters of the magnetic components vary with the mean average current flowing through them.5 1 0. JANUARY 2010 10 Vg [V] 60 40 20 100 150 200 250 300 Time [ms] Vo [V] 48. we believe that the proposed converter could offer a solution with larger magnetic components but smaller capacitors than other state-of-the-art topologies. close to zero or to one. CH1: Vg (10 V/div). In spite of the differences observed between the simulated and the experimental frequency responses. Figs. Permission must be obtained from the IEEE by emailing [email protected] 100 150 200 250 300 Time [ms] (a) (b) Fig. but has not been fully edited. Also. when the input and output voltages are close.5 1 0. 17.5 0 −0.org. For each input voltage. a wide bandwidth is achieved since the crossover frequency is between one tenth and one fifth of the switching frequency. CH2: Vo (1 V/div. For instance.This article has been accepted for publication in a future issue of this journal. In all cases. the table shows remarkably similar results in all cases. The converter operates usually in the other more efficient modes in which there is only one periodically switching MOSFET. are required to obtain a smooth transition between operation modes. and 18 show simulated and experimental transient responses to load changes for different constant input voltages corresponding to boost. In buck mode. VI. the output voltage is well regulated and the transient deviations are within the desired boundaries. The main discrepancy appears near the buck-boost mode as it is illustrated in Figs. Since both input and output currents are of non pulsating nature there Copyright (c) 2010 IEEE. VOL.5 48 47. For any other purposes. the load current has been changed from 10 A to 5 A in the top subplots (a) and (b) and back form 5 A to 10 A in the bottom subplots (c) and (d). this noise is attenuated by the output LC filter or rejected by the control loop and has little effect on the output voltage. X. Some of the differences that can be observed between simulated and experimental results for vg = 48 V are attributed to the nonlinearities in the transitions between modes mentioned previously. switching pulses can be skipped and the resulting ripple contains components at frequencies below of the converter switching frequency [28]. For this reason. Like in a buck regulator. boost pulses u1 and buck pulses u2 for changes in the input voltage. 18(d) where a couple of buck pulses are missed and an intermediate unexpected boost pulse appears. IEEE TRANSACTIONS ON POWER ELECTRONICS. Other differences are mainly due to nonlinearities in some passive components of the experimental prototype. X. In the buck-boost region both MOSFET are allowed to switch in the same period but this overlapping is permitted only for a narrow range of nearly equal input and output voltages to improve the efficiency.5 100 150 200 250 300 Time [ms] u1 [V] 1. Personal use is permitted. the capacitance of the intermediate capacitor exhibits a strong dependency on the applied voltage as has already been noted in Table II. CH4: u2 (5 V/div). .5 0 −0. NO. but they are not possible to achieve in practice due to the unavoidable switching delays. Simulation and experimental results of a prototype verify the predicted wide control bandwidth due to the absence of RHP zeroes. the input current and the intermediate capacitor voltage are also depicted. the MOSFET of the boost stage is always OFF. buck and buck-boost. with a reasonable agreement between simulated and measured variables. The combination of a coupling and a damping network at the intermediate capacitor provides a minimum-phase control-to-output transfer function with two dominant complex poles. output voltage Vo . Extreme duty cycles. CH3: u1 (5 V/div). A high efficiency is obtained by operating the converter switches in three regions depending on the input-output voltage ratio: boost.5 100 150 200 250 300 Time [ms] u2 [V] 1. The crossover frequency (CF) and phase margin (PM) are calculated and listed in Table III for each input voltage value. The transient dynamics of these variables is damped as expected.The skipped pulses also appear in transients like the one depicted in Fig. the phase margins indicate that the feedback system is stable for the desired input voltage range. (a) PSIM simulation (b) Waveforms measured. C ONCLUSION A new non-inverting buck-boost DC-DC switching converter has been obtained by magnetically coupling the input and output inductors of a cascade connection of a boost and a buck stages. 16. timebase: 20 ms/div. a frequency response analyzer (FRA) Venable 3120. Waveforms of input voltage Vg . In addition to output voltage and current. In our prototype. This frequency response has the three above mentioned different modes of operation that are achieved by varying the value of the input voltage vg . Expression (A. NO. yields (24).6) Copyright (c) 2010 IEEE. X.This article has been accepted for publication in a future issue of this journal.4). Future works contemplate also a bidirectional implementation of the switches that could provide even higher conversion efficiencies. A PPENDIX DAMPING NETWORK PARAMETER CALCULATION Equating (21) and (22) gives the following set of equations ατ 3 = Rd Cd Lm C τ 2 (2αζ + 1) = Lm (Cd + C) τ (α + 2ζ) = Rd Cd Dividing (A.3) τ2 = Lm C(α + 2ζ) α (A. Content may change prior to final publication.org. The capability of cycle-by-cycle limiting the input and/or output converter currents offers interesting possibilities to many applications like battery. a) Simulated magnitude. From (A. are two or more possible current control strategies. For any other purposes. Personal use is permitted.4) in (A. Loop gain Bode plots of the buck-boost converter: boost mode for vg = 39 V.1) (A.5). particularized for α = 1. 15. controlling the converter in current mode is a work in progress. JANUARY 2010 11 20 v =39 V g g g 20 v =39 V g g g 15 10 v =48 V v =55 V 15 10 v =48 V v =55 V Magnitude [dB] 5 0 −5 −10 −15 −20 4 Magnitude [dB] 5 0 −5 −10 −15 −20 4 10 10 Frequency [Hz] (a) −100 −110 −120 −100 −110 −120 Frequency [Hz] (b) Phase [deg] −130 −140 −150 −160 −170 −180 v =39 V g g g Phase [deg] −130 −140 −150 −160 −170 v =39 V g g g v =48 V v =55 V 10 4 v =48 V v =55 V −180 10 4 Frequency [Hz] (c) Frequency [Hz] (d) Fig. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. ACKNOWLEDGMENT The authors would like to thank Jos´ Maria Bosque for his e aid in the construction of the prototype. it is straightforward that Rd = τ (α + 2ζ) Cd (A.3) and (A. supercapacitor. IEEE TRANSACTIONS ON POWER ELECTRONICS. X. (A.2) and isolating Cd gives (23). For that reason. VOL.1) by (A. .3) and isolating τ 2 yields (A.2) (A. d) Experimental phase. c) Simulated phase. but has not been fully edited.4) Substituting (A. and Luis Mart´nezı Salamero and the anonymous reviewers for their valuable comments. Another open problem is the converter operation at light loads where several discontinuous conduction modes can appear. buck-boost mode for vg = 48 V and buck mode for vg = 55 V. b) Experimental magnitude.5) Since the derivative of (23) with respect to α is 2ζC(α2 − 1) dCd = dα α2 Cd has a minimum for α = 1. PV panel or fuel cell energy management. Ind.25 47. “Non-inverting buck-boost [10] vo [V] vc [V] [11] [12] [13] [14] [15] [16] [17] [18] converter for fuel cell applications. Apr. J. 2009.” IEEE Trans.. Lee. and F. CH1: vc (5 V/div). Power Electron. pp. Ruan. 2008. Guinjoan. 2008. Khaligh. Nov. pp. 263–268. pp. Yau. S.2 47. Li. “Two types of KY buck-boost converters. and S.. Emadi. L. vol..” IEEE Trans. 499–509. no. APEC. S. W. A. J.-H. Reg.04 4. pp. 5. and Q. Conf.. Martinez-Salamero.05 4. no. 19th IEEE Appl. 1002–1015. NO. Biel. “Digital combination of buck and boost converters to control a positive buckboost converter and improve the output transients. 24. no. Fundamentals of Power Electronics. 2004. Khaligh.95 60 8 8. Banerjee. F. 16. pp.. 2001. Mar.5 (a) 25 20 Current [A] 15 10 5 0 7. Huang. buckboost dc-dc converter. Power Electron. Conf. X. “A novel low-loss modulation strategy for high-power bidirectional buck + boost converters. IEEE Ind. and A. pp. vol. CH2: vo (500 mV/div.-C. A. Circuits Syst.08 4. Fernandez. 776–786. Lee. (c) and experimental measurements (b). Rasmussen. H. Sahu and G. 2010. A. dynamic.1 Time [ms] 4. Ho. Rincon-Mora. Chakraborty. (d) of the converter main variables when the load current changes from 10 A to 5 A and back to 10 A while the input voltage is Vg = 39 V. 4.3 (c) (d) Fig. Tseng. D. 39 –41. synchronous buck-boost converter for portable applications.12 4. JANUARY 2010 12 20 Current [A] 15 10 5 0 3.” Power Engineer. and A. “A low voltage. 2009. Power Electron. pp. X.” IEEE Trans. [9] E. and A. 21..” in Proc. “Sliding-mode control design of a boost-buck switching converter for ac signal generation. “Buck-boost PWM converters having two independently controlled switches. H. 25th IEEE Appl. 19. noninverting. pp. [8] Y. vol. Nov. no.5 8. noninverting. “A compensation technique for smooth transitions in a noninverting buck-boost converter. pp. Vidal-Idiarte.2 8. 56. [3] T. Fossas. I. 1589 –1599.” IEEE Trans. 25.98 60 4 4. pp. Hwu and Y.15 Time [ms] 8. vol. pp. Power Electron. IECON. 8. and J. Maksimovic. Shiau. Gaboriault and A. but has not been fully edited.” in Proc. Chen. Content may change prior to final publication. and R. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. 2.95 8 8. [2] J. 24. vol. D.” in Proc. Power Electron. vol. Electron. pp. Aug. Feb.. 443–452. 6. pp. Power Electron. Erickson. Mar.1 8. Ren. 2009. “Using magnetic coupling to eliminate right half-plane zeros in boost Copyright (c) 2010 IEEE. Chen. K. Conf. 2001. H. 24. Notman. and R.” in Proc. no. Sustainable Energy Technol. IEEE TRANSACTIONS ON POWER ELECTRONICS. 2010. 719–730. PSIM simulations (a). 2. Chen. VOL. 51.. Chen. and K.” IEEE Trans. no. 18. E. Mar. 2nd ed. W. pp. 24. ICSET. M. 4. Crocker and N. [7] Y. vol.This article has been accepted for publication in a future issue of this journal.15 Time [ms] 8.05 8. 1539 – 1551. Wu. Expo. 8. “Buck boost regulator (B 2 R) for spacecraft solar array power conversion. 1267–1279. Papers. Power Electron. A. Cheng. P. 2970–2980. pp. For any other purposes.. Black traces shows the simulated output current iRo and output voltage vo while the input current ig and the intermediate capacitor voltage vc are in white. and E.5 50 48 40 4 4. “Analysis and design of a lowstress buck-boost converter in universal-input PFC applications. Emadi. 24. Aug. “Three-mode dualfrequency two-edge modulation scheme for four-switch buck-boost converter. 2004..1 8. Specialists Conf. O. Khaligh.5 vo [V] vc [V] (b) 50 48 40 7. 2009. vol. X. 2009. APEC. 320 – 329.1 Time [ms] 4.2 8. 2004. vol. vol. 3.-K. 1411–1415.. 2. Chavarria.15 4. “A current-controlled tristate boost converter with improved performance through RHP zero elimination. Power Electron. AC coupling).14 4. PESC. Erickson and D. vol. Qian.-J.-H. Feb. Power Electron. 855–860.-Q. Erickson. Valderrama. [4] M. Maksimovic. Patra. Mourra. 32nd IEEE Annu. A. 3. 736– 741. “Hybrid buck-boost feedforward and reduced average inductor current techniques in fast line transient and high-efficiency buck-boost converter.-J. pp. 2009. Power Electron. Conf. no. 1st IEEE Int. “Fast and furious [electric dreams]. Aug. Expo. no. no. 3. 2.02 4. CH3: ig (5 A/div) and CH4: iRo (5 A/div).” IEEE Trans. Waffler and J. Jun. X.” IEEE Trans. 2006. Power Electron.05 8.” in Proc.06 4. J. 34th Annu.” IEEE Trans. . Kolar.. R EFERENCES [1] D. no.org. Electron. Schaltz.. May.” IEEE Trans. Cooper.3 48. 2004. no. Kapat. vol. C. “A high efficiency. Mar. Personal use is permitted. [5] P. Tonicello. R.-E. Kluwer Academic Publishers.. vol.16 48. “Stability analysis of a noninverting synchronous buck-boost power converter for a solar power management system. Soc.-J. Calvente.25 8. [6] B. and C. 1313–1319.” IEEE Trans. Maksimovic. 15 4.15 Time [ms] 8. no. E.” IEEE Power Electron Lett. 18–34. Esteve. Expo.1 Time [ms] 4. 2003.” in Proc. as Ingeniero Electricista and Master en Ingenier´a ı El´ ctrica in 2006 and in 2007.02 4.” in Proc. 32nd IEEE Annu. Ejea.95 8 8. J. 2004. Expo.org. Martinez-Salamero.06 4.” in Proc. V. Jordan. Sanchis-Kilders. Garrigos. Specialists Conf. Power Electron. 10.98 55 4 4. E.” Texas Instruments. “Dynamic optimization of bidirectional topologies for battery charge/discharge in satellites. in 2008. “Soft switching bidirectional converter for battery discharging-charging. “Bidirectional high-power high-efficiency non-isolated step-up dc-dc converter. (d) converter main variables for the same load changes of Fig. He is currently working toward the Ph.15 Time [ms] 8. pp. He o obtained the Master en Ingenier´a Electr´ nica from ı o the Universitat Rovira i Virgili de Tarragona. 39th IEEE Annu. M. “Zero dynamics-based design of damping networks for switching converters. PESC. vol. Copyright (c) 2010 IEEE. Conf. Power Electron. and J. and A. Specialists Conf. Garces. Jahns. “Optimal single resistors damping of input filters. Jun. Power Electron. 2006..08 4. J. Maset. Escola T` cnica o e a e Superior d’Enginyeria. Middlebrook and S.” in Proc. Electron. Spruijt. no.2 8. JANUARY 2010 13 12 10 Current [A] 8 6 4 2 3.2 8. Van Dijk. Spain. [19] [20] [21] [22] [23] [24] [25] [26] converters. 6. J. Specialists Conf. 1.” IEEE Trans. J. pp.5 40 4 4. (c) (d) Simulated (a).. 17.. Power Electron. A. Ejea.. Nov.05 4. E. Klaassens.3 Fig. Mar. Maksimovic. pp. 4.1 8. vol. “Analysis of PWM nonlinearity in noninverting buck-boost power converters. Personal use is permitted. vol. 1994–1999. 603–609. Esteve. Maset. APEC. (c) and measured (b). and A. 2. L. J. Power Electron. Maset. Romero. R. APEC. 126–131. but has not been fully edited. Leyva.5 8. “Pwm-switch modeling of dc-dc converters.5 50 48 40 7. Calvente. Calvente.04 4. and A. J. 2001.12 4. no. Mar. 4. Instruments.. P. vol. Jun. L. 1976. Feb. Jun. V. E. “Designing with the TL5001 PWM controller. 37th IEEE Annu. B. “A self-boost charge pump topology for a gate drive high-side power supply. with honors. For any other purposes.05 8. Ferreres. Power Electron. 1995. Calvente. IEEE Power Electron. Universitat Rovira i Virgili de Tarragona. Aplication Report SLVA034A. pp. Carlos Restrepo (S’10) graduated. X. A. Oct.. O’Sullivan.” in Rec. Jun.” in Proc. R. To be published. Jordan. pp. Conf. Aerosp.1 Time [ms] 4. 3741–3747. vo [V] vc [V] [27] T.. ´ R. Electron. 2006. [28] R.. vol. IEEE TRANSACTIONS ON POWER ELECTRONICS. Specialists Conf.25 8. 2.5 45 47.” IEEE Trans.. pp. 1292–1303. . Content may change prior to final publication. V. 659 – 665.” IEEE Trans. J. 21st IEEE Appl.. 16 and Vg = 46 V. X. NO. Syst. 1999. 58–62. Expo. E.05 8. Jordan. Park and T.25 47. “A general unified approach to modeling switching-converter power stages. Syst. Ferreres. Cuk. Garrigos. 1–7. Tarragona.95 60 vo [V] 50 vc [V] 48 (b) 8 8.D. P. Esteve.14 4. APEC. A. Sanchis.16 48. J. pp. E. Martinez-Salamero. 2. 1073–1079. VOL. “Bidirectional high-efficiency nonisolated step-up battery regulator.. pp. Ejea.1 8.” in Proc. Paul and D. 1995. A. 2003. His main research interests includes fuel cell modelling and power converters design. D.3 48. PESC. and J. J. J. Aerosp.2 47 (a) 20 Current [A] 15 10 5 0 7. pp. degree in the Departamento d’Enginyeria Electr` nica. Ferreres. 39. A. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. Colombia. Sanchis-Kilders. J. pp. Conf. 19th IEEE Appl. El` ctrica i Autom` tica. from the e Universidad Tecnol´ gica de Pereira. E. Calvente. J. Calvente. and B. Capel. PESC. 2008. Erickson.This article has been accepted for publication in a future issue of this journal. [29] S. respectively.. Garces. vol. Garrigos. 14th IEEE Appl. Power Electron. El` ctrica i o e Autom` tica. From February 2008 to July 2008.D degree (with honors) from Universitat Polit` cnica de Catalunya. X.95 60 8 8. Toulouse. in 1998.S.This article has been accepted for publication in a future issue of this journal.2 8. stability problems.04 4. He has participated in different Spanish domestic and cooperative international research projects. VOL. Systems and Signal Processing.16 48. Spain.D. France.15 Time [ms] 8.25 8.02 4. (c) and measured (b). He is currently an Associate Professor with the Departamento dEnginyeria Electr` nica. Spain. Tetouan. Manizales.5 55 48 50 4 4.1 8. Content may change prior to final publication. Spain.25 47. Tarragona. Barcelona. He obtained the graduate degree in physical science from Facult des sciences. His research interests are in the field of structure and control of power conditioning systems for autonomous systems. He received the Ph. International Journal of Sound and Vibration and Nonlinear Dynamics.05 8.1 8. Reims.1 Time [ms] 4. I. He is a member of the GAEI research group (Universitat Rovira i Virgili) on Industrial Electronics Copyright (c) 2010 IEEE. Toulouse. International Journal of Power Electronics.org. JANUARY 2010 14 10 Current [A] 8 6 4 2 3. he was a visiting scholar at the Centre de Recherche en Sciences et Technologies de Communications et de l’Informations (CReSTIC). El` ctrica i Autom` tica. He received the M. France in e 2005 and 2006.14 4. Escola T` cnica o e a e Superior dEnginyeria. 18. power factor correction.06 4. X. . chaotic dynamics. e Barcelona.05 4. where he became an associate professor in 2001 and a full-time tenure Associate Professor in 2005.5 55 48 50 7. respectively. bifurcations and control. Spain.15 4. Tarragona. nonlinear phenomena. Spain e in 2000. and from Institut National des Sciences Appliqu` es. NO. He is currently an associated professor at the Departament dEnginyeria Electr` nica. where he is working in the fields of power electronics and control systems. He has published more than 150 papers in scientific journals and conference proceedings. He is a reviewer for IEEE Transaction on Circuits and Systems part. France.95 8 8. LAAS-CNRS Toulouse. Javier Calvente (S’94-M’03) received the Ingeniero de Telecomunicaci´ n degree and the Ph.D. Universitat Rovira i Virgili (URV). respectively.2 8. Universitat Rovira i Virgili. Circuits. France. Electrical Engineering and Automatic Control.Regular papers and II Express Briefs. e degree from Universitat Polit` cnica de Catalunya. Tara ragona. Spain. degree in design of microelectronics and microsystems circuits in 2003 from Institut National des Sciences Appliqu` es. Morocco.5 (a) vo [V] vc [V] (b) 10 Current [A] 8 6 4 2 7. in e 1995.12 4. IEEE Transactions on Industrial Electronics. Barcelona.3 48. International Journal of Control.5 8.3 Fig. and the Ph. Technical School of Universitat Rovira i Virgili (URV). During the period 1999-2001 he was a visiting Professor at the Department of Electronics. vo [V] vc [V] Angel Cid-Pastor (S’99-M’07) He graduated as Ingeniero en Electr´ nica Industrial in 1999 and as o Ingeniero en Autom´ tica y Electr´ nica Industrial a o in 2002 at Universitat Rovira i Virgili. IET Electric Power Applications. conducting research on modeling of power Electronics circuits for energy management. but has not been fully edited. IEEE Transactions on Power Electronics. For any other purposes. o degree from the Universitat Polit` cnica de Catalunya e (UPC). Abdelali El Aroudi (M’00) was born in Tangier (Morocco).1 Time [ms] 4. International Journal of Systems Science. (c) (d) Simulated (a). Universidad Nacional de Colombia. Tarragona. His research interests are in the field of power electronics and renewable energy systems. in 1994 and 2001.05 8. He was a visiting scholar with Alcatel Space Industries. IEEE TRANSACTIONS ON POWER ELECTRONICS.15 Time [ms] 8. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. Personal use is permitted.08 4.2 47. Spain. in 1973. Universit´ Abdelmalek Essadi. During the period September 07-January 08 he was holding a visiting scholarship at the Department of Mathematics and Statistics. (d) converter main variables for the same load changes of Fig.98 60 4 4. 16 and Vg = 55 V. Escola T` cnica Superior dEnginyeria.D. JANUARY 2010 15 and Automatic Control whose main research fields are power conditioning for vehicles. X. He is currently an Associate Professor with the Departament dEnginyeria Electr` nica. satellites and renewable energy. . Tarragona. and 1999. 1994. South America and Africa. Copyright (c) 2010 IEEE. in 1991.S. VOL. For any other purposes. and the Ph.org. Content may change prior to final publication. NO. where he is working in the field of power electronics. X. Permission must be obtained from the IEEE by emailing pubs-permissions@ieee. Unia e versitat Rovira i Virgili. degree in ingeniera t´ cnica de telecomunie caci´ n.S. Roberto Giral (S’94-M’02-SM’10) received the B.This article has been accepted for publication in a future issue of this journal. Barcelona. the M. Spain. He has given invited talks in several universities in Europe. El` ctrica i Auo e tom` tica. IEEE TRANSACTIONS ON POWER ELECTRONICS. but has not been fully edited. Personal use is permitted. degree in ingeniera de telecomuo nicaci´ n. (with honors) degree from o the Universitat Polit` cnica de Catalunya. respectively. e Spain.