A High-Efficiency Positive Buck_Boost

4240IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 9, SEPTEMBER 2013 A High-Efficiency Positive Buck–Boost Converter With Mode-Select Circuit and Feed-Forward Techniques Jiann-Jong Chen, Member, IEEE, Pin-Nan Shen, and Yuh-Shyan Hwang, Member, IEEE Abstract—This paper presents a high-efficiency positive buck– boost converter with mode-select circuits and feed-forward techniques. Four power transistors produce more conduction and more switching losses when the positive buck–boost converter operates in buck–boost mode. Utilizing the mode-select circuit, the proposed converter can decrease the loss of switches and let the positive buck–boost converter operate in buck, buck–boost, or boost mode. By adding feed-forward techniques, the proposed converter can improve transient response when the supply voltages are changed. The proposed converter has been fabricated with TSMC 0.35-μm CMOS 2P4M processes. The total chip area is 2.59 × 2.74 mm2 (with PADs), the output voltage is 3.3 V, and the regulated supply voltage range is from 2.5–5 V. Its switching frequency is 500 kHz and the maximum power efficiency is 91.6% as the load current equals 150 mA. Index Terms—Feed-forward techniques, mode select, positive buck–boost converter. Fig. 1. Ratio of inductor current versus load current in three modes. Fig. 2. Output voltage versus the decreasing battery voltage. I. INTRODUCTION ECENTLY, with the flourishing of portable devices and the development of semiconductor manufacturing technology, conversion efficiency, power consumption, and the size of devices have become the most important design criteria of switching power converters [1]–[9]. Power converters are often applied to LED products, notebooks, mobile phones, and car electronics products. For portable applications, in order to provide consumers better conveniences, how to extend battery life and improve the conversion efficiency of power converters are challenges for designers. Therefore, it is essential to develop accurate switching power converters, which can reduce more wasted power energy [10]. The positive buck–boost converter can operate in buck mode, buck–boost mode, and boost mode. Fig. 1 illustrates the ratio of inductor current versus load current in three modes. The highest ratio occurs in buck–boost mode; the positive buck–boost converter causes more conduction loss and switching loss because R Manuscript received April 21, 2012; revised August 24, 2012; accepted October 4, 2012. Date of current version February 15, 2013. This work was supported by the National Science Council under Grant 100-2221-E-027-045 and Grant 100-2221-E-027-061. Recommended for publication by Associate Editor Y.-F. Liu. The authors are with the Department of Electronic Engineering, National Taipei University of Technology, Taipei 106, Taiwan (e-mail: jjchen@mail. ntut.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2012.2223718 of its four power transistors. To reduce the loss of switches, as the positive buck–boost converter operates in wide-range supply voltages, it is necessary to avoid power converters operating in buck–boost mode. Therefore, we design a mode-select circuit to detect the battery energy Vbattery and select the operation mode. When the converter operates in buck mode or boost mode, it only switches two power transistors. The mode-select circuit can reduce the conduction loss and switching loss of the proposed converter, and the power efficiency can be improved [11]–[17]. Fig. 2 shows the output voltage versus the decreasing battery voltage. As the battery voltage Vbattery is higher than Vbuck (3.6 V), the converter operates in buck mode; as the battery voltage Vbattery is between Vb o ost (3.1 V) and Vbuck (3.6 V), the converter operates in buck–boost mode; as the battery voltage Vbattery is lower than Vbuck (3.1 V), the converter operates in boost mode. The proposed converter can operate in wide supply voltage range and extend the battery life. Fig. 3(a) shows the proposed converter operating in the charging interval of buck mode; the power transistors Mp1 and Mp2 are turned ON and the power transistors Mn 3 and Mn 4 are turned OFF. Fig. 3(b) shows the proposed converter operating in the discharging interval of buck mode; the power transistors Mp2 and Mn 3 are turned ON and the power transistors Mp1 and Mn 4 are turned OFF. Fig. 4(a) shows the proposed 0885-8993/$31.00 © 2012 IEEE It is composed of four power transistors. the power transistors Mp1 and Mn 4 are turned ON and the power transistors Mp2 and Mn 3 are turned OFF. the digital PWN signal Vp is sent to nonoverlapping circuit and generates four signals.: HIGH-EFFICIENCY POSITIVE BUCK–BOOST CONVERTER WITH MODE-SELECT CIRCUIT AND FEED-FORWARD TECHNIQUES Fig. and buck–boost mode. a compensator network. Fig. and the experimental results are shown in Section III. an analog-adder circuit. Analog-Adder Circuit Fig. (b) Discharging interval of buck–boost mode. Finally. Rc + (Rd //Re ) Rd + (Rc //Re ) (1) . Fig. 4(b) shows the proposed converter operating in the discharging interval of buck–boost mode. the driving circuit drives the power transistors depending on the operation mode. (a) Charging interval. and then generates a output signal Vadd . a mode-select circuit. and a driving circuit. boost mode. the output error signal Vc can be designed at half of the supply voltage VDD so that the compensator can achieve the widest bandwidth. Fig. the output feeds back the voltage Vb to the compensator. When the proposed converter operates. and on the boundary reference voltage Vbuck and Vb o ost . Each circuit is described in the following. Fig. It is composed of an operational amplifier and five resistors. 4. (b) Discharging interval of buck mode. converter operating in the charging interval of buck–boost mode. CIRCUIT DESCRIPTIONS Fig. 3. (a) Charging interval. After that. 6 shows the block diagram of the proposed positive buck– boost converter. 7 shows the analog-adder circuit. Using the analog adder. (a) Charging interval. (b) Discharging interval of boost mode. Finally. The transfer function is shown as  II. generator. 5(a) shows the proposed converter operating in the charging interval of boost mode. the power transistors Mp1 and Mn 4 are turned ON and the power transistors Mp2 and Mn 3 are turned OFF. The analog-adder circuit adds the feed-forward supply voltage VDD and the error signal Vc to generate a signal Vadd . which transient response is fastest. the compensator sends an error signal Vc to the analog-adder circuit. In this paper. Using the analog adder. a dynamic ramp 4241 Va d d = 1+ Rb Ra   (Rd //Re ) (Rc //Re ) Vc + VD D . The operation mode is controlled by the mode-select circuit which sends a control signal to the nonoverlapping circuit. 5. A. which includes buck mode. the circuit description of the proposed is shown in Section II. 5(b) shows the proposed converter operating in the discharging interval of boost mode. and improve the transient response of the whole circuit when the load current changes.CHEN et al. the power transistors Mp1 and Mp2 are turned ON and the power transistors Mn 3 and Mn 4 are turned OFF. Then. the output error signal of the compensator can be designed at half of the supply voltage VDD so that the compensator can achieve the widest bandwidth. Vadd is compared with a dynamic ramp which depends on the supply voltage VDD so that the transient response could be improved while the supply voltage VDD and the load current Iload changed. the conclusion is made in Section IV. Fig. The analog-adder circuit adds the supply voltage VDD to the output error signal Vc of compensator. the power transistors Mp2 and Mn 3 are turned on and the power transistors Mp1 and Mn 4 are turned off. a nonoverlapping circuit. and Mp2 charges the capacitor Ct . the converter operates in buck mode. Mode-Select Circuit Fig. 8. 9. As the supply voltage VDD is lower than the voltage Vb o ost . (a) Dynamic ramp generator. 28. and then. and the output voltage Vm o de1 = 0 and Vm o de2 = 1. and a pulse signal Vclk . When the supply voltage VDD is higher than the voltages Vbuck and Vb o ost . the output voltage Vm o de1 = 0 and Vm o de2 = 0. and the output voltage Vm o de1 = 1 and Vm o de2 = 1. SEPTEMBER 2013 Fig. While the supply voltage VDD is lower than the voltage Vbuck and higher than the voltage Vb o ost . Fig. the converter operates in buck–boost mode. Mp3 and Mp4 are turned OFF. The positive terminal of the operational amplifier is connected to half of the supply voltage VDD . When the supply voltage VDD is decreased. Fig. the modeselect circuit is used to change the operation mode of the proposed converter to reduce the conduction loss and switching loss. Dynamic Ramp Generator Fig. As the battery is discharged. and charges the capacitor Ct with the current I1 . Analog-adder circuit. C. 7. the current decreases with VDD . NO. As the proposed converter operates in buck mode (Vm o de1 = 1 and Vm o de2 = 1). It is composed of an operational amplifier. Fig. 9(a) shows the dynamic ramp generator. 6. VOL. Vbuck . a capacitor Ct . (b) Timing diagram. the dynamic ramp generator creates a ramp signal which is changed with VDD . Owing to the varied supply voltage VDD . and Vb o ost . Mp4 is turned OFF. B. which is composed of two comparator and three reference voltage (VDD . the current Il changes with the supply voltage VDD . the inductor discharges energy. respectively). The drop voltage of Ct raises . Since the duty cycle of the proposed converter has a large variation when the operation mode changes. When the proposed converter operates in buck–boost mode (Vm o de1 = 0 and Vm o de2 = 1). Mode-select circuit. and then. The dynamic ramp circuit is used to improve these problems to reduce spikes and speed up transient responses.4242 IEEE TRANSACTIONS ON POWER ELECTRONICS. 8 shows the mode-select circuit. Block diagram of the proposed positive buck–boost converter. and to extend the battery life so that the efficiency can be increased. a resistor Rt . and Mp2 and Mp3 charge the capacitor Ct . the output voltage Vout causes spikes. 9. Mn 2 ) conduct at the same time. The nonoverlapping timing diagram is shown in Fig. therefore. sistors at the same time. and Vin4 to switch the four power transistors. As Vclk is high. Mn 1 . Mp2 . Finally. which drifts to ground from VDD . the nonoverlapping circuit generates four nonoverlapping control signals Vin1 . As the duty cycle is less than 50%. is sent to the nonoverlapping circuit. Vin2 . Then. the sizes of four power transistors are very large. and the frequency is controlled by a pulse signal Vclk . Nonoverlapping Circuit Fig. Vin3 . (b) Timing diagram. As the proposed converter operates in boost mode. Using this compensation. the supply voltage VDD will be greater than the output voltage Vout . Level Shifter Circuit Fig. 10 shows the compensator network [18]–[20]. if the four power transistors (Mp1 . G. It is necessary to use a level shifter circuit at the gate terminal of Mp2 so that the high level of the duty cycle can be raised. (b) Timing diagram. Compensator Network Fig. Fig. 12. it can avoid turning on the power tran- (a) Level shifter circuit. and Ct is charged. it could cause a large current. the output voltage Vout is higher than the supply voltage VDD . 6. and the drop voltage of Ct decreases. and consume very high power dissipation. linearly. The leadlag compensation is used in this converter. the four power transistors may be broken. the . the high level of the duty cycle will be equal to the output voltage Vout . 4243 (a) Nonoverlapping circuit. the output voltage Vout is limited by the supply voltage VDD . F. the system stability can be improved. When the duty cycle is greater than 50%. which has three functions. are square pulses. it can generate duty cycle signals to control power transistors. In order to decrease the turn-on resistance. Driving Circuit Fig. The transfer function can be described as (1 + sCc2 Rc2 )(1 + sCc1 Rc1 ) Vc   = Vout (sC ) [(R //R ) + R ] 1 + s C c 1 R c 1 (R f 1 //R f 2 ) c2 f1 f2 c1 (R f 1 //R f 2 )+R c 1 (2) where Vout is the output of the proposed converter.CHEN et al. D. Mn 6 conducts. and Vc is the output of the frequency compensator. it can determine the operation mode by a control signal. the gate terminals of those are equivalent to the large capacitances. Mn 6 is turned OFF. which is the output signal of PWM circuit. 11(a) shows the nonoverlapping circuit. 11(b).: HIGH-EFFICIENCY POSITIVE BUCK–BOOST CONVERTER WITH MODE-SELECT CIRCUIT AND FEED-FORWARD TECHNIQUES Fig. Fig. First. Since the Vp . 13 shows the driving circuit [21]. which is generated by Vm o de1 and Vm o de2 . and Vclk . the supply voltage VDD is less than the output voltage Vout . Then. Compensator network. 12(b) shows the waveforms of Vdriver2 and Vin2 . the high level of the duty cycle will be equal to the supply voltage VDD . E. When Vclk is low. Moreover. 10. 11. and causes Mp2 to be turned OFF. Fig. Vram p . as the simultaneous conduction time is too long. As shown in Fig. which are derived from the nonoverlapping circuit. The input signals of those. Fig. 9(b) shows the waveforms of 1/2VDD . 12(a) shows the level shifter circuit. Vref is the reference voltage. 14.3 V.4244 Fig. the proposed converter operates in buck–boost mode. the proposed converter operates in buck–boost mode. and the inductor current is 200 mA.3 V. Fig.3 V. 14. and the duty cycle is equal to 50%. 13. Fig. SEPTEMBER 2013 Driving circuit. NO. 9. 16 shows the experimental results of the proposed converter as the supply voltage VDD is 4.4 V. Fig.74 mm × 2. and the switching frequency is 500 kHz. the output voltage Vout is 3. the output voltage V o u t is 3. IEEE TRANSACTIONS ON POWER ELECTRONICS. the proposed converter operates in buck mode.3 V. 18 shows the experimental results Fig. the output voltage Vout is 3. and the duty cycle is 75%. 28. Experimental results of the proposed converter as the supply voltage V D D is 4. the regulated supply voltage range is from 2. 17. Fig.3 V. III. and the duty cycle is 75%. the proposed converter operates in buck mode. .5 to 5 V. EXPERIMENTAL RESULTS A high-efficiency positive buck–boost converter with modeselect circuit and feed-forward techniques has been fabricated with TSMC 0. Experimental results of the proposed converter as the supply voltage V D D is 3. and the duty cycle is 50%. The output voltage is 3. 17 shows the experimental results of the proposed converter as the supply voltage VDD is 3. and the driving circuit is used to increase the driving ability.35-μm CMOS 2P4M processes.3 V. the output voltage V o u t is 3. the proposed converter operates in buck mode. VOL. and the inductor current is 200 mA. slopes at rising and falling edge are not infinity. The total chip area is 2. Fig. 15.4 V.3 V.3 V. 15 shows the experimental results of the proposed converter as the supply voltage VDD is 4.59 mm. Fig. 16. the output voltage Vout is 3. The chip microphotograph is shown in Fig.4 V.4 V. Fig. Chip microphotograph of the proposed positive buck–boost converter.3 V. Experimental results of the proposed converter as the supply voltage V D D is 4. the proposed converter operates in buck mode. the output voltage V o u t is 3. Fig.3 V. 21 shows the power efficiency of the proposed converter for the output voltage equal to 3. the output voltage Vout is 3. the output voltage Vout is 3.6 V.6% as the load current is 150 mA and supply voltage is 3. the proposed converter operates in boost mode. When the positive buck–boost converter operates in buck– boost mode.7 V. and the inductor current is 140 mA. Power efficiency of the proposed converter for V o u t = 3.3 V. the output voltage V o u t is 3. IV.3 V. By using feed-forward techniques. Experimental results of the proposed converter as the supply voltage V D D is 2. 20. the output voltage V o u t is 3. Experimental results of the proposed converter as the supply voltage V D D is 3.7 V.3 V. The mode-select circuit is used to solve these problems and make the converter operate in buck.3 V. Fig. 20 shows the experimental results of the proposed converter as the supply voltage VDD is 2. 19 shows the experimental results of the proposed converter as the supply voltage VDD is 2. .3 V. buck– boost. CONCLUSION A high-efficiency positive buck–boost converter with modeselect circuit and feed-forward techniques is proposed in this paper.7 V. 19. The performance comparison of the proposed converter with previous works is summarized in Table I. the proposed converter operates in buck–boost mode. of the proposed converter as the supply voltage VDD is 3. The maximum efficiency can be up to 91.: HIGH-EFFICIENCY POSITIVE BUCK–BOOST CONVERTER WITH MODE-SELECT CIRCUIT AND FEED-FORWARD TECHNIQUES Fig.6 V. the output voltage Vout is 3. or boost mode. the proposed converter can achieve faster transient response when the supply voltage changes.3 V. and the duty cycle is 18%. the output voltage V o u t is 3. 18. and the duty cycle is 18%.7 V.5 to 5 V.3 V. 21. Fig. 4245 Fig. the proposed converter operates in boost mode. The maximum efficiency can be up to 91. Experimental results of the proposed converter as the supply voltage V D D is 2.3 V. The proposed positive buck–boost converter can precisely provide an adjustable input with a voltage range from 2. the proposed converter operates in buck–boost mode. and the inductor current is 100 mA. The switching frequency is 500 kHz. the four power transistors cause more conduction loss and switching loss.6% when load current is 150 mA and supply voltage is 3. Fig. and the inductor current is 140 mA.CHEN et al. the proposed converter operates in boost mode. Fig. and the inductor current is 100 mA.3 V. the proposed converter operates in boost mode. 719–730. and D. Power Electron. “A novel buck–boost converter combining KY and buck converters. E. National Taipei University of Technology. Wang.” IEEE Trans. 19.” in Proc.-H. K.. 5. [9] C. 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His main research interests include mixed-signal integrated circuits for power management. he became the Technical Program Committee member of Very Large Scale Integration Design/CAD Symposium. In 2003. Taipei.CHEN et al. He received the B.S. Taipei. Taiwan. he was a Lecturer in the Department of Electrical Engineering. Taiwan. He received the Ph. power electronic integrated circuits. in 2011. degree in electrical engineering from the National Taipei University of Technology. From 1996 to 2003. degree from the Department of Electrical Engineering. National Taiwan University. Taiwan. he joined the Department of Electronic Engineering and Graduate Institute of Computer and Communication Engineering. National Taipei University of Technology. Taichung. His current research interests include analog integrated circuits. degree in electrical engineering from National Chin-Yi University of Technology. During 1991–1996. Hwa-Hsia Institute of Technology.: HIGH-EFFICIENCY POSITIVE BUCK–BOOST CONVERTER WITH MODE-SELECT CIRCUIT AND FEED-FORWARD TECHNIQUES Pin-Nan Shen was born in Yilan. and current-mode analog signal processing. Hwang is the reviewer of more than ten IEEE and Science Citation Index journals. he was an Associate Professor in the Department of Electrical Engineering. mixed-signal integrated circuits. in 2009. 4247 Yuh-Shyan Hwang (M’04) was born in Taipei. in 1966. . Taipei.S. he joined the Editorial Board of the Journal of Active and Passive Electronic Components. and the M.D. in 1996. In 2010. In 2010. Dr. Taiwan. in 1987. where he is currently a Full Professor. Lee-Ming Institute of Technology.