8086 and Memory Interfacing

8086 and Memory InterfacingBore Gowda S B ECE Department Manipal Institute of Technology Manipal-576104 Memory organization In the design of all computers. Memory Capacity The number of bits/bytes that a semiconductor memory chip can store is called its chip capacity . or memory map. In an 8086 the high addresses in the memory map should always be occupied by a ROM. The size of the address space depends on the number of address lines of the microprocessor. while the low addresses in the memory map should always be occupied by a RAM. semiconductor memories are used as primary storage for data and code They are connected directly to the CPU and they are the memory the CPU asks for information (code or data) Among the most widely used are RAM and ROM The physical address space. of a microprocessor refers to the range of addresses of memory location that can accessed by the microprocessor. At least two memory devices are required in a microprocessor system: one for the ROM and one for the RAM. to select a specific location The number of address pins on a memory chip specifies the number of memory locations. then Number of memory location = 2n . inside the memory chip. Data.Memory organization A memory device or memory chip must have three types of lines or connections: Address. Enable and Control. If ‘n’ specifies the number of address lines. Address Lines: The input lines that select a memory location within the memory device. Decoders are used. The number of data pins is related to the size of the memory location . For example. an 8-bit wide (byte-wide) memory device has 8 data pins The number of data lines (m-bits) determines the size of each location in the memory.Memory organization Data Lines: The data pins are typically bi-directional in read-write memories. Memory Capacity = 2n x m . Control Lines: RAM chips have two control input signals that specify the type of memory operation: the Read (𝑹𝑫) and the Write (𝑾𝑹) signals. or written into it. used to select or enable the memory device. thus there is no need for a Write (𝑾𝑹) signal.Memory organization Enable Lines: All memory devices have at least one Chip Select (𝑪𝑺) or Chip Enable (𝑪𝑬) input. − If a device is not selected or enabled then no data can be read from. − Some RAM chips have a common Read/ Write (R/𝑾) signal. − The 𝑪𝑺 or 𝑪𝑬 input is usually controlled by the microprocessor through the higher address lines via an address decoding circuit. ROM chips can perform only memory read operations. . − In most real ROM devices the Read signal is called the Output Enable (𝑶𝑬) signal. An 𝑪𝑺 Read/Write R/𝑾 Chip select n-address lines A0 .Dm RAM Memory Chip RAM Memory Chip .An Write Read 𝑪𝑺 𝑾𝑹 𝑹𝑫 2n words m-bits per word 2n words m-bits per word m-data lines D0 .Memory organization Chip select n-address lines A0 .Dm m-data lines D0 . Memory organization Chip select n-address lines A0 .An 𝑪𝑺 Read 𝑹𝑫 2n words m-bits per word m-data lines D0 .Dm ROM Memory Chip . and A0 are used for generating the chip select signal for ODD and EVEN bank using decoding circuits . 2.Memory Interfacing If the microprocessor has ‘n’ address lines. The upper 8-bit bank is called ODD Address memory bank and the lower 8-bit bank is called EVEN Address bank. If only P memory locations are to be interfaced. 𝐵𝐻𝐸. 3. then it is possible to address 2n =N memory locations. Connect address lines of memory chips with those of the microprocessor and also connect the memory 𝑅𝐷 and 𝑊𝑅 inputs to the corresponding to the processor control signal. then least significant p address lines out of n lines are required The remaining (n-p) higher order address lines may be used to generate chip select signal using decoding circuit Procedure for interfacing memory with 8086 1. The remaining address lines of the microprocessor. Arrange the available memory chips so as to obtain 16-bit data bus width. and the chip is selected only for the specified logic levels on these high order address lines. All the address are not used by the memory devices to select particular memory locations. The unused lines are used to decode to generate chip select signals. Linear or Partial decoding Full Decoding – All of the higher address lines are decoded to select memory chip.Memory Decoding In general. – Each memory location has unique address – Disadvantages: it needs more hardware for decoding . two techniques are used to decode the address 1. Absolute or Full decoding 2. Basically. all the memory locations are not implemented. 4. 2. basically used in small systems Individual high order address lines are used to decode the chip select for the memory chips using less hardware Disadvantages: Each memory location has more than one address called roll-over addresses (fold back or shading). PAL. GAL) Comparators . Decoding circuits 1. NAND gates Decoders Programmable Logic Devices(PLAs.Memory Decoding Partial Decoding All the address lines are not used to generate chip select. 3. The address of RAM may be selected anywhere in the 1MB address space. Select suitable address maps Note: 1. To address 8K=23 x 210 = 213 . 2. The address of EPROM/ROM may be selected such that the address FFFF0H must lie in this space. the processor needs 13 address lines So address lines A0 – A12 used to address 8K locations A13 – A19 are used to generate chip select signal Address Map/ Address decoding Table CHIPS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS EPROM 1 (O and E) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 FFFFFH FE000H To decoder To 4K Memory IC .Interface two 4Kx8 EPROM (8Kx8) chips to 8086.