80386 Microprocessor

80386 microprocessorSalient features 1. 2. 3. 4. 5. Flexible 32 bit microprocessor Address bus is of 32-bit Operating frequency of 20-33 MHz . Contains total 132 Pins. Intel’s first practical microprocessor to contain a 32-bit data bus and 32-bit memory address. 6. 16 byte prefetch queue 7. Very large address space a. 4 Gb of physical memory supported b. 64 Tb of virtual memory supported c. 4 Gb of maximum segment size 8. Integrated memory management unit 9. Object code compatible with all 8086 family microprocessors 10. High speed numeric support via 80387 11. Can operates in real, protected & virtual Mode 12. Introduced paging, virtual memory concept 13. Can operate at 11.4 MIPS. 2 14. Contains near about 2,75,000 Transistors. BY UBAID SAUDAGAR 09-10-2012 Versions of 80386 Microprocessor (A) 80386 SX (1). A.B. is of 32 Bit. (2). D.B. is of 32 Bit. (3). Total 132 Pins. (4). Can address upto 4GB of memory. BY UBAID SAUDAGAR 3 (B) 80386 DX (1). A.B. is of 24 Bit. (2). D.B. is of 16 Bit. (3). Total 100 Pins. (4). Can address upto 16MB of memory. 09-10-2012 Pin configuration BY UBAID SAUDAGAR 4 09-10-2012 . BY UBAID SAUDAGAR 5 09-10-2012 .Pin configuration cont. BY UBAID SAUDAGAR 6 09-10-2012 . 30 address lines are required i.  Address bus(A31 –A2. therefore memory is connected in 4 banks(bank 0 – bank 3).e. it is able to address 4GB of physical memory space from 00000000H to FFFFFFFFH. So the 80386 can transfer 8/16/32 bit data in one machine cycle. 4GB is connected as 4 banks of 1GB each. BE3 – BE0): With the help of address lines. Therefore to address 1GB of memory.Pin configuration cont.  Data bus(D31 – D0): It consist of 32 data pins. from A2-A31. BY UBAID SAUDAGAR Lower two address pins A1 and A0 are internally decoded by 80386 to generate 4 bank enable signals(BE3 – BE0) BE0 applies to D7 to D0 BE1 applies to D15 to D8 BE2 applies to D23 to D16 BE3 applies to D31 to D24 When any one of the BE pin goes low.Pin configuration cont. data bytes are transferred to or from the microprocessor from the corresponding data lines When all are low then complete 32 bit data is transferred between microprocessor and memory in one machine cycle 7 09-10-2012 . If bus size is of 16 bits then 32 bit data will be transferred in two machine cycles.  READY: If the ready input is 0. then µp performs normal operation or normal machine cycle without any wait state. BY UBAID SAUDAGAR 8 09-10-2012 . It is used along with slow devices.  BS16(bus size 16): If logic 0/1 is applied on BS16 pin. then it indicates the size of the external data bus is of 16 bits/32 bits respectively. so the µp has to use 16/32 data pins correspondingly. If the ready i/p is 1.then the µp will introduce wait state in machine cycle.Pin configuration cont. Pin configuration cont. Whenever the 80387 has to perform data transfer then it will give logic 1 on PEREQ pin of the 80386. The physical address of memory location is generated by 80386. This address and read/write control signals is transferred by 80386.  PEREQ(Processor extension request): If the coprocessor is connected in the system. BY UBAID SAUDAGAR 9 09-10-2012 . then the data transfer between the coprocessor and memory is performed by the main processor 80386. but the data transfer is performed between coprocessor and memory. then the µp will remain in the wait state. then the µp will check the BUSY pin. then the µp will exit from the wait state and will execute next instruction in sequence.Pin configuration cont. When the BUSY input becomes 1. If the BUSY input is 0.10 BY UBAID SAUDAGAR 09-10-2012 .  BUSY: If the instruction wait is given to the microprocessor. The ISR of the INT16 is used to check the error flags of the coprocessor and display the message on the screen. the coprocessor will give logic 0 on the ERROR pin of the µp. So the µp is interrupted on dedicated interrupt INT16.  ERROR: When the coprocessor performs any operation and if error is obtained in the result. Pin configuration cont.  HOLD AND HLDA: HOLD pin indicates that another bus master is requesting a local bus. It acknowledges it by making HLDA high. These two are generally used by DMA controller. It takes the charge over the system bus for DMA operation. HOLD signal is activated to inform the µp that it want’s the charge of the bus. When the µp receives the HOLD request it will issue HLDA as an acknowledgement. When the HOLD line becomes low, HLDA also becomes low and µp gets back the control over the system bus BY UBAID SAUDAGAR 11 09-10-2012 BY UBAID SAUDAGAR 12 09-10-2012 Pin configuration cont.  W/R(write/read): When the µp writes the data into the memory or o/p device then it gives W/R = 1. When the µp reads data from memory or i/p device, then it gives W/R = 0.  D/C(data / control): When data transfer operation is performed between µp and memory, or µp and the io device µp makes this signal go high. When the µp performs control operations like opcode fetch, giving INTA signal then µp makes this signal go low. BY UBAID SAUDAGAR 13 09-10-2012 Pin configuration cont. When the data transfer takes place between µp and io device then µp gives a low signal on this pin.  M/IO(memory/input-output): When the data transfer is performed between µp and memory then the µp gives high signal on this pin. BY UBAID SAUDAGAR 14 09-10-2012 . The o/p of this pin is applied to ic8289.Pin configuration cont. BY UBAID SAUDAGAR 15 09-10-2012 . when it is low it prevents other processors from gaining access the system bus. which informs other processors that the system bus is going to remain LOCK with 80386.  LOCK: it is a prefix. This signal is activated by the LOCK instruction and remains active till this instruction is carried out. then the µp has to transfer the address of the next machine cycle.  ADS(address data strobe): µp has to transfer valid memory or i/o address on address pins. then to latch this address in the external latch. µp gives logic 0 on ADS pin. BY UBAID SAUDAGAR 09-10-2012 .Pin configuration cont.  NA(next address): When the bus controller gives logic 0 on the NA pin. even if the current machine cycle is not completed. This is called as address pipelining and it increases the speed of 16 operation. Memory System of 80386DX BY UBAID SAUDAGAR 17 09-10-2012 . Architecture of 80386 BY UBAID SAUDAGAR 18 09-10-2012 . Architecture of 80386  The 80386DX µp is available in a 132 pin array.e.  It can operate in 16/20/25/33/ MHz frequencies  If operating frequency is 33 MHz.  The internal block diagram Is divided into six units BY UBAID SAUDAGAR 19 09-10-2012 . 66 MHz's. then we have to apply double frequency i. then address and control signals are transferred by BIU of 80386.Bus interface unit  It is used to transfer 32 bit address.  BIU also performs address pipelining. data and control signals on system bus.  In other words to interface with outside world BIU is used. but can be used in systems as 16/32 bit.  This information is indicated on BS16 pin. BY UBAID SAUDAGAR 20 09-10-2012 .  The µp consist of 32 data pins. that is the address of next machine cycle is transferred on the address pins even if the current machine cycle is not completed.  If data transfer takes place between memory and co – processor. 8 bit registers.Code prefetch unit  This unit will prefetch the instruction code and it is stored in the instruction queue which consists of 16. BY UBAID SAUDAGAR 21 09-10-2012 . Decode unit  Prefetch unit will transfer instruction code to decode unit.  This decode unit will pre decode 3 bytes of instruction codes and it is stored in the decoded instruction queue. BY UBAID SAUDAGAR 22 09-10-2012 .  So time required to execute rotate/shift/multiplication/division is reduced. BY UBAID SAUDAGAR 23 09-10-2012 . ALU and barrel shifter. logical. data transfer operations.  The barrel shifter can be used to shift data by multiple bits in one clock cycle.Execution unit  It will execute decoded instruction to perform different arithmetic.  It consist of different registers. flags.  This information is transferred by µp to the segment invisible cache register. i. base address.  In real mode segment registers are used to store the base address of memory. BY UBAID SAUDAGAR 24 09-10-2012 . limits and access rights.e.  In protected mode segment registers are used to point the descriptors which contains information about memory.Segment unit  It consists of segment registers and segment invisible cache register. then 32 bit linear address is transferred as 32 bit physical address. then the 32 bit linear address generated in protected mode is translated using 2 level paging into 32 bit physical address.Paging unit  If the paging unit is enabled. BY UBAID SAUDAGAR 25 09-10-2012 .  If paging unit is disabled. Debug register 7. General purpose registers 2. System address registers 5. Segment registers 4. Instruction pointer and flags 3. Test register BY UBAID SAUDAGAR 26 09-10-2012 . Control register 6.Register organization of 80386  80386 registers are categorized as follows: 1. General purpose registers BY UBAID SAUDAGAR 27 09-10-2012 . similarly BX is EBX etc.  Example : A 32 bit register corresponding to AX is EAX.CL.CH.bit register known as an extended register. DX.BL.DL can also be accessed separately hence 28 providing more flexibility. BP and SP. CX. BX. DI.DH.e.  The lower and the higher bytes of general purpose registers i. is represented by the register name with prefix E.AL.  A 32 .General purpose registers  The 8 general purpose registers of 32 bit hold data or address. SI.  The least significant 16 bits of the registers can be accessed separately.BH.  This is done by using the names AX. The upper 16 bits are neither used nor changed. AH. BY UBAID SAUDAGAR 09-10-2012 . Segment registers BY UBAID SAUDAGAR 29 09-10-2012 . GS.Segment Registers  Six segment registers hold the base address(in real mode) or segment selector values(in protected mode).FS and DS all are generally used as data segments BY UBAID SAUDAGAR 30 09-10-2012 .  The ES. Instruction pointer and flag register BY UBAID SAUDAGAR 31 09-10-2012 . Instruction pointer  The instruction pointer is a 32 bit register named EIP  It holds the offset of the next instruction which is to be executed  The offset is always relative to the base address of Code segment(CS)  The lower 16 bits are called as IP BY UBAID SAUDAGAR 32 09-10-2012 . Flag register BY UBAID SAUDAGAR 33 09-10-2012 . Carry flag BY UBAID SAUDAGAR 34 09-10-2012 . Auxiliary carry flag BY UBAID SAUDAGAR 35 09-10-2012 . Parity flag BY UBAID SAUDAGAR 36 09-10-2012 . Zero flag BY UBAID SAUDAGAR 37 09-10-2012 . Sign Flag BY UBAID SAUDAGAR 38 09-10-2012 . Overflow flag  Bit 11  During the addition of two numbers. goes out of range.e. BY UBAID SAUDAGAR 39 09-10-2012 . overflow flag is set. if their result exceeds the limit i. Interrupt flag BY UBAID SAUDAGAR 40 09-10-2012 . Trap Flag BY UBAID SAUDAGAR 41 09-10-2012 . Direction flag BY UBAID SAUDAGAR 42 09-10-2012 . I/O privilege level BY UBAID SAUDAGAR 43 09-10-2012 . Nested task BY UBAID SAUDAGAR 44 09-10-2012 . Virtual 8086 mode  Bit 17  This bit provides virtual 8086 mode within protected mode. the 80386 will switch to 8086 operations.  When this bit is set while 80386 is in protected mode. It can be set only in the protected mode BY UBAID SAUDAGAR 45 09-10-2012 . it causes any debug fault to be ignored on the next instruction.Resume flag  Bit 16  When RF is set. BY UBAID SAUDAGAR 46 09-10-2012 .  It is then automatically cleared on successful completion of every instruction (no fault is signaled). the RPL bits indicates the requested privilege level. 48 shows that the segment register is used as selector in protected mode.  RPL = 00 (highest)  RPL = 11 (lowest) BY UBAID SAUDAGAR 47 09-10-2012 .Use of segment registers in protected mode  The figure on pg.  The leftmost 13 bit index is a descriptor number  The TI bit selects either local (TI = 1) or global (TI = 0) descriptor table.  Whenever the new selector number is loaded into one of the segment registers. the 80386 µp accesses one of the descriptor tables and automatically loads the descriptor into the segment invisible cache register. Use of segment registers in protected mode BY UBAID SAUDAGAR 48 09-10-2012 . BY UBAID SAUDAGAR 49 09-10-2012 . In real mode the 80386 appears to programmers as a fast 8086.Addressing modes of 80386 REAL MODE: Real-address mode (often called just "real mode") is the mode of the processor immediately after RESET. In this mode all instructions and features OF 80386 are available for utilization. BY UBAID SAUDAGAR 50 09-10-2012 .Addressing modes of 80386 PROTECTED MODE: Protected mode is the natural 32-bit environment of the 80386 processor. The CPU enters V86 mode from protected mode to execute an 8086 program. BY UBAID SAUDAGAR 51 09-10-2012 .Addressing modes of 80386 VIRTUAL MODE: Virtual 8086 mode (also called V86 mode) is a dynamic mode in the sense that the processor can switch repeatedly and rapidly between V86 mode and protected mode. then leaves V86 mode and enters protected mode to continue executing a native 80386 program. memory larger than 1 MB can be accessed.PROTECTED MODE         In the protected-mode. segments can be of variable size. In protected mode. Note: Each descriptor corresponds to a segment with a maximum size of 4 GB or 232 bytes In addition. and access rights. In protected mode the segment register is used as selector that selects a descriptor from a descriptor table. the base : offset logical memory addressing scheme (which is used in real mode) is changed. The descriptor describes the memory segment's location. Each descriptor is 8 bytes long 52 09-10-2012 BY UBAID SAUDAGAR . length. The selector. selects one of 8192 descriptors from one of two tables of descriptors (stored in memory): the global and local descriptor tables. PROTECTED MODE  The 8192 descriptor table requires 8 * 8192 = 64K bytes of memory. BY UBAID SAUDAGAR 53 09-10-2012 . However.. Since this field is 20 bits.e. if the G bit (granularity bit) is set. the segment size varies upto 1M bytes. In this case.PROTECTED MODE  The main parts of a descriptor are: Base (B31 – B0): indicates the starting location (base address) of the memory segment. Limit (L19 – L0): This defines the segment size. the value of the limit is multiplied by 4K bytes (i. BY UBAID SAUDAGAR 54 09-10-2012 . the segment size could be anywhere between 4K and 4G bytes. appended with FFFH). End = Base + Limit = 10000000h + 001FFh = 100001FFh Segment Size = 512 bytes Base = Start = 1000 0000h Limit = 001FFh and G = 1 So. Base = Start = 1000 0000h FFF = 1111 1111 1111 Limit = 001FFh and G = 0 appended at the end So. End = Base + Limit * 4K = 10000000h + 001FF FFFh = 101FFFFFh Segment Size = 2M bytes BY UBAID SAUDAGAR 55 09-10-2012 .PROTECTED MODE  Example. Granular bit is 0 Since the descriptor contains limit of 20 bits with which the maximum size is 1 Mbyte 1 Descriptor 1 Mbyte 1 Mbyte Offset address is 32 bits which varies from 000 00000 000 FFFFF Question arises why blocks of 1 Mbyte? This is the base address which is varying BY UBAID SAUDAGAR 000 00000 001 00000 002 00000 FFF 00000 With the help of base address different blocks are selected 1 Mbyte 1 Mbyte 1 Mbyte 4 Gb memory associated with 56descriptor each Limit is multiplied by 4k.therefore now offset address which was varying as: Now is multiplied by 4k i. 4k x 1 Mb = 4 Gb Now offset varies from 0000 0000 09-10-2012 FFFF FFFF Total 4k blocks of 1 Mbyte associated with 1 descriptor .e. This means that the instructions use 16-bit offset addresses and 16-bit registers by default. the instructions are 16-bit instructions. If D = 1. the instructions are 32-bits by default.  D bit: If D = 0.  Access rights byte: allows complete control over the segment by defining the privilege level and other information about the segment. compatible with the 808680286 microprocessors.PROTECTED MODE  AV bit: is used by some operating systems to indicate that the segment is available (AV = 1) or not available (AV = 0). BY UBAID SAUDAGAR 57 09-10-2012 .  The descriptor contains base address of the segment and the limit (which defines the maximum size of segment).  Base address is of 32 bits and limit is of 20 bits (therefore the maximum size of the segment is 1Mbyte)  Now the linear address is formed by adding the 32 bit offset with 32 bit base address to get 32 bit linear address. BY UBAID SAUDAGAR 58 09-10-2012 .Address calculation in protected mode  In protected mode the address is formed in such a way that the selector (16 bit segment register) selects one of the many descriptors from the descriptor table. limit and access rights 16 bit selector 32 bit offset 0 1 2 Selects one of the many descriptors 3 .Descriptor contains base address. . 8191 BY UBAID SAUDAGAR 0H 8H 10h 18h 32 bit base address + fff8h 59 32 bit linear address Global or Local descriptor table = Physical address. since paging is not enabled 09-10-2012 . . Due to which the offset gets added to base address but the upper 12 bits of offset are all 0’s. BY UBAID SAUDAGAR 60 09-10-2012 . But limit size is 20 bits and which indicates that maximum segment size is of 1 Mbyte.Address calculation in protected mode     Offset is of 32 bits therefore the maximum size of the segment possible is 4 Gb. In above case we notice that the granular bit in the descriptor is 0. which are required currently for the execution need to available in the physical memory. Only a few pages of the segments. Whenever the other pages of the task are required for execution.Paging mechanism  The segmentation scheme may divide the physical memory into variable size segments but the paging divides the memory into fixed size pages. The previous pages which are executed need not be available in the memory. BY UBAID SAUDAGAR 61 09-10-2012 .  Thus the memory requirement of the task is reduced. therefore remaining memory is used for other tasks. they may be fetched from the secondary storage.  The advantage of the paging scheme is that the complete segment of a task need not be in the physical memory at any time. Program B requests 3 pages of memory.  Example: Show memory page allocation for the following sequence: Program A requests 3 pages of memory.Paging Mechanism  A key advantage to memory paging is that memory allocated to a program does not have to be contiguous. plus an additional page after program D. Program C terminates. and because of that. Program D requests 2 pages of memory. Program C requests 2 pages of memory. there is very little internal fragmentation. leaving 2 empty pages. and it is allocated the 2 empty pages that program C left. BY UBAID SAUDAGAR 62 09-10-2012 . Paging Mechanism BY UBAID SAUDAGAR 63 09-10-2012 . BY UBAID SAUDAGAR 64 09-10-2012 .Address calculation when paging is enabled  The 32-bit linear address generated by the segmentation unit can be optionally fed into the paging unit to undergo a second address manipulation process. Descriptor contains base address. . 8191 BY Ubaid by UBAID Saudagar SAUDAGAR 0H 8H 10h 18h 32 bit base address + 32 bit linear address fff8h 65 Global or Local descriptor table Goes to paging unit 09-10-2012 . . limit and access rights 16 bit selector 32 bit offset 0 1 2 Selects one of the many descriptors 3 .  But in case of paging this linear address is applied to paging unit and then physical address is formed which accesses the pages.  Lets see how physical address is formed on pg.  This is actually the physical address in case of segmentation which is used to access the segments. the linear address is formed by combining the base address and the offset address.Address calculation when paging is enabled  In the above figure we notice that. 67 BY UBAID SAUDAGAR 66 09-10-2012 . (Upper 10 bits) Offset within page directory (next 10 bits) offset within page tables Page tables of 4 Kb each 4 bytes 4 bytes 4 bytes (12 bits) offset within pages Linear address + Page directory of 4 Kb 4 bytes 4 bytes + 4 bytes Base address Pages Base address + 4 kb 4 kb Total number of pages = 1024 * 1024 .1048576 = 1M = - 1024 entries. each entry is base address of page Each table table has 1024 entries. each BY gives UBAID SAUDAGAR entry points CR3 the base address to a page - 4 bytes 4 bytes 4 bytes 67 1024 page tables 4 kb Offset address varies within a page = 0000 0000 0000 = 000 1 1 1 1 1 1 1 1 1 1 1 1 = FFF09-10-2012 . Virtual address 801C3400H 10 0000 0000 (200H) 01 1100 0011 (1C3H) 0100 0000 0000 (400H) 200h This physical address is used to access a page 000E4000h 00028000h + Physical address = 00028400h Base address BY UBAID SAUDAGAR 68 09-10-2012 .  The next 10 bits of the linear address serve as an index into the corresponding page table. BY UBAID SAUDAGAR 69 09-10-2012 .  By adding the page table entry value that is actually the base address to the page and the offset which comes from the last 12 bits of linear address we can locate the requested physical address and send it to its address bus and access a page.Address calculation when paging is enabled  A close examination of the paging process reveals that the processor breaks the linear address into three components before turning it into a physical one.  The top 10 bits of the linear address are used by the processor to index or point the page directory table. With the help of base address page directory is selected and with the help of offset the entries in the page directory is selected.  Imp: The total entries in the page directory are 1024.  The upper 10 bits are used to select the entries in the page directory.Address calculation when paging is enabled  The linear address obtained by combining the base address (obtained from descriptor) and offset address is split up into three parts by the MMU.  Page directory : The page directory contains 1024 page directory entries. Therefore to access these entries we require 10 addressing bits which we get from the upper 10 bits of linear address. each of which is 4 bytes (32 bits). This means the page directory is 4 K bytes long. BY UBAID SAUDAGAR 70 09-10-2012 . There is only one page directory in memory and its base address is contained in CR3. But.Address calculation when paging is enabled  Therefore the 10 bits(offset) will vary as: 00 0000 0000 = 000 (hex) = 0 1 1 1 1 1 1 1 1 1 1 = 3FF (hex) = 1023 (decimal) Now each address will select an entry in the page directory table. each entry is of 4 bytes therefore total number no. therefore to address 4096 locations 12 bits are required hence the MMU appends two bits at the end and their value are always 00 Now the offset will vary as: 0000 0000 00 00 = 000 (hex) = 0th location 0000 0000 01 00 = 004 (hex) = 4th location 0000 0000 10 00 = 008 (hex) = 8th location First 10 bits 1 1 1 1 1 1 1 1 1 1 00 = FFC (hex) = 1024th location BY UBAID SAUDAGAR 71 09-10-2012 . of memory locations are: 1024 * 4 = 4096. Address calculation when paging is enabled  The next 10 bits are used to select the entries within the page tables. This means that each page table is 4 K bytes long. BY UBAID SAUDAGAR 72 09-10-2012 .e. Each page table entry is actually the base address to a page in the page frame. same as page directory.  Page table: Page directory has 1024 entries and each entry selects a page table. As such there are 1024 page tables and each table of 4Kb. Therefore number of pages accessed or addressed are 1024 (1 page table entries) * 1024 (number of page tables) = 1048576 = 1 Mb pages. Note: The number of bits available as offset to move within the page table are 10 i. Each page table contains 1024 page table entries. each of which is 4 bytes (32 bits). hence addressing is same as explained previously. BY UBAID SAUDAGAR 73 09-10-2012 . 10bits are used to address entries in the page table (even though PT requires 4Kb of memory). It is important to notice that 10 bits are used to address entries in the page directory(even though PD requires 4Kb of memory). This is because MMU appends 00 at the end of 10 bits hence it moves within a PD and PT and addresses 4kb of memory and only the entries which are 1024 for which only 10 bits are required. 12 bits are required as offset to move within a page (even though page size is of 4Kb).Address calculation when paging is enabled  The next 12 bits are used as offset to move within the pages of 4Kb. e. the physical page number).. 1M pages * 4K (size of each page) = 4Gb space = size of page frame BY UBAID SAUDAGAR 74 09-10-2012 .Address calculation when paging is enabled Page: Each page table entry points to the starting physical address of a page in memory (i. Number of pages accessed or addressed are 1024 (1 page table entries) * 1024 (number of page tables) = 1048576 = 1 Mb pages. In other words each entry in the page table acts as base address to a page and the 12 bits from the linear address acts as offset address. The MMU performs the task of converting linear addresses. into physical addresses that access a physical memory location located anywhere within the memory system.Note: The memory-management unit (MMU) within the 80386 is similar to the MMU inside the 80286. as they appear as outputs from a program. BY UBAID SAUDAGAR 75 09-10-2012 . except that the 80386 contains a paging unit not found in the 80286. Whenever a linear address is to be converted to physical address. it is first checked to see. it would be very inefficient to have to access them every time an address requires translation since two memory reads are needed to read the entries from each table.Translation look aside buffer A translation look aside buffer (TLB) is a cache that memory management hardware uses to improve virtual address translation speed. To improve performance. This page table cache is called as translation look-aside buffer (TLB) that automatically translate the upper 20 bits of the virtual address into upper 20 physical address bits. This requires n number of clock cycles. Since the page directory and page tables are of 4kb. whether it corresponds to any of the page table cache entries. a 32-entry page table cache is provided which stores the 32 recently accessed page table entries. BY UBAID SAUDAGAR 76 09-10-2012 . Translation look aside buffer 10 bits 10bits 12 bits (offset) 20 bits Valid virtual upper 20 bits physical upper 20 bits 0 0 0 1 0 0 0 BY UBAID SAUDAGAR TLB + Physical address 0 77 09-10-2012 Translation look aside buffer  Whenever a linear address is formed, it gets converted to physical address through 2 level paging (i.e. PD and PT). The resent addresses (linear and physical) are stored in the TLB.  Thus from the above figure we see that the Translation look aside buffer (TLB) contains upper 20 bits of virtual address (linear address) as well as upper 20 bits of physical address. Whenever any page is to be accessed, this linear address needs to be converted again and again to physical address through 2 level paging.  To avoid this and to access the most resent pages or to access some pages again and again quickly we use TLB.  The linear address (virtual address) is stored in TLB along with its corresponding physical address, if the required linear address is available then it’s corresponding physical address is retrieved and combined with the offset to access the page. This happens in a single clock cycle. BY UBAID SAUDAGAR 78 09-10-2012 Control Registers  Figure below shows the format of the 80386 control registers CR0, CR2, and CR3.  CR0 contains system control flags, which control or indicate conditions that apply to the system as a whole, not to an individual task. BY UBAID SAUDAGAR 79 09-10-2012 Control registers 16 MSB P G 16 LSB 0---------------------------------------------------------------------------0 0-------------------------------------------------------------------------0 E T E M P T S M P E CR0 INTEL RESERVED PAGE FAULT LINEAR ADDRESS CR1 CR2 PAGE DIRECTORY BASE ADDRESS 0000 0000 0000 CR3 BY UBAID SAUDAGAR 80 09-10-2012 . The defined CR0 bits are described below: BY UBAID SAUDAGAR 81 09-10-2012 .Control Registers Control Register (CR0): Machine Control Register As shown in figure. The low order 16 bits of CR0 are also known as machine status word(MSW). control register CR0 contains six defined bits for control and status purposes. for compatibility with 80286 protected mode. ET (Extension Coprocessor. The ET bit of CR0 indicates which type of coprocessor is present.bit4): If 0/1. the 80386 uses the 16-bit protocol of the 80287.Cont. then it indicates that the microprocessor 80386 is connected with the co-processor 80287/80387. bit 31): If paging bit is 1/0. PG (Paging. then paging is enabled/disabled from the on-chip paging unit. BY UBAID SAUDAGAR 82 09-10-2012 . if reset. The 80386 is designed to operate with either an 80287 or 80387 math coprocessor. the 80386 uses the 32-bit protocol of the 80387. ET is set automatically by the 80386 after RESET If ET is set. then it allows the co processor opcodes to be actually executed on an actually 80387DX co processor (this is the default case after reset). If TS = 0. If TS = 1. If EM = 0. bit 2): If EM = 1. bit 3): TS is automatically set whenever a task switch operation is performed.Cont.e. i. then µp will not performing task switching. then the µp will execute more than one program. TS(Task switch. EM (Emulate Co-processor. BY UBAID SAUDAGAR 83 09-10-2012 . not going to another program without executing first program. then whenever Coprocessor instructions comes in the program then µp executes INT7 (exception 7). It will take nearly 100 times more time compared to the time required by the co processor. The ISR of INT7 is used to execute the operation of the co processor instructions using software. e.processor). then it indicates that co processor is present/not present respectively. then 80386 again operates in real mode. when MP = 1. then there is no use of EM. i. MP (Monitor Processor extension (co . PE (Protection enable. BY UBAID SAUDAGAR 84 09-10-2012 . bit 0): If PE = 1.Cont. then the 80386 gets defined from real mode to protected mode. then there is no meaning of the EM bit. If PE = 0. bit 1 ): If MP = 1/0. When the co processor is connected to 80386. INT14) to display the error message. Control register (CR1) : Intel Reserved It is reserved by Intel for used in future microprocessor IC’s Control register (CR2) : Page fault linear address If the paging unit is enabled. then 32 bit linear address is saved in register CR2 and the µp executes exception (dedicated interrupt. BY UBAID SAUDAGAR 85 09-10-2012 . but if there is any fault in paging unit.Cont. Control Register (CR3): Page directory base address A directory table points to the page table and page table points to page frame. Directory table is pointed by CR3 (i. the base address or starting address or root address of directory table is present in CR3) Note that this address locates the page directory at any 4K boundary in the memory system because it is appended internally with 000h. BY UBAID SAUDAGAR 86 09-10-2012 .Cont.e. the IR is unused by the programmer.Invisible register  Every memory segment is associated with a descriptor.e. i. the next memory segment.e. i.  When other memory segment is to be selected. BY UBAID SAUDAGAR 87 09-10-2012 . the base address of previous one is automatically stored in invisible register (IR).  The invisible register is operated by the microprocessor. System address registers  GDTR = Global Descriptor Table Register  LDTR = Local Descriptor Table Register  TR = Task Register BY UBAID SAUDAGAR 88 09-10-2012 . size of GDT is 64kb Physical memory Descriptor 8191 Descriptor 8190 Descriptor 8189 - Length of the GDT 47 Base address 16 15 Limit 0 BA Descriptor 1 Descriptor 0 80386 microprocessor BY UBAID SAUDAGAR 89 09-10-2012 .GDTR GDTR Since limit has 16 bits. GDTR  GDT consist of descriptors which are available to almost all the task in the system  The contents of the global descriptor table register define a table in the 80386DX's physical memory address space called the Global Descriptor Table (GDT).536 bytes long. The lower two bytes of this register. which are identified as LIMIT. This 32-bit base address allows the table to be positioned anywhere in the 80386DX's address space BY UBAID SAUDAGAR 90 09-10-2012 . which are labelled BASE. the GDT can be up to 65. specify the size in byte of the GDT. The upper four bytes of the GDTR.  GDTR is a 48-bit register that is located inside the 80386DX. locate the beginning of the GDT in physical memory. Since LIMIT has 16 bits. n 0 LDTR invisible or cache register 47 Base address 16 15 Limit 0 Descriptor 8191 Descriptor 1 Base address BY UBAID SAUDAGAR 91 LDT Descriptor 0 09-10-2012 .LDTR Physical memory Descriptor 8191 Descriptor n Descriptor 0 GDT 15 LDTR Selector no.  Now this base address is the starting location of LDT in physical memory and limit defines the maximum size of the LDT.  Now the question arises how this LDT gets created?  LDTR is a 16 bit selector which selects one of the descriptors from the GDT. GDT consist of descriptors which are global and LDT consist of those descriptors which are associated to a particular task.LDTR  Firstly the main difference between GDT and LDT is that.  This 32 bit base address and 16 bit limit value are stored in a LDTR invisible register also called as cache register. from there it gets the base address and limit. BY UBAID SAUDAGAR 92 09-10-2012 .  In other words LDTR is a 16 bit selector which points to a LDT descriptor in the GDT. Task register (TR)  The task register is one of the key elements in the protected mode task switching mechanism of the 80386DX microprocessor. BY UBAID SAUDAGAR 93 09-10-2012 .  TR is used to locate a descriptor in the global descriptor table  The initial selector must be loaded into TR under software control. the selector is changed automatically whenever the 80386DX executes an instruction that performs a task switching. This register holds a 16-bit index value called a selector. This starts the initial task.  After this is done. Debug registers 31 Breakpoint address 0 0 𝐷𝑅0 𝐷𝑅1 𝐷𝑅2 𝐷𝑅3 𝐷𝑅4 𝐷𝑅5 𝐷𝑅6 09-10-2012 Breakpoint address 1 Breakpoint address 2 Breakpoint address 3 Intel reserved Intel reserved Breakpoint status BY UBAID SAUDAGAR 94 control Breakpoint 𝐷𝑅7 . BY UBAID SAUDAGAR 95 09-10-2012 .𝐷𝑅3 specify the four linear breakpoints.Debug registers There are in all six debug registers which are accessible to the programmer and on chip support for debugging. Debug control register 𝐷𝑅7 is used to set the breakpoints. If a match occurs then 80386 will cause type 1 interrupt (TRAP) indicating to stop executing in free run mode. Debug registers 𝐷𝑅0 . In other words. that address is stored in these 4 registers. the addresses (32 bit address)where we place a breakpoint. Debug status register 𝐷𝑅6 is used to check the current status of the breakpoints. These addresses are constantly compared with the address generated by the program. Test registers 31 Test command register Test data register 0 𝑇𝑅6 𝑇𝑅7 BY UBAID SAUDAGAR 96 09-10-2012 . paging must be turned off i. This particular mechanism is unique to Intel386 DX. Test command register (𝑇𝑅6 ) and Test Data register (𝑇𝑅7 ). Perform TLB lookups When we need to test the TLB. Two test registers are used for testing mechanism viz.Test registers The Intel 386DX provides a mechanism for testing the TLB if desired. Write entries into the TLB 2. BY UBAID SAUDAGAR 97 09-10-2012 . There are two TLB testing operations: 1.e. (PG = 0 in 𝐶𝑅0 ) to enable the TLB testing hardware and avoid interference with the test data being written to the TLB. the only way was to reset the µp.Virtual 8086 mode of 80386 microprocessor In the real mode. Now we are in the protected mode. but now due to V8086 mode we can switch to real mode without reset. BY UBAID SAUDAGAR 98 09-10-2012 . Thus. In the protected mode all the features of 80386 are available. the virtual 8086 mode of operation of 80386 offers an advantage of executing 8086 programs while in protected mode. generally to go back to real mode the only way was to reset the µp. it is by default in the real mode. Whenever we boot the µp. But to come back to real mode. µp works as a fast 8086. To go the protected mode the PE bit in CR0 is set to 1. Virtual 8086 mode of 80386 microprocessor Virtual 8086 mode is entered by changing the VM bit in the EFLAG register to a logic 1. Therefore VM bit tells us that whether we are using 8086 instructions or 80386 instructions. This mode is entered via an IRET instruction if the privilege level is 00. This bit cannot be set in any other manner. BY UBAID SAUDAGAR 99 09-10-2012 . The virtual 8086 mode executes all the programs at privilege level 3 (the least privilege). The address forming mechanism in virtual 8086 mode is identical to that of 8086. The 80386 allows the operating system to specify which programs use 8086 style address mechanism and which programs use protected mode addressing. Virtual 8086 mode of 80386 microprocessor TaskA of 80386 µp TaskB of 8086 TaskC of 80386 BY UBAID SAUDAGAR 100 09-10-2012 . BY UBAID SAUDAGAR 101 09-10-2012 .Virtual 8086 mode of 80386 microprocessor  Consider the above example: To execute task A we need to enter to enter in the protected mode as it is a 80386 program. programmer executes IRET instruction at privilege level 00 which sets the VM bit in the EFLAG register. Now when the processor switches to task B to execute 8086 program. VM =1 09-10-2012 .Difference between 80286 and 80386 80286  16 bit microprocessor  Accessible memory: Physical memory = 16Mb Virtual memory = 1 Gb  Address bus = 24 bits  Data bus = 16 bits  Paging mechanism not supported  Control registers and test registers not present  On chip debug registers not present  To move from protected mode to real mode µp needs to be reset.e. BY UBAID SAUDAGAR 102 80386  32 bit microprocessor  Accessible memory: Physical memory = 4 Gb Virtual memory = 64 Tb  Address bus = 32 bits  Data bus = 32 bits  Supports 2 level paging mechanism  Control registers and test registers present  On chip debug registers  To move from protected mode to real mode VM bit in the EFLAG must be set i. Data types supported by 80386 Unsigned integer number Signed integer number Packed BCD number Unpacked BCD number 9 in unpacked BCD is 0000 1001 87 in packed BCD is 0000 1000 0000 0111 ASCII numbers or codes Real numbers Short real number = 32 bit Long real number = 64 bit Temporary real number = 80 bit Byte Byte 9 in packed BCD is 1001 87 in packed BCD is 1000 0111 Word Word Dword Dword Qword BY UBAID SAUDAGAR Qword 103 09-10-2012 .