7-1Asynchronous(ripple)counters Chapter 7 Counters and Registers 1 Asychronous Counters(Cont.) 2 Signal Flow • Each FF output drives the CLK input of the next FF. • FFs do not change states in exact synchronism with the applied clock pulses. • There is delay between the responses of successive FFS. • It is also often referred to as a ripple counter due to the way the FFs respond one after another in a kind of rippling effect. • It is conventional in circuit schematics to draw the circuits(whenever possible) such that the signal flow is from left to right, with inputs on the left and outputs one the right. • In this chapter, we will often break with this convention, especially in diagrams showing counters. 3 Example 4 Example • The counter in Figure 7-1 starts off in the 0000 state, and then clock pulses are applied. Some time later the clock pulses are removed, and the counter FFs read 0011. How many clock pulses have occurred? • The counter in Figure 7-1 starts off in the 0000 state, and then clock pulses are applied. Some time later the clock pulses are removed, and the counter FFs read 0011. How many clock pulses have occurred? Answer: 3 or 19 or 163 N*16 + 3 (N is unknown) 5 6 1 • The MOD number can be increased simply by adding more FFs to the counter. • Assume that the counter in Figure 7-1 is holding the count 0101. Such circuits are known as divide-by-N counters.MOD Number Frequency division • The counter in Figure 7-1 has 16 distinct states.e. hours. That is – MOD number = 2N • Example – A counter is needed that will count the number of items passing on a conveyor belt. This 1-HZ waveform is fed to a series of counters. the signal at the output of the last FF(i. pulse-shaping circuit to produce a square wave as illustrated in Figure 7-3. which then count seconds. The 60HZ square wave is then put into a MOD-60 counter. A photocell and light source combination is used to generate a single pulse each time an item crosses its path. which is used to divide the 60-HZ frequency by exactly 60 to produce a 1-HZ waveform. 8 Example • The first step involved in building a digital clock is to take the 60-Hz signal and feed it into a Schmitt-trigger.. How many FFs are required for the MOD-60 counter? 9 10 Review Questions • True or False: In an asychronous counter. What will be the count after 27 clock pulses? • What would be the MOD number of the counter if three more FFs were added? 11 12 2 . all FFs change states at the same time. and so on. How many FFs are required? 7 In any counter. minutes. the MSB) will have a frequency equal to the input clock frequency divided by the MOD number of the counter. The counter must be able to count as many as one thousand items. it is a MOD-16 ripple counter. thus. Example 14 Changing the MOD number • What will be the status of the LEDs when the counter is holding the count of five? • What will the LEDs display as the counter is clocked by a 1-kHz input? • Will the 110 state be visible on the LEDs? Determine the MOD number of the counter in Figure 76(a). no matter what the sequence. 17 18 3 .State Transition Diagram 7-2 Counters with MOD NUMBER < 2N MOD-6 counter produced by clearing a MOD-8 counter when 13 a count of six occurs. • BCD counter – A decade counter counts in sequence from 0000(zero) through 1001(decimal 9). Also determine the frequency at the D output 15 Changing the MOD number 16 Decade Counters/BCD counters Construct a MOD-10 counter that will count from 0000(zero) through 1001(decimal 9) • Decade counter – Any counter has 10 distinct states. Example Review Questions • Construct an appropriate MOD-60 counter. • Show how to wire the 74LS293 as a MOD-10 counter 23 24 4 . • What FF outputs should be connected to the clearing NAND gate to form a MOD-13 counter? • True of False: All BCD counters are decade counters. Determine the frequency at Q3. • What is the output frequency of a decade counter that is clocked from a 50-KHz signal? 19 20 7-3 IC Asynchronous counters RESET IN OUTPUT ___ ___ Ro1 Ro2 | Qd Qc Qb Qa -------------------------1 1 | 0 0 0 0 0 X | COUNT X 0 | COUNT 21 Example 22 Example • Show how the 74LS293 should be connected to operate as a MOD-16 counter with a 10-kHz clock input. 29 30 5 .Example Example • A way to get a MOD-60 counter is shown below. • Show how to wire a 74LS293 as a MOD-14 counter 25 Review Questions 26 7-4 Asychronous Down counter • A 2-kHz clock signal is applied to CP of a 74LS293. What is the frequency at Q3? • What would be the final output frequency if the order of the counters were reversed in Figure 7-12? • What is the MOD number of a 74HC4040 counter? • What would the notation “DIV64” mean on a counter symbol? • Which outputs would you connect to an AND gate to convert the 74HC4024 to a MOD-120 counter? 1 27 28 7-5 Propagation delay in ripple counters Review Questions • What is the difference between the counting sequence of an up counter and a down counter? • Describe how an asynchronous down-counter circuit differs from an up-counter circuit. Explain how this circuit works. • A certain J-K flip-flop has tpd=12 ns. Only those FFs that are supposed to toggle on that NGT should have J=K=1 when that NGT occurs. 33 Synchronous คุณสมบัติของ JK FF J K Q 0 0 No Change 0 1 0 1 0 1 1 1 Toggle 34 Synchronous Counter Modulo 6 Counter สถานะของเอาทพุท Qเดิม Qไหม J K 0 0 0 d 0 1 1 d 1 0 d 1 1 1 d 0 35 CP 0 1 2 3 4 5 6 Q2 0 0 0 0 1 1 0 Q1 0 0 1 1 0 0 0 Q0 0 1 0 1 0 1 0 J0 K0 1 d J1 K1 0 d d 1 1 d d 1 1 d d 1 1 d d 0 0 d 0 1 d d J2 K2 0 d 0 d 0 1 d d d d 0 1 36 6 . – Overcome the problem caused by FF propagation delay. as is discussed later. we need • Explain why a ripple counter’s maximum frequency limitation decreases as more FFs are added to the counter.Discussion on Ripple Counter Review Questions • For proper counter operation. Another problem caused by propagation delays in asychronous counters occurs when the counter outputs are decoded. especially for large number of bits. 31 32 7-6 Synchronous(Parallel) counters Circuit operation • Synchronous(parallel) counters – All of the FFs are triggered simultaneously by the clock input pulses. What is the largest MOD counter that can be constructed from these FFs and still operate up to 10 MHz? Tclock ≥ N × t pd Asychronous counters are not useful at very high frequencies. 0 d Q0 K0 Q2Q1 10 d J2 Q2Q1 0 11 d Q0 1 01 d J1 Q2Q1 0 00 K1 = 1 00 01 11 10 d d d d d d 1 0 K2 = Q1 40 Logic diagram Qa “0” CP (LSB) K clr 41 Q J a set Q Qc Qb “1” (MSB) Q J K b clr Q Q J K c clr Q 42 7 .J0 Q2Q1 Q0 0 1 00 11 1 d 1 d d d d Q0 00 1 Q0 01 11 d d d d 00 01 10 Q0 0 1 11 1 d d d 1 J2 = Q1Q0 d Logic diagram 1 K0 = 1 00 d Q0 0 1 01 d K2 Q2Q1 10 d 1 K1 Q2Q1 J1 = Q2Q0 0 1 1 J0 = 1 0 J2 Q2Q1 K0 Q2Q1 00 01 11 10 Q0 d d d d 0 10 1 J1 Q2Q1 1 01 1 11 d d d d 00 01 K clr 11 d d d d d d Q2 0 0 1 1 0 Q1 0 1 0 1 0 Q0 1 1 1 1 1 J1 K1 1 d d 0 d 0 d 0 d 1 1 d d 1 a clr Q J K Q b clr Q J c K Q Q clr 1 K2 = Q0 J0 K0 d 0 Q 10 37 38 J0 Q2Q1 Q0 Synchronous Counter 1 3 5 7 1 CP 0 1 2 3 4 (MSB) (LSB) J CP K1 = Q0 Qc Qb Qa “1” 10 0 J2 K2 0 d 1 d d 0 d 1 1 d d d d d 1 39 Q0 0 00 01 11 K1 Q2Q1 10 d d d 1 d d 1 Q0 0 1 J1 = 1 00 01 11 d d d 0 1 d d 01 1 J2 = Q1 d 10 d K0 = 0 00 01 11 10 d d d d 1 1 d Q0 0 11 d d K2 Q2Q1 10 d 00 d 1 J0 = 1. . – Total delay • FFtpd+ANDgate tpd • Determine fmax for the counter of Figure 7-17(a) if tpd for each FF is 50ns and tpd for each AND gate is 20 ns.(Synchronous Counter) Advantage of Synchronous counters over Asychronous Example • States are changed simultaneously. 74HC160/162: Synchronous decade counters – 74ALS161/163. 74HC161/163: Synchronous MOD-16 counters 47 48 8 . • Actual Ics – 74ALS160/162.วงจรนับแบบซิงโครนัส (Synchronous Counter) 43 44 45 46 วงจรนับแบบซิงโครนัส หาร . • What must be done to convert this counter to MOD-32? • Determine fmax for the MOD-32 parallel counter.. Compare this value with fmax for a MOD-16 ripple counter... 74HC161. 74ALS163 – 74Hc160.7-7 Synchronous Down and UP/Down counters Review Questions • What is the advantage of a synchronous counter over an asynchronous counter? What is the disadvantage? • How many logic devices are required for a MOD-64 parallel counter? • What logic signal drives the J. 53 54 9 .K inputs of the MSB flip-flop for the counter of question 2? 49 Example 50 Presettable counters • What problems might be caused if the UP/Down signal changes levels on the NGT of the clock? 51 Synchronous Presetting 52 Review Questions • Examples of IC counters – 74ALS160. 74ALS612. 74ALS161. 74HC162. 74HC163 • What is meant when we say that a counter is presettable? • Describe the difference between asynchronous and synchronous presetting. • Describe the function of the MR input • True or False: The 74HC193 cannot be preset while MR is active. • What logic levels must be present at CPD. PL and MR in order for the 74ALS193 to count pulses that appear at CPU? • What would be the maximum counting range for a fourstage counter made up of 74HC193 Ics? 59 60 10 .Example The 74ALS193/HC193 55 Example 56 Variable MOD Number using the 74ALS193/HC193 57 Multistage Arrangement 58 Review Questions • Describe the function of the input PL and P0 to P3. – Active-High Decoding – Active-Low Decoding – BCD counter decoding 61 Example 62 Active-LOW Decoding • How many AND gates are required to decode completely all of the states of a MOD-32 binary counter? What are the inputs to the gate that decodes for the count of 21? 63 BCD Counter Decoding 64 Review Questions • How many gates are needed to decode a six-bit counter fully? • Describe the decoding gate needed to produce a LOW output when a MOD-64 counter is at the counter of 23.7-11 Decoding a counter Active-High Decoding • Mentally decoding the binary states of the LEDs – Becomes inconvenient as the size of the counter increases • Electronically decoding – To control the timing or sequencing of operations automatically without human intervention. 65 66 11 . • How does strobing eliminate decoding glitches? 69 7-15 Shift-Register Counters 70 Starting a Ring Counter 71 72 12 .7-12 Decoding Glitches Strobing 67 Review Questions 68 Cascading BCD counters • Explain why the decoding gates for an asynchronous counter may have glitches on their outputs. How many FFs are needed in a MOD-16 ring counter? How many are needed in a MOD-16 Johnson Counter? 75 13 .Johnson Counter Decoding A Johnson Counter 73 74 Review Questions • • • • • Which shift-register counter requires the most FFs for a given MOD number? Which shift-register counter requires the most decoding circuitry? How can a ring counter be converted to a Johnson counter? True or False: – The outputs of a ring counter are always square waves. – The decoding circuitry for a Johnson counter is simpler than for a binary counter – Ring and Johnson counters are synchronous counters.