Chapter-4 Class Notes of Applied Electronics IIApril, 2017 4. Wave Shaping Circuits 4.1 Introduction In this chapter we will present methods of generating waveforms. Waveforms are classified as periodic or non periodic waveforms. A waveform which undergoes a pattern of changes, returns to its original pattern, and repeats the same pattern of changes is called a Periodic waveform. Common Periodic waveforms are the sine wave, square wave, rectangular wave, sawtooth wave, trapezoidal wave, and trigger pulses. A wave form which has not repeated patterns is called non-periodic waveform. 4.2 Waveform generator circuits, sample and hold circuits Currently we have several pulsed circuits and waveform generators also known as relaxation oscillators. These circuits are part of a family of circuits that include differentiators, integrators, clipping and clamping circuits, pulse−timing and delay circuits, logic circuits, and switching circuits. In this chapter we will discuss the Schmitt trigger, the three types of multivibrators, and the 555 Timer. Sinusoidal oscillators are discussed in next Chapter. Nonsinusoidal oscillators generate complex waveforms such as those just discussed. Because the outputs of these oscillators are generally characterized by a sudden change, or relaxation, these oscillators are often called relaxation oscillators. The pulse repetition rate of these oscillators is usually governed by the charge and discharge timing of a capacitor in series with a resistor. However, some oscillators contain inductors that, along with circuit resistance, affect the output frequency. These RC and LC networks within oscillator circuits are used for frequency determination. Within this category of relaxation oscillators are multivibrators, blocking oscillators, and sawtooth- and trapezoidal-wave generators. As the name indicates, a sample and hold circuit is a circuit which samples an input signal and holds onto its last sampled value until the input is sampled again. Sample and hold circuits are commonly used in analogue to digital converts, communication circuits, PWM circuits etc. Many electronic circuits are not in an "on" condition all of the time. In computers, for example, waveforms must be turned on and off for specific lengths of time. The time intervals vary from tenths of microseconds to several thousand microseconds. Square and rectangular waveforms are normally used to turn such circuits on and off because the sharp leading and trailing edges make them ideal for timing purposes. 4.3 Schmitt Trigger Circuits, Multivibrators Schmitt Trigger is a bistable multivibrator circuit shown in Fig. 4.1(a). Figure 4.1 Schmitt trigger circuit and waveforms for increasing and decreasing input signals Electrical and Computer Engineering Department CET, Adigrat University, By Bisrat Kahsay 1 Chapter-4 Class Notes of Applied Electronics II April, 2017 The Schmitt trigger circuit and transfer characteristics are similar to the comparator. It provides an voltage when its input signal Vs reaches some predetermined value set at the non−inverting input of the op amp. The output of the op amp changes from the positive saturation voltage Vout(max) to its negative saturation voltage -Vout(max) and vice versa. As shown in Fig. 4.1(b), the output is positively saturated as long as the input signal Vs is less than the upper) threshold V+ upper. If the input signal Vs rises slightly above this threshold voltage, the output drop abruptly to -Vout(max) and stays there until Vs drops below a lower threshold voltage V+ lower. The threshold voltages V+ upper and V+ lower are determined by the resistors and, and the reference voltage Vref. These threshold voltages can be found by application of KCL at the non−inverting input of the op amp. Thus, (4.1) In eqn. (4.1), when Vout is the maximum positive output voltage, V+ = V+upper, and when Vout is the maximum negative output voltage, V + = V+lower . Normally, the peak−to−peak output voltage of the Schmitt trigger of Fig. 4.1 is often limited by the use of back−to−back zeners across the output terminal and ground. The zener voltages are chosen so that the output swing from positive to negative or vice versa, is compatible with commercially available IC digital devices. Example 4.1 For the Schmitt trigger circuit of Fig. 4.2(a), the input signal is Vs as shown in Fig. 4.2(b). Find and sketch V +upper and V+lower. Solution: It is given that the Schmitt trigger saturates positively at +12. Then, with eqn. (4.1) That is, when the input signal VS exceeds this value, the output abruptly swings to negative saturation, i.e., -12V as shown in Fig. 4.3. Electrical and Computer Engineering Department CET, Adigrat University, By Bisrat Kahsay 2 4. 2017 Figure 4. when the input signal VS drops below this value. the output drops again to –12 V as shown in Fig. Electrical and Computer Engineering Department CET. One of the amplifiers is conducting while the other is cut off.2 Schmitt trigger circuit and input signal waveform for Example 4. By Bisrat Kahsay 3 ..1 When the output saturates negatively at -12V the lower threshold voltage is That is.3 Waveforms for Example 4. 4. i.Chapter-4 Class Notes of Applied Electronics II April. is basically two amplifier circuits arranged with regenerative feedback.1 Figure 4.3. as shown in Fig. and when the input signal rises again to 2.24 V.4. The type of circuit most often used to generate square or rectangular waves is the multivibrator. Adigrat University.e. A multivibrator. +12 V. the output abruptly swings back to positive saturation. when the transistor is driven into saturation. its collector voltage will be about 0 volts. However. Electrical and Computer Engineering Department CET. and its collector voltage will be almost VCC. This principle is used in multivibrators. Adigrat University. the transistor can be driven into cutoff. 2017 Figure 4. A circuit that is designed to go quickly from cutoff to saturation will produce a square or rectangular wave at its output.4 Astable multivibrator When an input signal to one amplifier is large enough.Chapter-4 Class Notes of Applied Electronics II April. By Bisrat Kahsay 4 . This is an astable multivibrator. one transistor remains in conduction and the other remains cut off until an external signal is applied. Monostable. It is impossible to tell which transistor will actually conduct when the circuit is energized. either of the transistors may be assumed to conduct for circuit analysis purposes. It is called free-running because it alternates between two different output voltage levels during the time it is on.1 Astable Multivibrator An astable multivibrator is also known as a free-running multivibrator. We assume Q1 saturates and Q2 is in cutoff because the circuit is symmetrical. 4. and Bistable. The bistable multivibrator has two stable states. The astable circuit has no stable state. The multivibrator then changes back (FLOPS) to its first stable state. 2017 4. The output remains at each voltage level for a definite period of time. This situation is shown in Fig. the circuit will return to its original condition where it remains until the next signal arrives.5 Astable multivibrator (Q1 saturated) Electrical and Computer Engineering Department CET. The astable multivibrator is said to oscillate. The monostable circuit has one stable state. R2 = R3. The astable multivibrator has two outputs. A steady state exists when circuit operation is essentially constant. If you looked at this output on an oscilloscope. By Bisrat Kahsay 5 .4 again. The three types of multivibrators are the Astable. 4. R1 = R4. A signal must be applied to change this condition. the transistors alternately switch from cutoff to saturation at a frequency determined by the RC time constants of the coupling circuits. mono-stable and bi-stable circuits Multivibrators are classified according to the number of steady (stable) states of the circuit. that is. To understand why the astable multivibrator oscillates. you would see continuous square or rectangular waveforms.4. It remains in one of the stable states until a trigger is applied.4 Astable.5. that is. For this reason. and Q1 = Q2. Let's look at the multivibrator in Fig. C1 = C2. After a period of time. 4. Figure 4. one transistor conducts while the other is cut off.Chapter-4 Class Notes of Applied Electronics II April. With no external signal applied. It then FLIPS to the other stable condition and remains there until another trigger is applied. Adigrat University. but no inputs. determined by the internal RC components. assume that transistor Q1 saturates and transistor Q2 cuts off when the circuit is energized. The negative voltage accumulated on the right side on capacitor C1 has caused Q2 to conduct. The time necessary for Q2 to become saturated is determined by the time constant R2C1. Notice that the right-hand side of capacitor C1 is connected to the base of transistor Q2.6 is the mirror image of Fig. and the voltage at output 2 changes from approximately −VCC to approximately 0 volts.4.4. By Bisrat Kahsay 6 . The right-hand side of capacitor C1 is becoming increasingly negative. the output voltage (from either output of the multivibrator) alternates from approximately 0 volts to approximately −VCC. Since Q1 offers almost no resistance in its saturated state. 4. forcing Q1 to cutoff. all the current in the circuit flows through Q1. When the base of Q1 becomes negative enough to allow Q1 to conduct. Electrical and Computer Engineering Department CET. As the left side of C2 becomes more negative. which is now at cutoff. In Fig. This change in voltage is coupled through C2 to the base of Q1. Now the following sequence of events takes place almost instantaneously. The next state is shown in Fig. If the base of Q2 becomes sufficiently negative. The time may range from a microsecond to as much as a second or two.6 the left side of capacitor C2 becomes more negative at a rate determined by the time constant R3C2. 2017 Essentially. timing and gating circuits often have different pulse widths as shown in Fig. the time period of higher voltage (−VCC) and the time period of lower voltage (0 volts) will be equal. 4. Let's analyze what is happening.and lower-voltage times. remaining in each state for a definite period of time.6 Astable Multivibrator (Q2 saturated) Notice that Fig. Now Q1 is in cutoff and Q2 is in saturation. Q2 starts conducting and quickly saturates. 4. Adigrat University. Other applications require differing higher. as shown in Fig. In some applications. the base of Q1 also becomes more negative.Chapter-4 Class Notes of Applied Electronics II April. Figure 4.7. Q1 will again go into saturation. The resulting change in voltage at output 1 will cause Q2 to return to the cutoff state. the rate of charge of C1 depends only on the time constant of R2 and C1 (recall that TC = RC). Look at the output waveform from transistor Q2. 4. For example. Q1 offers almost no resistance to current flow. 4. After a certain period of time. the base of Q2 will become sufficiently negative to cause Q2 to change states from cutoff to conduction.6. Notice that capacitor C1 is charging. Q2 will conduct.8. By Bisrat Kahsay 7 . R3. astable multivibrator. shows the diagram of a triggered.8 Rectangular waves Frequency Stability Some astable multivibrators must have a high degree of frequency stability.7 Square wave output from Q2. 4. One way to obtain a high degree of frequency stability is to apply triggers. At time T0.9A Triggered astable multivibrator and output Electrical and Computer Engineering Department CET. Fig. Observe the parallel paths for C3 to discharge. Adigrat University. 2017 Figure 4. and R6. The circuit will remain in this condition as long as the base voltage of Q2 is positive. which drives Q2 to cutoff. The length of time the base of Q2 will remain positive is determined by C3. view (A). Figure 4. Figure 4.Chapter-4 Class Notes of Applied Electronics II April. a negative input trigger to the base of Q1 (through C1) causes Q1 to go into saturation.9. It is used in computer logic systems and communication navigation equipment. The base voltage waveform of Q1 shows a positive potential that is holding Q1 at cutoff. 4. Q1 goes into saturation and Q2 is caused to cut off. With no input signal (quiescent condition) one amplifier conducts and the other is in cutoff. The input is triggered with a pulse of voltage. This voltage would normally hold Q1 at cutoff until a point between T2 and T3. However. The monostable multivibrator is basically used for pulse stretching. All of the square output pulses are of the same amplitude and time duration.Chapter-4 Class Notes of Applied Electronics II April. The monostable multivibrator actually takes this series of input triggers and converts them to uniform square pulses. 4. T6) is applied. The output remains at this new voltage level for a definite period of time. at time T2 another trigger is applied to the base of Q1. Q2 comes out of cutoff and goes into saturation. Then the circuit automatically reverts to its original condition and remains that way until another trigger pulse is applied to the input. This action repeats each time a trigger (T2.2 Monostable Multivibrator The monostable multivibrator (sometimes called a One-Shot Multivibrator) is a square. Adigrat University.or rectangular-wave generator with just one stable condition. Also. At time T1. Figure 4. causing it to begin conducting. This is to make certain the triggers control the pulse repetition time of the output.10. Q1 is caused to come out of saturation and is cut off.9B Triggered astable multivibrator and output The pulse repetition time of the input triggers must be shorter than the natural free-running pulse repetition time of the astable multivibrator. T4. as shown in Fig. By Bisrat Kahsay 8 .9 shows the waveforms associated with the circuit. or the trigger pulse repetition frequency must be slightly higher than the free-running pulse repetition frequency of the circuit.4. The operation of the monostable multivibrator is relatively simple. The output changes from one voltage level to a different voltage level. 4.10 Monostable multivibrator block diagram Electrical and Computer Engineering Department CET. 2017 View (A) of Fig. Figure 4. Q1 is cut off. This positive voltage causes Q1 to cut off. 4. Adigrat University. as shown in Fig. one transistor conducts and the other cuts off when the circuit is energized. so its collector is essentially at 0 volts. Like the astable multivibrator. 4. Therefore.11 Monostable multivibrator schematic Recall that when the astable multivibrator was first energized. R5 and Electrical and Computer Engineering Department CET. Q1 is cut off and Q2 is saturated before a trigger pulse is applied. As stated above. it was impossible to predict which transistor would initially go to cutoff because of circuit symmetry. 2017 The schematic for a monostable multivibrator is shown in Fig.12).Chapter-4 Class Notes of Applied Electronics II April. Q2 is saturated and has practically no voltage drop across it. The circuit is shown in its stable state. Figure 4.12. 4. Figure 4.11. and the collector of Q1 is at −VCC. By Bisrat Kahsay 9 . The one-shot circuit is not symmetrical like the astable multivibrator. Positive voltage VBB is applied through R5 to the base of Q1. Transistor Q2 saturates because of the negative voltage applied from -VCC to its base through R2. so no current flows through R1.12 Monostable multivibrator (stable state) Let's take a more detailed look at the circuit conditions in this stable state (refer to Fig. The voltage divider formed by R5 and R3 then holds the base of Q1 negative. C1 must be charged to nearly VCC volts with the polarity shown. so the circuit cannot be turned off here. Q1 is held in saturation by the negative voltage applied through R3 to its base. 4. and its collector voltage immediately rises to ground potential. By Bisrat Kahsay 10 . the collector voltage of Q2 immediately drops to VCC. The tie point between these two resistors will be positive. To see how it does this. The time required for C1 to discharge depends on the RC time constant of C1 and R2. through R2 to the other side of C1. Figure 4. ensuring that Q1 remains cutoff. C1 will now begin to discharge through Q1 to ground. with its negative terminal on the collector of Q1 and its positive terminal connected to the base of Q2. back through −VCC.13 Monostable multivibrator (triggered) The one-shot multivibrator has now been turned on by applying a pulse at the input. This sharp voltage increase is coupled through C1 to the base of Q2. Notice that the base of Q2 is connected to C1. the base of Q1 is held positive.14 is a timing diagram that shows the negative input pulse and the resultant waveforms that you would expect to see for this circuit description. causing Q2 to cut off. This voltage is what cuts off Q2. Fig. 2017 R3 form a voltage divider from VBB to the ground potential at the collector of Q2. Q1 quickly saturates.13). Assume that a negative pulse is applied at the input terminal. and Q1 is locked in saturation. 4. Thus. It will turn itself off after a period of time. look at Figure 4. C2 couples this voltage change to the base of Q1 and starts Q1 conducting. Electrical and Computer Engineering Department CET.13 again. Now that all the components and voltages have been described for the stable state.Chapter-4 Class Notes of Applied Electronics II April. The positive charge on C1 keeps Q2 cutoff. let us see how the circuit operates (see Fig. When the collector of Q1 switches from -VCC volts to 0 volts the charge on C1 acts like a battery. placing Q2 in cutoff. Adigrat University. If the collector of Q1 is near −VCC and the base of Q2 is near ground. Q2 will remain saturated because the base of Q2 is very slightly negative as a result of the voltage drop across R2. Remember that a positive voltage change (essentially a pulse) was coupled from the collector of Q1 when it began conducting to the base of Q2. Q1 is cut off and Q2 is conducting. With the forward bias. C1 now discharges and keeps Q2 cut off.14 Waveforms of a monostable multivibrator (triggered) The only part of the operation not described so far is the short C1 charge time that occurs right after Q1 and Q2 return to their stable states.15. The input trigger (positive pulse at T1) is applied to the collector of Q1 and coupled by C1 to the base of Q2 causing Q2 to be cut off. By Bisrat Kahsay 11 .15A Monostable miltivibrator and wave shapes. Adigrat University. This charge time is determined by the R1C1 time constant. Figure 4. Q1 conducts. When Q2 conducts again. and the collector voltage of Q1 goes to about 0 volts. Another version of the monostable multivibrator is shown in figure 4. 2017 Figure 4. View (A) is the circuit and view (B) shows the associated waveforms. The more negative voltage at the collector of Q2 forward biases Q1 through R4. Q2 remains cut off until C1 discharges enough to allow Q2 to conduct again (T2).Chapter-4 Class Notes of Applied Electronics II April. The circuit remains in this stable state until the next trigger arrives (T3). The collector voltage of Q2 then goes −VCC. Schematic Electrical and Computer Engineering Department CET. In its stable condition (T0). The circuit returns to its quiescent state and has completed a cycle. This is simply the time required for C1 to gain electrons on its left side. its collector voltage goes toward 0 volts and Q1 is cut off. Chapter-4 Class Notes of Applied Electronics II April. Increasing the value of R3 widens the gate.15B Monostable miltivibrator and wave shapes.16 shows the relationships between the trigger and the output signal. To decrease the gate width. 4. a complete cycle. or a positive and negative alternation of the output. decrease the value of R3. Although the durations of the gates are different. View (D) of the figure illustrates that the trailing edge of the positive alternation is variable. Figure 4.16 Monostable multivibrator waveforms with a variable gate The reason the monostable multivibrator is also called a one-shot multivibrator can easily be seen. 2017 Figure 4. Fig. the duration of the complete cycle remains the same as the pulse repetition time of the triggers. Wave shapes Note that R3 is variable to allow adjustment of the gate width. Electrical and Computer Engineering Department CET. views (B) and (C) show the different gate widths made available by R3. For every trigger pulse applied to the multivibrator. Increasing R3 increases the discharge time for C1 which increases the cutoff time for Q2. By Bisrat Kahsay 12 . Adigrat University. View (A) of the figure shows the input trigger. is completed. R1 and R7 are the collector load resistors. R7. The bistable multivibrator circuit and the associated waveforms are shown in Fig.17. This type of coupling is required because the circuit depends on input triggers for operation. Observe that this is direct coupling of feedback. C1 and C2 couple the input triggers to the transistor bases. By Bisrat Kahsay 13 . and R5 provide forward bias for Q2. Voltage dividers R1. Both transistors use common emitter resistor R4 which provides emitter coupling. occurring at different times.17B Bistable multivibrator and waveforms Electrical and Computer Engineering Department CET.3 Bistable Multivibrator As the name implies. In this circuit. 4. not on RC time constants inside the circuit.17A Bistable multivibrator and waveforms Figure 4. The trigger need not have a fixed prf. respectively. If a trigger of the correct polarity and amplitude is applied to the circuit. and R3 provide forward bias for Q1. views (A) and (B). Adigrat University. in fact. R6. triggers from different sources. Figure 4. 2017 4. the bistable multivibrator has two stable states. can be used to switch this circuit.4.Chapter-4 Class Notes of Applied Electronics II April. it will change states and remain there until triggered again. These resistors also couple the collector signal from one transistor to the base of the other. R2. that is. one to turn it on and the other to turn it off. "bi" meaning two. When Q2 conducts less. This regenerative action continues until Q2 is cutoff and Q1 is saturated. Q1 is brought into conduction and the regenerative switching action cuts off Q2. When power is first applied. it would measure either a small positive or negative voltage. Both transistors have forward bias and both conduct. its collector voltage becomes more negative. the collector voltage becomes negative. each transistor amplifier has the same component values. The flip-flop can rapidly flip from one state to the other and then flop back to its original state. stable means that the flip-flop will remain in a particular state indefinitely. The circuit is in a stable state and will remain there until a trigger is applied to change the state. its collector voltage becomes positive. It will not change states unless the proper type of trigger pulse is applied. the Flip-Flop circuit (Fig. The negative-going change at the collector of Q2 is coupled to the base of Q1 and causes Q1 to conduct even more heavily. The bistable multivibrator that most technicians know is commonly known by other names: the Eccles-Jordan circuit and. At T1. As Q2 goes into conduction. No matter which voltage is measured. a negative trigger is applied to both bases through C1 and C2. If a voltmeter were connected to the output of a flip-flop. The trigger overcomes cutoff bias on Q2 and causes it to conduct. 2017 Notice that the circuit is symmetrical. the flip-flop would be stable. Remember. Due to some slight difference between the two circuits. The bistable multivibrator will continue to change states as long as triggers are applied. This decreases the forward bias of Q2 and decreases the conduction of Q2. more commonly. This switching action causes a very rapid change of state with Q2 now conducting and Q1 cut off. one transistor will conduct more than the other. The positive-going change at the Q2 collector causes a reverse bias on the base of Q1. The trigger does not affect Q1 since it is already conducting. Notice that two input triggers are required to produce one gate. The flip-flop is a bistable multivibrator. the voltage divider networks place a negative voltage at the bases of Q1 and Q2. At T2. 4. The increased conduction of Q1 causes the collector voltage of Q1 to be less negative (more voltage drop across R1).Chapter-4 Class Notes of Applied Electronics II April.18). a negative trigger is again applied to both bases. or a particularly low voltage (essentially 0 volts). that is. By Bisrat Kahsay 14 . The input trigger frequency is twice the output frequency. Electrical and Computer Engineering Department CET. Assume that Q1 conducts more than Q2. This time. As the conduction of Q1 decreases to the cutoff point. Adigrat University. the flip-flop has two stable states. Think of the flip-flop as two common-emitter amplifier circuits. point (C). Point (D) is connected through R4 to C4 to point (A). Notice that the basic flip-flop. Figure 4.18 Basic flip-flop Flip-flops are used in switching-circuit applications (computer logic operations) as counters. shift registers. you should be able to see how it maintains its stable condition. where the output of one amplifier is connected to the input of the other amplifier. and in memory circuits. The inputs are coupled to the bases of the transistors and the outputs are coupled from the collectors of the transistors. Taking a close look at the flip-flop circuit. which is the output of Q1. 4.18. 2017 Figure 4. illustrated in Fig. is connected through R3 and C3 to the input (point (B)) of transistor Q2. and vice-versa.Chapter-4 Class Notes of Applied Electronics II April. Typical values for the resistors and applied voltages are shown in Fig. clock pulse generators. By Bisrat Kahsay 15 . 4. The capacitors have been removed for simplicity. Adigrat University. By the same token.19. They are also used for relay-control functions and for a variety of similar applications in radar and communications systems. has two inputs and two outputs. Point (A) is the input to transistor Q1.19 Flip-flop (capacitors removed) Electrical and Computer Engineering Department CET. Fig. One voltage divider consisting of resistors R1.21 Flip-flop (Q2 voltage divider) Electrical and Computer Engineering Department CET. 4. R6. Adigrat University. R4. Figure 4. and R6 supplies the bias voltage to the base of Q1. and +VBB. R3.20 Flip-flop (Q1 voltage divider). very little voltage is dropped across R6 (approximately 0. This voltage (-9. Assume that Q1 (Fig. The voltage at output 2 would measure -9.5 volt). are shown in the figure.5 volts) is considered to be a HIGH output. this places the base of Q1 at ground potential. By Bisrat Kahsay 16 . and R5 and supplies the bias voltage to the base of Q2. R1.5 volts to ground (approximately -VCC). The voltages developed in the voltage divider.20) is initially saturated and Q2 is cut off. Since no current flows through Q2. −VCC. The other voltage divider consists of R2. 2017 Two voltage-divider networks extend from -10 volts (VCC) to +6 volts (VBB). 4.Chapter-4 Class Notes of Applied Electronics II April.21 shows the values of the other voltage-divider network. Figure 4. In effect. Recall that the voltage drop from the base to the emitter of a saturated transistor is essentially 0 volts. R4. Capacitors C3 and C4 transmit almost instantaneously any changes in voltage from the collector of one transistor to the base of the other. By Bisrat Kahsay 17 . assume that transistor Q1 is saturated and transistor Q2 is cut off. a large current flows through R5. Adigrat University. 4. In Fig. First. The meter would measure a positive voltage (between 0 volts and +6 volts) at the base of Q2 (point (B)).22 Flip-flop As before. Two methods are available to cause the flip-flop to change states. Second. 4. Figure 4. the flip-flop would change back to its original state as shown in Fig. the same result can be achieved by applying a negative-going pulse to input 2. Capacitors C1 and C2 are input coupling capacitors. 4. as before. This is because Q1 is already cut off. Transistor Q2 would then change from Cutoff to saturation. 2017 With Q1 saturated. A positive voltage on the base of a pnp transistor will cause that transistor to cut off.22 to change the state of the flip-flop from one condition to the other. The flip-flop has now changed states. Q1 is cut off and Q2 is saturated. a positive pulse on its base has no effect. called a trigger pulse. The meter would measure approximately 0 volts (ground potential) at point (C). a pulse is applied to the saturated transistor causing it to cut off. a positive-going pulse can be applied to input 1 to cause Q1 to change from saturation to cutoff. Notice that point (B) is located between point (C) (at 0 volts) and +VBB (at +6 volts).19 must be returned to the flip-flop as shown in figure 4. An input pulse which is of the correct polarity to change the state of the flip-flop is.Chapter-4 Class Notes of Applied Electronics II April. therefore. The capacitors that were removed from Fig. Electrical and Computer Engineering Department CET. If one transistor is saturated. the other must be cut off.23 a positive-going trigger pulse has been applied to input 1.24. Normally. But if a positive-going trigger pulse were applied to input 2. it has no effect. If a second positive-going trigger pulse is applied to input 1. The flip-flop is stable in this state. The functional operation would not change. you may see either type of transistor used. the basic flip-flop has used only pnp transistors. npn or pnp.24 Flip-Flop (original state) So far. 2017 Figure 4. The two inputs are represented by the lines on the left and the outputs by the Electrical and Computer Engineering Department CET. Adigrat University. By Bisrat Kahsay 18 .23 Bistable multivibrator (flip-flop) Figure 4.26. 4. A special kind of block diagram has been adopted as a standard symbol for the flip-flop and is shown in Figs.Chapter-4 Class Notes of Applied Electronics II April. only the polarities required for conduction and cutoff change.25 and 4. A symbolic block diagram is sometimes used to avoid confusion about voltage polarities. It could have just as easily used npn transistors. As a technician. At T2 a positive pulse on the CLEAR input drives the "0" output to a CLEAR state. At T1 a positive pulse on the SET input drives the "1" output to the SET state. This condition is called the SET STATE. a positive or negative voltage would also indicate that the flip-flop is in the CLEAR state.25 Flip-Flop (SET state) Figure 4. 4.Chapter-4 Class Notes of Applied Electronics II April. The "1" output goes to 0 volts. the flip-flop is in the SET state prior to T0 (negative voltage on the "1" output).26 Flip-Flop (CLEAR state) If a trigger pulse is applied to the CLEAR input. This input has no effect since the f/f is already in the CLEAR state. This condition is called the Clear State. as shown in Fig. At the same time. By Bisrat Kahsay 19 . The positive pulse at T0 on the CLEAR input shifts the f/f to the CLEAR state (negative voltage at the "0" output). and T3) with the input pulse.27. If the "0" output is measured. you can measure either the "1" or the "0" output. 2017 lines on the right. the "0" output equals 0 volts. T2.27 Flip-flop with trigger pulse on SET and inputs Electrical and Computer Engineering Department CET. Studying this figure should help you understand how the flip-flop works. only one reading is necessary. Now compare the changes in output voltage at each point in time (T0. a positive or negative voltage is produced at the "0" output. Either way. Figure 4. At T3 another positive pulse is applied to the CLEAR input. Inputs to a flip-flop are S (SET) and C (CLEAR) and OUTPUTS from a flip-flop are "1" and "0. 4. Measuring 0 volts at the "1" output indicates that the flip-flop is in the CLEAR state. To determine what state the flip-flop is in.26." A trigger pulse applied to the SET input causes the "1" output to be a positive or negative voltage. T1. depending on the type of transistor. Adigrat University. Figure 4. In Fig. and if ? is Low. and these outputs are determined by the inputs Threshold at the plus (+) input of Comparator 1. 2017 4. The SR flip-flop is Set when a High level is applied to the S input. The output of the 555 Timer is the ? output of the SR flip−flop and when it is Low. and if the input Discharge is High. if ? is High (Set state). ?̅ is Low. The outputs of the comparators determine the state of the SR flip−flop whose output is either ? or ?̅ . 4. Electrical and Computer Engineering Department CET. ?̅ will be High (Reset state) or vice versa.28 Simplified circuit for the 555 Timer We observe that this IC includes a resistive voltage divider consisting of three identical resistors and this divider sets the voltage at the plus (+) input of the lower comparator at +1/3VCC and at plus (+) input of the upper comparator at +2/3VCC.5 The 555 Timer The 555 Timer circuit is a widely used IC for generating waveforms. and Trigger at the minus (−) input of Comparator 2.Chapter-4 Class Notes of Applied Electronics II April. Figure 4. By Bisrat Kahsay 20 . the flip−flop is Set or Reset depending on the outputs of the two comparators. and it is Reset when a High level is applied to the R input.28. A simplified diagram is shown in Fig. Thus. the transistor will be saturated and it will provide a path to the ground. ?̅ will be High. Accordingly. Adigrat University.