CPLD-Oriented Design Projects for the First Course in Digital SystemsDavid J. Ahlgren Department of Engineering Trinity College Hartford, CT 06106 Abstract - This paper reports on enhanced educational outcomes that have been achieved at Trinity College by introducing complex programmable logic devices (CPLD’s) and the hardware description language VHDL in the first course in digital design. Using Altera’s Max + Plus II package and concurrent engineering practices, a team of eight students implemented a fully operational four-bit “tiny” CPU as a three-week final design project. Such successes demonstrate that modern CAD tools and use of CPLD's encourage creativity and system-level thinking in the first course.These basic outcomes are realized primarily through a sequence of introductory laboratory design projects. Based on the standard LSTTL family, these projects have included traffic light controllers, adders and subtractors, and minicommunication networks. Design has been facilitated by the use of a a user-friendly schematic-capture and simulation program, B^2Logic, that runs on Macintosh and PC machines. (B^2Logic is available from Beige Bag Software, Ann Arbor, MI.) Students use B^2Logic to enter and verify their LSTTL-based designs before constructing them thereby reducing hardware debugging time significantly. Still, the scope of student designs is limited by breadboard space and wiring complexity. The basic educational outcomes listed above have been augmented by the following enhanced outcomes: • completion of a large, team-based design project that requires use of hierarchical design and concurrent engineering methods; • experience in the use of an advanced CAD toolset; • working knowledge of a useful subset of the standard hardware description language, VHDL. Underlying the enhanced outcomes is the belief that tackling problems large enough to require teamwork develops new skills that will prove useful in advanced courses, senior design projects (e.g. in digital signal processing and robotics), and on the job. Moreover, successful large projects would instill pride and be seen as exciting and contemporary. Introduction This paper focuses on educational outcomes that have been achieved by introducing complex programmable logic devices (CPLD's) in the introductory digital design course at Trinity College. It describes the pedagogical approaches and CAD tools used to engage students in large-scale projects that require teamwork and concurrent engineering methods. The paper introduces the CPU221/97 design, a working four-bit "tiny" processor that was developed by a team of eight students during a three-week period in Fall, 1997. This introductory course, ENGR 221L, is taken primarily by sophomores pursuing concentrations in electrical or computer engineering. It also attracts computer science majors. ENGR 221L has three one-hour lectures and a three-hour laboratory session each week. The basic outcomes expected of students are: • a working knowledge of logic gates, flip-flops, synchronous sequential networks, and memory elements and their implementation in a standard logic family (LSTTL, primarily); • the ability to design digital circuitry using standard methods (e.g., K-maps, state transition diagrams); • the ability to use CAD tools for schematic capture and simulation; • the ability to build and debug hardware circuits; • familiarity with programmable logic devices (e.g. GAL22V10) and an associated hardware description language (ABEL or CUPL); • the ability to complete a term project working closely with other students; • the ability to write clear and complete documentation. Pedagogical Approach The keys to achieving the enhanced outcomes were twofold. First, the teaching of VHDL was integrated throughout the course. Whenever logic gates, MSI components, flip-flops, counters, and registers were introduced in class, students were given VHDL descriptions of them. These examples provided a basic knowledge of language structure and syntax and introduced a VHDL subset sufficient to develop CPLDbased designs. (This subset consists of the VHDL constructs: ENTITY, ARCHITECTURE, SIGNAL, TYPE, PORT, PROCESS, IF-THEN-ELSE, CASE..WHEN, WHEN...ELSE conditional assignment structure, and ‘EVENT.) Second, the laboratory provided a smooth bi-directional data bus interface. The problem required the development of a four-bit processor and associated EEPROM and RAM circuitry. In the next lab. 3) programming model showing CPU registers (accumulator A. The fifth lab design--a 4-bit adder/subtractor--was built first using LSTTL chips. took students through the basics of applying standard synthesis methods for combinational logic (K-Maps). shutter speed tester. The first four lab projects. and 4) to illustrate the application of a finite state machine as the Results In previous years. the assignment included project suggestions. the necessary register transfers at each microinstruction cycle of the CPU. 3) to introduce the concept of address and (bi-directional) data busses. and index register X). and serial ASCII interface. This transition was eased by the CAD toolset used in ENGR 221L: Altera's Max + Plus II. and the final project report was due on December 17.. digital stopwatch. temporary register B.) The planning matrix was the key instructional tool for this project. 2) to introduce memory interfacing. a pattern that they were expected to continue. simulated the overall system. and array summation program). and the timing of internal register transfers and data path multiplexer select signals. To attack final design projects. They added a BCDto-seven segment decoder developed in VHDL. In the next week's lab. and tested the programmed chip. A one-page project prospectus was due on November 24. subtraction program. using Beige Bag Software's B^Logic. suggested projects included a vending machine. for each machine instruction. Of the twelve enrolled students. In addition to the CPU design.g. students were able to tackle their final design projects using Max + Plus II and Altera CPLD's. This exercise paved the way for the CPU221/97 final design project. pairs could be combined to form larger teams. control element in a programmable system. Final Design Projects With the background provided by these exercises. From these VHDL exercises. From the matrix. 5) planning matrix where students recorded. address register MAR. The CPU project implicitly led students to achieve the enhanced outcomes. connected the modules together using the Max + Plus II graphic editor. students improved a skeletal design for an arithmetic logic unit (ALU) by increasing the word size and adding new logical operations. students entered the same design with the Max + Plus II graphic editor using LSTTL equivalent cells from the Altera library. Students had worked in pairs throughout the term. students developed a full understanding of the state transitions and data transfers necessary to execute each machine instruction. By completing it. calculator. as follows: 1) team leader (one student). 2) timing diagram showing the two-phase system clock.). and three teamed up to design a digital stopwatch.transition between designing with standard logic circuits and CPLD's. programmed the design into a single Altera EPM5032 device. Handed out four weeks before the end of the term. control unit states. students organized themselves instead by job category. but it encouraged students to develop their own ideas. Specific project goals included: 1) to introduce the stored program concept. (Assignment handouts are available from the author. addressing logic. Students were given a tutorial handout that included the following: 1) block diagram of the previous year's processor showing CPU sub-systems and their interconnections (ALU. status register SR. control unit including control logic and finite-state machine). which were carried out using LSTTL chips. Max + Plus II and VHDL became the preferred design tools for the rest of the semester. In 1997. program counter PC. 2) programming and hardware design (three Instruction Load A immediate Load A direct Load A indexed Add immediate Add indexed NAND indexed Store A direct Store A indexed NAND immediate Unused Load X immediate Load X direct Store X direct Update X Immediate Branch uncond’l Branch if zero Mnemonic LDAI LDAD LDAX ADDI ADDX NANDX STAD STAX NANDI * LDXI LDXD STXD UDXI BRA BEQ Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table I: Initial Instruction Set . and wiring and debugging circuits on a breadboard. teams divided the CPU into sub-systems and assigned design and verification of a sub-system to each pair of students. Similar projects had been completed by ENGR 221L students each year since 1994. students gained appreciation for the productivity increase that results from the use of VHDL and CPLD's. and 6) program examples (e. they were able to develop a Boolean expression for every data path select signal and register transfer enable signal in the CPU. 4) initial instruction set and op-code list (Table I below) (Students were encouraged to revise this set. As a result. one worked on the calculator. eight teamed up to work on the CPU. Then. • deletion of the STAX instruction in the initial design and addition of op-codes OUTI and OUTX.51 or higher and on HP. producing a clean circuit layout. The design experience provided in ENGR 221L has served as a springboard for independent study and senior design projects. the team could observe register transfers and state changes during the execution of each machine instruction. Appendix: Getting Started Altera CPLD technology and development tools are available from the Altera University Program. both contained in 84-pin PLCC packages. the equivalent of approximately 5000 logic gates. and programmer (one student). The MAX9320 and MAX7064 devices. (AHDL is the Altera Hardware Description Language. approach. An advantage of incorporating CPLD's in the introductory course is that students can . The design required 272 logic cells of the 320 available on the chip. the latter just in time for the holidays. in the space of three weeks. were interfaced to a standard breadboard using convenient PLCC-to-DIP adapters. the CPU221/97 design was programmed into an Altera MAX9320 84-pin CPLD. which can be contacted via the e-mail address university@altera. they developed a working knowledge of CPLD-based design and the use of VHDL as a means for describing and synthesizing digital systems. There are no charges to the school for software support and maintenance. register contents. The wiring group created a bank of LED's that displayed data and address bus activity.students). including CPU. The tone generator is a table-driven presettable downcounter that divides a 30kHz external clock to yield a twooctave musical scale. For example. 3) memory system. participating schools receive the University Program Design Laboratory Package. and IBM RISC 6000 UNIX machines.com o r on the Web at http://www. Enrollment in the University Program is straightforward and may be accomplished through the Web site. for example. Toronto. in CPU221/97’s machine language. the CPU221/97 processor from standard SSI and MSI components. In addition. Max + Plus II runs on appropriately-configured PCs equipped with Windows 95 or NT 3. complete. After this step. allowing the processor to access 256 locations--128 in ROM and 128 in RAM. was verified using Max + Plus II. ENGR 221L students were able quickly to design and implement a tone generator for CPU221/97 using VHDL. in short time frames. This success was made possible by the CAD tools. Each element of this tiny computer. The team made the following improvements to the initial design: • expansion of the address bus from 7 bits to 8 bits. Modern CAD tools and CPLD's encourage system-level thinking in the first course by enabling the completion of such large projects. Sun SPARC. the texts [4]-[7] have proved to Conclusion All ENGR 221L students achieved the basic outcomes of the course listed earlier in the paper. Altera provides clear documentation about Max + Plus II installation and operation [1] and very readable manuals on VHDL and AHDL [2].) In addition. Altera provides to member schools multiple copies of Max + Plus II software and documentation for PC's or workstations.) To demonstrate their system. which contains Max + Plus II Student Edition software and device programming hardware. The first programmed chip executed programs correctly. Altera is eager to receive course materials and student papers that may be shared with other University Program schools. and document large projects that require teamwork and concurrent engineering approaches. the programmers developed code. and machine states. The tools also encourage creativity. Reference [2] includes a number of excellent VHDL templates that have helped ENGR221L students to understand language syntax and structure. the modules were integrated using the graphic editor. and full verification was carried out at the system level. which enabled team-based design by supporting concurrent engineering of sub-systems and the hierarchical integration of these modules. chief simulator. especially in the application of digital design to robotics and DSP hardware development.altera. Almost all students who have taken ENGR 221L go on to take a more advanced course in digital electronics. and writing (three students). The success of this project and earlier CPU design projects in ENGR 221L has been a source of pride for students and has motivated the further study of digital electronics. [3]. They programmed a second Altera CPLD (type MAX7064) as a buffer to drive the LED monitors. external ROM and RAM. and several students have applied what they have learned about VHDL and CPLD’s in ENGR 221L to their senior design projects. wiring. By running the CPU at a slow clock rate.com. Altera donates software and CPLD chips to schools that offer courses in digital systems. (These adapters are available from Technological Arts. • design of a tone generator interfaced via a new CPU register sk and controlled by OUTI and OUTX. support for hardware description languages (VHDL and AHDL) and interfaces to other EDA tools. In addition. 4) librarian. it would be impractical for sophomores to build. and sound generator. to play "Mary Had a Little Lamb" and "Jingle Bells". San Jose. Michael Kornhauser. Addison Wesley. 1996. [2] Max+Plus II VHDL. [6] F. 1997. Morgan-Kaufman. San Jose. [4] K. San Jose. Sheldon Provost. Boston. and Customization. Prentice-Hall.VHDL for Programmable Logic. Ashenden. [3] Max+Plus II AHDL. References [1] Getting Started With Max+Plus II.be helpful references for both teacher and students. Patrick Hannon. Altera Corporation. Prototyping. 1997. 1996. VHDL and FPLDs in Digital Systems Design. and they are recommended by the author. Salcic. Altera Corporation. Acknowledgements The author thanks the Altera University Program for its generous support. Michael Lock. Altera Corporation. 1997. 1997. [5] Z. Scarpino. Nick Allen. Skahill. Steve Baker. VHDL and AHDL. [7] P. 1998. San Francisco. and Brian Jackson . The author also acknowledges the hard work of the CPU221/97 design team: Amir Tamrakar. The Designer’s Guide to VHDL. Kluwer.