39622L

PIC18F2XXX/4XXX FAMILYFlash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW This document includes the programming specifications for the following devices: • PIC18F2221 • PIC18F2321 • PIC18F2410 • PIC18F2420 • PIC18F2423 • PIC18F2450 • PIC18F2455 • PIC18F2458 • PIC18F2480 • PIC18F2510 • PIC18F2515 • PIC18F2520 • PIC18F2523 • PIC18F2525 • PIC18F2550 • PIC18F2553 • PIC18F2580 • PIC18F2585 • PIC18F2610 • PIC18F2620 • PIC18F2680 • PIC18F2682 • PIC18F2685 • PIC18F4221 • PIC18F4321 • PIC18F4410 • PIC18F4420 • PIC18F4423 • PIC18F4450 • PIC18F4455 • PIC18F4458 • PIC18F4480 • PIC18F4510 • PIC18F4515 • PIC18F4520 • PIC18F4523 • PIC18F4525 • PIC18F4550 • PIC18F4553 • PIC18F4580 • PIC18F4585 • PIC18F4610 • PIC18F4620 • PIC18F4680 • PIC18F4682 • PIC18F4685 ICSP method is slightly different than the high-voltage method and these differences are noted where applicable. This programming specification applies to the PIC18F2XXX/4XXX family devices in all package types. 2.1 Hardware Requirements In High-Voltage ICSP mode, PIC18F2XXX/4XXX family devices require two programmable power supplies: one for VDD and one for MCLR/VPP/RE3. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify Test Mode” for additional hardware parameters. 2.1.1 LOW-VOLTAGE ICSP PROGRAMMING 2.0 PROGRAMMING OVERVIEW PIC18F2XXX/4XXX family devices can be programmed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the low-voltage ICSP method. Both methods can be done with the device in the user’s system. The low-voltage In Low-Voltage ICSP mode, PIC18F2XXX/4XXX family devices can be programmed using a VDD source in the operating range. The MCLR/VPP/RE3 does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. Refer to Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify Test Mode” for additional hardware parameters. 2.2 Pin Diagrams The pin diagrams for the PIC18F2XXX/4XXX family are shown in Figure 2-1 and Figure 2-2. TABLE 2-1: Pin Name MCLR/VPP/RE3 VDD(2) VSS(2) RB5 RB6 RB7 Legend: Note 1: 2: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XXX/4XXX FAMILY During Programming Pin Name VPP VDD VSS PGM PGC PGD Pin Type P P P I I I/O Programming Enable Power Supply Ground Low-Voltage ICSP™ Input when LVP Configuration bit equals ‘1’(1) Serial Clock Serial Data Pin Description I = Input, O = Output, P = Power See Figure 5-1 for more information. All power supply (VDD) and ground (VSS) pins must be connected.  2010 Microchip Technology Inc. DS39622L-page 1 PIC18F2XXX/4XXX FAMILY FIGURE 2-1: PIC18F2XXX/4XXX FAMILY PIN DIAGRAMS 28-Pin SPDIP, PDIP, SOIC and SSOP The following devices are included in 28-pin SPDIP, PDIP and SOIC parts: • PIC18F2221 • PIC18F2321 • PIC18F2410 • PIC18F2420 • PIC18F2423 • PIC18F2450 • PIC18F2455 • PIC18F2458 • PIC18F2480 • PIC18F2510 • PIC18F2515 • PIC18F2520 MCLR/VPP/RE3 RB7/PGD RB6/PGC RB5/PGM RB4 • PIC18F2523 • PIC18F2525 • PIC18F2550 • PIC18F2553 • PIC18F2580 • PIC18F2585 • PIC18F2610 • PIC18F2620 • PIC18F2680 • PIC18F2682 • PIC18F2685 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS OSC1 OSC2 RC0 RC1 RC2 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 The following devices are included in 28-pin SSOP parts: • PIC18F2221 • PIC18F2321 RA1 RA0 28-Pin QFN The following devices are included in 28-pin QFN parts: • PIC18F2221 • PIC18F2321 • PIC18F2410 • PIC18F2420 • PIC18F2423 • PIC18F2450 • PIC18F2480 RC0 RC1 RC2 RC3 RC4 RC5 RC6 28 27 26 25 24 23 22 RA2 RA3 RA4 RA5 VSS OSC1 OSC2 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 • PIC18F2510 • PIC18F2520 • PIC18F2523 • PIC18F2580 • PIC18F2682 • PIC18F2685 PIC18F2XXX 8 9 10 11 12 13 14 40-Pin PDIP The following devices are included in 40-pin PDIP parts: • PIC18F4221 • PIC18F4321 • PIC18F4410 • PIC18F4420 • PIC18F4423 • PIC18F4450 • PIC18F4455 • PIC18F4458 • PIC18F4480 • PIC18F4510 • PIC18F4515 • PIC18F4520 • PIC18F4523 • PIC18F4525 • PIC18F4550 • PIC18F4553 • PIC18F4580 • PIC18F4585 • PIC18F4610 • PIC18F4620 • PIC18F4680 • PIC18F4682 • PIC18F4685 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS OSC1 OSC2 RC0 RC1 RC2 RC3 RD0 RD1 PIC18F2XXX 1 2 3 4 5 6 7 40 39 38 37 36 35 34 8 9 10 11 12 13 14 15 16 17 18 19 20 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 PIC18F4XXX DS39622L-page 2  2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY FIGURE 2-2: PIC18F2XXX/4XXX FAMILY PIN DIAGRAMS RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC(1)/ICPORTS 44 43 42 41 40 39 38 37 36 35 34 44-Pin TQFP The following devices are included in 40-pin TQFP parts: • PIC18F4221 • PIC18F4321 • PIC18F4410 • PIC18F4420 • PIC18F4423 • PIC18F4450 • PIC18F4455 • PIC18F4458 • PIC18F4480 • PIC18F4510 • PIC18F4520 • PIC18F4515 Note 1: These pins are NC (No Connect) for all devices listed above with the exception of the PIC18F4450, PIC18F4455, PIC18F4458 and the PIC18F4553 devices (see Section 2.8 “Dedicated ICSP/ICD Port (44-Pin TQFP Only)” for more information on programming these pins in these devices). • PIC18F4523 • PIC18F4525 • PIC18F4550 • PIC18F4553 • PIC18F4580 • PIC18F4585 • PIC18F4610 • PIC18F4620 • PIC18F4680 • PIC18F4682 • PIC18F4685 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 PIC18F4XXX 44-Pin QFN The following devices are included in 44-pin QFN parts: • PIC18F4221 • PIC18F4321 • PIC18F4410 • PIC18F4420 • PIC18F4423 • PIC18F4450 • PIC18F4455 • PIC18F4458 • PIC18F4480 • PIC18F4510 • PIC18F4520 • PIC18F4515 • PIC18F4523 • PIC18F4525 • PIC18F4550 • PIC18F4553 • PIC18F4580 • PIC18F4585 • PIC18F4610 • PIC18F4620 • PIC18F4680 • PIC18F4682 • PIC18F4685 RC7 RD4 RD5 RD6 RD7 VSS AVDD VDD RB0 RB1 RB2 44 43 42 41 40 39 38 37 36 35 34 RC6 D+/VP D-/VM RD3 RD2 RD1 RD0 VUSB RC2 RC1 RC0 NC(1)/ICPGC NC(1)/ICPGD RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0 RA1 RA2 RA3 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 NC(1)/ICVPP RC0 OSC2 OSC1 VSS VDD RE2 RE1 RE0 RA5 RA4  2010 Microchip Technology Inc. RB3 NC RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0 RA1 RA2 RA3 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 PIC18F4XXX 33 32 31 30 29 28 27 26 25 24 23 OSC2 OSC1 VSS AVSS VDD AVDD RE2 RE1 RE0 RA5 RA4 DS39622L-page 3 PIC18F2XXX/4XXX FAMILY 2.3 Memory Maps TABLE 2-2: Device PIC18F2515 PIC18F2525 PIC18F2585 PIC18F4515 PIC18F4525 PIC18F4585 PIC18F2610 PIC18F2620 PIC18F2680 PIC18F4610 PIC18F4620 PIC18F4680 000000h-00FFFFh (64K) 000000h-00BFFFh (48K) For PIC18FX6X0 devices, the code memory space extends from 0000h to 0FFFFh (64 Kbytes) in four 16-Kbyte blocks. For PIC18FX5X5 devices, the code memory space extends from 0000h to 0BFFFFh (48 Kbytes) in three 16-Kbyte blocks. Addresses, 0000h through 07FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. The size of the Boot Block in PIC18F2585/2680/4585/ 4680 devices can be configured as 1, 2 or 4K words (see Figure 2-3). This is done through the BBSIZ<1:0> bits in the Configuration register, CONFIG4L. It is important to note that increasing the size of the Boot Block decreases the size of Block 0. IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) FIGURE 2-3: 000000h MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX5X5/X6X0 DEVICES MEMORY SIZE/DEVICE Address Range Code Memory 01FFFFh 64 Kbytes (PIC18FX6X0) BBSIZ<1:0> 11/10 01 Boot Block* 00 Boot Block* Boot Block* 11/10 48 Kbytes (PIC18FX5X5) 01 00 Boot Block* 000000h 0007FFh 000800h 000FFFh 001000h Block 0 001FFFh 002000h Unimplemented Read as ‘0’ Boot Block* Boot Block* Block 0 200000h Block 0 Block 0 Block 0 Block 0 003FFFh 004000h Block 1 Configuration and ID Space Block 1 007FFFh 008000h Block 2 Block 2 00BFFFh 00C000h Block 3 Unimplemented Reads all ‘0’s 3FFFFFh Note: * Unimplemented Reads all ‘0’s 00FFFFh 01FFFFh Sizes of memory areas are not to scale. Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register. DS39622L-page 4  2010 Microchip Technology Inc. The size of the Boot Block in PIC18F2685/4685 and PIC18F2682/4682 devices can be configured as 1. define a “Boot Block” region that is treated separately from Block 0. TABLE 2-3: Device PIC18F2682 PIC18F4682 PIC18F2685 PIC18F4685 IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) 000000h-013FFFh (80K) 000000h-017FFFh (96K) FIGURE 2-4: MEMORY MAP AND THE CODE MEMORY SPACE  FOR PIC18F2685/4685 AND PIC18F2682/4682 DEVICES MEMORY SIZE/DEVICE Address Range 000000h Code Memory 01FFFFh 96 Kbytes (PIC18F2685/4685) BBSIZ1:BBSIZ2 11/10 01 Boot Block* 00 Boot Block* Boot Block* 11/10 80 Kbytes (PIC18F2682/4682) 01 00 Boot Block* 000000h 0007FFh 000800h 000FFFh 001000h Block 0 001FFFh 002000h Unimplemented Read as ‘0’ Boot Block* Boot Block* Block 0 Block 0 Block 0 Block 0 Block 0 200000h Block 1 Block 1 003FFFh 004000h 007FFFh 008000h Block 2 Block 2 00BFFFh 00C000h Block 3 Block 3 00FFFFh 010000h Block 4 Block 4 013FFFh 014000h Block 5 Unimplemented Reads all ‘0’s 017FFFh Configuration and ID Space 3FFFFFh Note: * Unimplemented Reads all ‘0’s 01FFFFh Sizes of memory areas are not to scale. All of these blocks define code protection boundaries within the code memory space. This is done through the BBSIZ<2:1> bits in the Configuration register. Addresses. DS39622L-page 5 . however. 2 or 4K words (see Figure 2-4). Boot Block size is determined by the BBSIZ<1:2> bits in the CONFIG4L register. the code memory space extends from 0000h to 0013FFFh (80 Kbytes) in four 16-Kbyte blocks. 0000h through 0FFFh. It is important to note that increasing the size of the Boot Block decreases the size of Block 0. For PIC18F2682/4682 devices. the code memory space extends from 0000h to 017FFFh (96 Kbytes) in five 16-Kbyte blocks.  2010 Microchip Technology Inc. CONFIG4L.PIC18F2XXX/4XXX FAMILY For PIC18F2685/4685 devices. For PIC18FX4X5/X4X8 devices. the code memory space extends from 000000h to 007FFFh (32 Kbytes) in four 8-Kbyte blocks. define a “Boot Block” region that is treated separately from Block 0. the code memory space extends from 000000h to 005FFFh (24 Kbytes) in three 8-Kbyte blocks. however.PIC18F2XXX/4XXX FAMILY For PIC18FX5X0/X5X3 devices. 000000h through 0007FFh. TABLE 2-4: Device PIC18F2455 PIC18F2458 PIC18F4455 PIC18F4458 PIC18F2510 PIC18F2520 PIC18F2523 PIC18F2550 PIC18F2553 PIC18F4510 PIC18F4520 PIC18F4523 PIC18F4550 PIC18F4553 IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) 000000h-005FFFh (24K) 000000h-007FFFh (32K) FIGURE 2-5: 000000h MEMORY MAP AND THE CODE MEMORY SPACE  FOR PIC18FX4X5/X4X8/X5X0/X5X3 DEVICES Code Memory 1FFFFFh MEMORY SIZE/DEVICE 32 Kbytes (PIC18FX5X0/X5X3) Boot Block Unimplemented Read as ‘0’ Block 0 24 Kbytes (PIC18FX4X5/X4X8) Boot Block Block 0 Address Range 000000h 0007FFh 000800h 001FFFh 002000h Block 1 Block 1 003FFFh 004000h Block 2 Block 2 005FFFh 006000h Block 3 007FFFh 008000h 200000h Configuration and ID Space Unimplemented Reads all ‘0’s Unimplemented Reads all ‘0’s 1FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. DS39622L-page 6  2010 Microchip Technology Inc. . Addresses. All of these blocks define code protection boundaries within the code memory space. PIC18F2XXX/4XXX FAMILY For PIC18FX4X0/X4X3 devices. TABLE 2-5: Device PIC18F2410 PIC18F2420 PIC18F2423 PIC18F2450 PIC18F4410 PIC18F4420 PIC18F4450 IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) 000000h-003FFFh (16K) FIGURE 2-6: MEMORY MAP AND THE CODE MEMORY SPACE  FOR PIC18FX4X0/X4X3 DEVICES 000000h Code Memory 1FFFFFh MEMORY SIZE/ DEVICE 16 Kbytes Address (PIC18FX4X0/X4X3) Range Boot Block Unimplemented Read as ‘0’ Block 0 000000h 0007FFh 000800h 001FFFh 002000h Block 1 003FFFh 004000h 200000h 005FFFh 006000h 008000h 007FFFh Configuration and ID Space Unimplemented Reads all ‘0’s 1FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. however. All of these blocks define code protection boundaries within the code memory space. the code memory space extends from 000000h to 003FFFh (16 Kbytes) in two 8-Kbyte blocks. 000000h through 0003FFh. Addresses.  2010 Microchip Technology Inc. DS39622L-page 7 . define a “Boot Block” region that is treated separately from Block 0. Addresses.PIC18F2XXX/4XXX FAMILY For PIC18F2480/4480 devices. however. 0000h through 07FFh. For PIC18F2580/4580 devices. Boot Block size is determined by the BBSIZ<0> bit in the CONFIG4L register. It is important to note that increasing the size of the Boot Block decreases the size of Block 0. . the code memory space extends from 0000h to 07FFFh (32 Kbytes) in two 16-Kbyte blocks. CONFIG4L. TABLE 2-6: Device PIC18F2480 PIC18F4480 PIC18F2580 PIC18F4580 IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) 000000h-003FFFh (16K) 000000h-007FFFh (32K) FIGURE 2-7: 000000h MEMORY MAP AND THE CODE MEMORY SPACE  FOR PIC18F2480/2580/4480/4580 DEVICES Code Memory MEMORY SIZE/DEVICE 32 Kbytes (PIC18FX580) BBSIZ<0> 1 0 Boot Block* Boot Block* Boot Block* 1 0 Boot Block* 000000h 0007FFh 000800h 000FFFh 001000h Block 0 Block 0 001FFFh 002000h Block 1 003FFFh 004000h Block 2 005FFFh 006000h Block 3 Unimplemented Reads all ‘0’s 007FFFh 16 Kbytes (PIC18FX480) Address Range 01FFFFh Unimplemented Read as ‘0’ Block 0 Block 0 200000h Configuration and ID Space 3FFFFFh Unimplemented Reads all ‘0’s 01FFFFh Note: * Sizes of memory areas are not to scale. This is done through the BBSIZ<0> bit in the Configuration register. The size of the Boot Block in PIC18F2480/2580/4480/ 4580 devices can be configured as 1 or 2K words (see Figure 2-7). All of these blocks define code protection boundaries within the code memory space. DS39622L-page 8  2010 Microchip Technology Inc. the code memory space extends from 0000h to 03FFFh (16 Kbytes) in one 16-Kbyte block. define a “Boot Block” region that is treated separately from Block 0. TABLE 2-7: Device PIC18F2221 PIC18F4221 PIC18F2321 PIC18F4321 IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) 000000h-000FFFh (4K) 000000h-001FFFh (8K) FIGURE 2-8: MEMORY MAP AND THE CODE MEMORY SPACE  FOR PIC18F2221/2321/4221/4321 DEVICES MEMORY SIZE/DEVICE Address Range 4 Kbytes (PIC18FX221) BBSIZ<1:0> 11/10 01 00 Boot Block* 256 words 11/10/01 00 Boot Block* 256 words 000000h 0001FFh 000200h 0003FFh 000400h 000000h Code Memory 01FFFFh 8 Kbytes (PIC18FX321) Unimplemented Read as ‘0’ Boot Block* 512 words Boot Block* 1K word Boot Block* 512 words Block 0 0.5K words 200000h Block 0 1K word Block 1 1K word 000FFFh 001000h Configuration and ID Space Block 1 2K words Unimplemented Reads all ‘0’s 3FFFFFh Unimplemented Reads all ‘0’s 001FFFh 002000h 1FFFFFh Note: * Sizes of memory areas are not to scale.75K words 0007FFh 000800h Block 0 1. Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register. 512 or 1024 words (see Figure 2-8). DS39622L-page 9 . It is important to note that increasing the size of the Boot Block decreases the size of Block 0. This is done through the BBSIZ<1:0> bits in the Configuration register. Addresses. 0000h through 07FFh. the code memory space extends from 0000h to 01FFFh (8 Kbytes) in two 4-Kbyte blocks. the code memory space extends from 0000h to 00FFFh (4 Kbytes) in one 4-Kbyte block.PIC18F2XXX/4XXX FAMILY For PIC18F2221/4221 devices. define a variable “Boot Block” region that is treated separately from Block 0.5K words Block 0 1.  2010 Microchip Technology Inc. CONFIG4L (see Figure 2-8). All of these blocks define code protection boundaries within the code memory space. For PIC18F2321/4321 devices.75K words Block 0 0. however. The size of the Boot Block in PIC18F2221/2321/4221/ 4321 devices can be configured as 256. The ID locations read out normally. These bits select various device options and are described in Section 5. These Configuration bits read out normally. 2. Their locations in the memory map are shown in Figure 2-9. even after code protection is applied. 0000000h to 3FFFFFh. 3FFFFEh 3FFFFFh DS39622L-page 10  2010 Microchip Technology Inc.PIC18F2XXX/4XXX FAMILY In addition to the code memory space.3.0 “Configuration Word”. Locations.1 MEMORY ADDRESS POINTER Memory in the address space. These ID registers are mapped in addresses. are reserved for the Device ID bits. 300000h through 30000Dh. 3FFFFEh and 3FFFFFh. are reserved for the Configuration bits. is addressed via the Table Pointer register. even after code protection. These Device ID bits read out normally. FIGURE 2-9: 000000h CONFIGURATION AND ID LOCATIONS FOR PIC18F2XXX/4XXX FAMILY DEVICES Code Memory 01FFFFh ID Location 1 ID Location 2 ID Location 3 ID Location 4 ID Location 5 ID Location 6 ID Location 7 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h Unimplemented Read as ‘0’ ID Location 8 CONFIG1L CONFIG1H CONFIG2L CONFIG2H 1FFFFFh CONFIG3L CONFIG3H CONFIG4L Configuration and ID Space CONFIG4H CONFIG5L CONFIG5H CONFIG6L 2FFFFFh CONFIG6H CONFIG7L CONFIG7H 300000h 300001h 300002h 300003h 300004h 300005h 300006h 300007h 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh Device ID1 Device ID2 3FFFFFh Note: Sizes of memory areas are not to scale. which is comprised of three pointer registers: • TBLPTRU at RAM address 0FF8h • TBLPTRH at RAM address 0FF7h • TBLPTRL at RAM address 0FF6h TBLPTRU Addr[21:16] TBLPTRH Addr[15:8] TBLPTRL Addr[7:0] The 4-bit command. ‘0000’ (core instruction). is used to load the Table Pointer prior to using many read or write operations. Locations.0 “Configuration Word”. Users may store identification information (ID) in eight ID registers. These bits may be used by the programmer to identify what device type is being programmed and are described in Section 5. . 200000h through 200007h. even after code protection. there are three blocks that are accessible to the user through Table Reads and Table Writes. the Configuration bits are then programmed and verified.3 “Data EEPROM Programming”).3 “Data EEPROM Programming”).3 “Data EEPROM Programming”. ID locations and Configuration bits can be accessed and programmed in serial fashion. ID locations and data EEPROM are programmed (selected devices only. As shown in Figure 2-11.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode Figure 2-10 shows the high-level overview of the programming process. Figure 2-12 shows the exit sequence. First. data EEPROM (selected devices only. Once in this mode. The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. the code memory. see Section 3. If no errors are detected. DS39622L-page 11 . FIGURE 2-10: HIGH-LEVEL PROGRAMMING FLOW Start FIGURE 2-11: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P1 P12 Perform Bulk Erase Program Memory D110 MCLR/VPP/RE3 Program IDs VDD PGD Program Data EE(1) PGC PGD = Input Verify Program Verify IDs FIGURE 2-12: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE P16 P17 Verify Data MCLR/VPP/RE3 Program Configuration Bits D110 VDD Verify Configuration Bits Done Note 1: Selected devices only. Next. PGD PGC P1 PGD = Input  2010 Microchip Technology Inc. see Section 3. These memories are then verified to ensure that programming was successful. the code memory. see Section 3.4 High-Level Overview of the Programming Process 2.PIC18F2XXX/4XXX FAMILY 2. a Bulk Erase is performed. the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/VPP/RE3 to VIHH (high voltage). 3 “Single-Supply ICSP Programming”). Low-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low. Pre-Increment Table Write Table Write.6 Entering and Exiting Low-Voltage ICSP Program/Verify Mode 2. the Low-Voltage ICSP mode is enabled. TABLE 2-8: COMMANDS FOR PROGRAMMING Description 4-Bit Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 FIGURE 2-14: EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE P16 P18 VIH Core Instruction (Shift in16-bit instruction) Shift Out TABLAT Register Table Read Table Read. Post-Decrement MCLR/VPP/RE3 VDD Table Read.2 CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution.  Post-Increment by 2 Table Write. The commands needed for programming and verification are shown in Table 2-8. placing a logic high on PGM and then raising MCLR/VPP/RE3 to VIH. Throughout this specification. the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. consisting of a leading 4-bit command followed by a 16-bit operand. As shown in Figure 2-13. Start Programming TABLE 2-9: 4-Bit Command 1101 SAMPLE COMMAND SEQUENCE Data Payload 3C 40 Core Instruction Table Write.7 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation.  post-increment by 2 DS39622L-page 12  2010 Microchip Technology Inc. To input a command. Start Programming. or “Data Payload”.7. the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. commands and data are presented as illustrated in Table 2-9. Post-Increment Table Read. PGC is cycled four times.1 4-BIT COMMANDS All instructions are 20 bits. This is needed to set up registers as appropriate for use with other commands. Figure 2-14 shows the exit sequence. In this mode. 2. which depends on the type of command being executed. The 4-bit command is shown Most Significant bit (MSb) first.PIC18F2XXX/4XXX FAMILY 2. When the LVP Configuration bit is ‘1’ (see Section 5. FIGURE 2-13: ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE P15 VIH P12 MCLR/VPP/RE3 VDD VIH PGM PGD PGC PGD = Input 2. .7. The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. Figure 2-15 demonstrates how to serially present a 20-bit command/operand to the device. Post-Increment by 2 VIH PGM PGD PGC PGD = Input Table Write. Commands and data are transmitted on the rising edge of PGC. The command operand. Depending on the 4-bit command. latched on the falling edge of PGC and are Least Significant bit (LSb) first. is shown as <MSB><LSB>. In conjunction with ICD capability. When the VIH is seen on the MCLR/VPP/RE3 pin prior to applying VIH to the ICRST/ICVPP pin. Setting the ICPRT Configuration bit enables the dedicated ICSP/ICD port. alternate pins are used instead of the default pins. unexpected operation may occur. otherwise. Note: The ICPRT Configuration bit can only be programmed through the default ICSP port. Chip Erase functions through the dedicated ICSP/ICD port do not affect this bit. however. however. ICSP is still available through the default port even though the ICPRT Configuration bit is set. POST-INCREMENT TIMING (1101) P2A P2B 1 P5 P4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P5A 1 2 3 4 PGC P3 PGD 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 3 0 0 n n n n 4-Bit Command 4 C 16-Bit Data Payload Fetch Next 4-Bit Command PGD = Input 2. when the VIH is seen on ICRST/ICVPP prior to applying VIH to MCLR/ VPP/RE3. then the state of the ICRST/ICVPP pin is ignored.PIC18F2XXX/4XXX FAMILY FIGURE 2-15: P2 1 2 3 4 TABLE WRITE. P = Power  2010 Microchip Technology Inc. the NC/ICPORTS pin must be tied to either VDD or VSS. The dedicated ICSP/ICD port functions the same as the default ICSP/ICD port. The primary purpose of this port is to provide an alternate In-Circuit Debugging (ICD) option and free the pins (RB6.8 Dedicated ICSP/ICD Port  (44-Pin TQFP Only) The PIC18F4455/4458/4550/4553 44-pin TQFP devices are designed to support an alternate programming input: the dedicated ICSP/ICD port. O = Output. TABLE 2-10: Pin Name ICSP™ EQUIVALENT PINS During Programming Pin Name Pin Type P I I/O Dedicated Pins NC/ICRST/ICVPP NC/ICCK/ICPGC NC/ICDT/ICPGD Pin Description Programming Enable Serial Clock Serial Data MCLR/VPP/RE3 RB6 RB7 VPP PGC PGD Legend: I = Input. the dedicated ICSP/ICD port also provides an alternate port for ICSP. When the ICPRT Configuration bit is set (dedicated ICSP/ICD port enabled). Table 2-10 identifies the functionally equivalent pins for ICSP purposes: The dedicated ICSP/ICD port is an alternate port. then the state of the MCLR/VPP/RE3 pin is ignored. RB7 and MCLR) that would normally be used for debugging the application. DS39622L-page 13 . The ICPRT Configuration bit must be maintained clear for all 28-pin and 40-pin devices. Likewise. Thus. . Erase options are detailed in Table 3-1. NOP Hold PGD low until erase completes.g. the user must request an erase of data EEPROM (e. The code sequence to erase the entire device is shown in Table 3-2 and the flowchart is shown in Figure 3-1. TABLE 3-2: BULK ERASE COMMAND SEQUENCE Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 05h MOVWF TBLPTRL Write 3F3Fh to 3C0005h MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 8F8Fh TO 3C0004h to erase entire device. If data EEPROM is code-protected (CPD = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e. Bulk Erase operations will also clear any code-protect settings associated with the memory block being erased.1 ICSP Erase HIGH-VOLTAGE ICSP BULK ERASE Erasing code or data EEPROM is accomplished by configuring two Bulk Erase Control registers located at 3C0004h and 3C0005h. the EECON1 register must be configured in order to operate on a particular memory region. When using the EECON1 register to act on code memory. The FREE bit must be set (EECON1<4> = 1) in order to erase the program space being pointed to by the Table Pointer. except high-voltage ICSP Bulk Erase. serial execution will cease until the erase completes (Parameter P11).PIC18F2XXX/4XXX FAMILY 3. 4-Bit Data Command Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 3F 0E 6E 0E 6E 0E 6E 8F 3C F8 00 F7 05 F6 3F 3C F8 00 F7 04 F6 8F 3. Delay P11 + P10 Time Done DS39622L-page 14  2010 Microchip Technology Inc.1. the EEPGD bit must be set (EECON1<7> = 1) and the CFGS bit must be cleared (EECON1<6> = 0). It is strongly recommended that the WREN bit only be set immediately prior to a program erase. or the user may erase the entire device in one action. The actual Bulk Erase function is a self-timed operation.1 3.g. see Section 3. Once the erase has started (falling edge of the 4th PGC after the NOP command). .0 DEVICE PROGRAMMING Programming includes the ability to erase or write the various memory regions within the device. In all cases. erases) and this must be done prior to initiating a write sequence.3 “Data EEPROM Programming”. Code memory may be erased.. Note: A Bulk Erase is the only way to reprogram code-protect bits from an ON state to an OFF state. portions at a time. TABLE 3-1: BULK ERASE OPTIONS Data (3C0005h:3C0004h) 3F8Fh 0084h 0081h 0082h 0180h 0280h 0480h 0880h 1080h 2080h 0000 0000 00 00 00 00 Description Chip Erase Erase Data EEPROM(1) Erase Boot Block Erase Configuration Bits Erase Code EEPROM Block 0 Erase Code EEPROM Block 1 Erase Code EEPROM Block 2 Erase Code EEPROM Block 3 Erase Code EEPROM Block 4 Erase Code EEPROM Block 5 Note 1: FIGURE 3-1: BULK ERASE FLOW Start Write 3F3Fh to 3C0005h Write 8F8Fh to 3C0004h to Erase Entire Device Selected devices only. During this time. 0084h as shown in Table 3-1). PGC may continue to toggle but PGD must be held low. The erase or write sequence is initiated by setting the WR bit (EECON1<1> = 1). it is possible to erase one row (64 bytes of data). After PGC is brought low.3 “Data EEPROM Programming”) must be performed at a supply voltage below the Bulk Erase limit.1. PGC must be held low for the time specified by Parameter P10 to allow high-voltage discharge of the memory array.3 ICSP ROW ERASE Regardless of whether high or low-voltage ICSP is used.  2010 Microchip Technology Inc. The code sequence to Row Erase a PIC18F2XXX/ 4XXX family device is shown in Table 3-3. apply. 000000h. shown in Figure 3-3. a NOP is issued.1 “Modifying Code Memory”. Note: The TBLPTR register can point to any byte within the row intended for erase. the part must be supplied by the voltage specified in Parameter D111 if a Bulk Erase is to be executed.3 “Data EEPROM Programming” and write ‘1’s to the array.2 LOW-VOLTAGE ICSP BULK ERASE When using low-voltage ICSP. beginning at program memory address.1. After the WR bit in EECON1 is set. provided the block is not code or write-protected. where the 4th PGC is held high for the duration of the programming time. follow the methodology described in Section 3. see Section 3.PIC18F2XXX/4XXX FAMILY 3. The flowchart. FIGURE 3-2: BULK ERASE TIMING P10 1 2 3 4 1 2 15 16 P5A 1 2 3 4 1 2 15 16 P5A 1 2 3 4 1 2 PGC P5 P5 P11 PGD 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Erase Time n n 4-Bit Command 16-Bit Data Payload 4-Bit Command 16-Bit Data Payload 4-Bit Command 16-Bit Data Payload PGD = Input 3. as described above. If it is determined that a data EEPROM erase (selected devices only. extending to the internal program memory limit (see Section 2.3 “ICSP Row Erase” and Section 3.1. the programming sequence is terminated. The timing diagram that details the Start Programming command and Parameters P9 and P10 is shown in Figure 3-5. The Row Erase duration is externally timed and is controlled by PGC. All other Bulk Erase details. DS39622L-page 15 . depicts the logic necessary to completely erase a PIC18F2XXX/4XXX family device. If it is determined that a program memory erase must be performed at a supply voltage below the Bulk Erase limit. refer to the erase methodology described in Section 3. Rows are located at static boundaries.3 “Memory Maps”).2. P9. FREE BSF EECON1. WR NOP – hold PGC high for time P9 and low for time P10. FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Start Addr = 0 Configure Device for Row Erases Start Erase Sequence and Hold PGC High for Time P9 Addr = Addr + 64 Hold PGC Low for Time P10 No All rows done? Yes Done DS39622L-page 16  2010 Microchip Technology Inc. with the Address Pointer incremented by 64 until all rows are erased. CFGS EECON1. 0000 0000 0000 88 A6 82 A6 00 00 BSF EECON1. Step 4: Repeat Step 3. WREN Step 2: Point to first row in code memory.PIC18F2XXX/4XXX FAMILY TABLE 3-3: 4-Bit Command ERASE CODE MEMORY CODE SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 0000 8E A6 9C A6 84 A6 BSF BCF BSF EECON1. 0000 0000 0000 6A F8 6A F7 6A F6 CLRF CLRF CLRF TBLPTRU TBLPTRH TBLPTRL Step 3: Enable erase and erase single row. . EEPGD EECON1. PIC18F4515. PIC18F4458. NOP . PIC18F4550 PIC18F2458. where the 4th PGC is held high for the duration of the programming time. The actual memory write sequence takes the contents of this buffer and programs the proper amount of code memory that contains the Table Pointer. where the Address Pointer is incremented by 2 at each iteration of the loop.hold PGC high for time P9 and low for time P10. EEPGD EECON1. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 3: Repeat for all but the last two bytes. PIC18F4585. Note: The TBLPTR register must point to the same region when initiating the programming sequence as it did when the write buffers were loaded. CFGS Step 2: Load write buffer. PIC18F4450 PIC18F2410. Step 4: Load write buffer for last two bytes. PIC18F2580.2 Code Memory Programming Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. PIC18F4423. To continue writing data. The write and erase buffer sizes. ‘1111’). PIC18F4580 PIC18F2455. PIC18F4510 PIC18F2420. PIC18F4525. 1111 0000 <MSB><LSB> 00 00 Write 2 bytes and start programming. depicts the logic necessary to completely write a PIC18F2XXX/4XXX family device. PIC18F4610 PIC18F2525. PIC18F2610. PIC18F4682. PIC18F4455. PIC18F4680 PIC18F2682. PIC18F2321. PIC18F4480. PIC18F2520. DS39622L-page 17 . PIC18F2510. PIC18F2550. After PGC is brought low. PGC must be held low for the time specified by Parameter P10 to allow high-voltage discharge of the memory array. beginning at 000000h. shown in Figure 3-4. The timing diagram that details the Start Programming command and Parameters P9 and P10 is shown in Figure 3-5. PIC18F2523.PIC18F2XXX/4XXX FAMILY 3. After a Start Programming command is issued (4-bit command. TABLE 3-4: WRITE AND ERASE BUFFER SIZES Devices (Arranged by Family) Write Buffer Size (Bytes) 8 16 Erase Buffer Size (Bytes) 64 64 PIC18F2221. PIC18F4520 PIC18F2423. PIC18F4523 PIC18F2480. The code sequence to program a PIC18F2XXX/4XXX family device is shown in Table 3-5. shown in Table 3-4. PIC18F4620 PIC18F2585. PIC18F4553 PIC18F2515. The programming duration is externally timed and is controlled by PGC. repeat Steps 2 through 4. a NOP is issued. 0000 0000 8E A6 9C A6 BSF BCF EECON1. PIC18F2620. PIC18F4410. the programming sequence is terminated. PIC18F2553. PIC18F4420. PIC18F2680. PIC18F4221. PIC18F2685. PIC18F4321 PIC18F2450. P9. can be mapped to any location of the same size. 1101 <MSB><LSB> Write 2 bytes and post-increment address by 2. PIC18F4685 32 64 64 64 TABLE 3-5: 4-Bit Command WRITE CODE MEMORY CODE SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. The flowchart.  2010 Microchip Technology Inc. .PIC18F2XXX/4XXX FAMILY FIGURE 3-4: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes N=N+1 Load 2 Bytes to Write Buffer at <Addr> No All bytes written? Yes Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 N=1 LoopCount = LoopCount + 1 No All locations done? Yes Done FIGURE 3-5: 1 2 3 TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) P10 4 P5 1 2 3 4 5 6 15 16 P5A 1 2 3 P9 4 1 2 3 PGC PGD 1 1 1 1 n n n n n n n n 0 0 0 0 Programming Time 0 0 0 4-Bit Command 16-Bit Data Payload 4-Bit Command 16-Bit Data Payload PGD = Input DS39622L-page 18  2010 Microchip Technology Inc. 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[8:15]> 6E F7 0E <Addr[7:0]> 6E F6 <MSB><LSB> . <MSB><LSB> 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write 2 <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL bytes and post-increment address by 2. . EEPGD EECON1. the block of code memory that was read out must be erased and rewritten with the modified data. Then. NOP . TABLE 3-6: 4-Bit Command MODIFYING CODE MEMORY Data Payload Core Instruction Step 1: Direct access to code memory. Modifications can be made on this buffer. Step 6: Load write buffer.hold PGC high for time P9 and low for time P10. The correct bytes will be selected based on the Table Pointer.PIC18F2XXX/4XXX FAMILY 3.2. ID Locations and Configuration Bits”). Step 2: Read and modify code memory (see Section 4. .1 “Read Code Memory. .1 “High-Voltage ICSP Bulk Erase”). Repeat as many times as necessary to fill the write buffer Write 2 bytes and start programming. FREE Step 5: Initiate erase. DS39622L-page 19 .hold PGC high for time P9 and low for time P10. WREN EECON1. CFGS Step 3: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 1101 . . WR NOP . 0000 0000 8E A6 9C A6 BSF BCF EECON1. 0000 94 A6 BCF EECON1. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[8:15]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL Step 4: Enable memory writes and set up an erase. The WREN bit must be set if the WR bit in EECON1 is used to initiate a write sequence. WREN  2010 Microchip Technology Inc. that the user wishes to modify only a section of an already programmed device.2 “Verify Code Memory and ID Locations”) and buffered. 0000 0000 84 A6 88 A6 BSF BSF EECON1. where the Address Pointer is incremented by the appropriate number of bytes (see Table 3-4) at each iteration of the loop. 0000 0000 82 A6 00 00 BSF EECON1.1 MODIFYING CODE MEMORY The previous programming example assumed that the device had been Bulk Erased prior to programming (see Section 3. however. Step 7: Disable writes. It may be the case. repeat Steps 2 through 6.1. The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4. To continue modifying data. Data EEPROM is written by loading EEADRH:EEADR with the desired memory location. PGC must still be held low for the time specified by Parameter P10 to allow high-voltage discharge of the memory array. both the EEPGD and CFGS bits must be cleared (EECON1<7:6> = 00). Set Data Enable Write Start Write Sequence WR bit clear? Yes No Done? Yes Done No FIGURE 3-7: 1 2 3 4 DATA EEPROM WRITE TIMING P10 1 2 15 16 P5A P11A n BSF EECON1.3 Note: Data EEPROM Programming Data EEPROM programming is not available on the the following devices: PIC18F4410 PIC18F4450 PIC18F4510 PIC18F4515 PIC18F4610 After the programming sequence terminates. It ends when the WR bit is cleared by hardware. A byte write automatically erases the location and writes the new data (erase-before-write). Repeat until Clear (see below) n 1 2 PGC P5 0 0 0 0 PGD 4-Bit Command 16-Bit Data Payload PGD = Input 1 2 3 4 1 2 15 16 1 2 3 4 P5 1 2 15 16 P5A PGC P5 P5A Poll WR bit PGD 0 0 0 0 0 0 0 0 MOVWF TABLAT Shift Out Data (see Figure 4-4) 4-Bit Command MOVF EECON1. WR Poll WR bit.PIC18F2XXX/4XXX FAMILY 3. The write sequence is initiated by setting the WR bit (EECON1<1> = 1). W. When using the EECON1 register to perform a data EEPROM write. EEDATA. . with the data to be written and initiating a memory write by appropriately configuring the EECON1 register. The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort and this must be done prior to initiating a write sequence. The write begins on the falling edge of the 4th PGC after the WR bit is set. 0 4-Bit Command PGD = Input PGD = Output DS39622L-page 20  2010 Microchip Technology Inc. PIC18F2410 PIC18F2450 PIC18F2510 PIC18F2515 PIC18F2610 FIGURE 3-6: PROGRAM DATA FLOW Start Set Address Data EEPROM is accessed one byte at a time via an Address Pointer (register pair: EEADRH:EEADR) and a data latch (EEDATA). 0000 0000 0E <Data> 6E A8 MOVLW MOVWF <Data> EEDATA Step 4: Enable memory writes.  2010 Microchip Technology Inc. Step 8: Disable writes. CFGS Step 2: Set the data EEPROM Address Pointer. W. repeat until the bit is clear. Note 1: See Figure 4-4 for details on shift out data timing. DS39622L-page 21 . WR Step 6: Poll WR bit. EEPGD EECON1. 0 MOVWF TABLAT NOP Shift out data(1) Step 7: Hold PGC low for time P10. 0000 82 A6 BSF EECON1. 0000 0000 0000 0000 0E 6E OE 6E <Addr> A9 <AddrH> AA MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH Step 3: Load the data to be written. WREN Repeat Steps 2 through 8 to write more data. WREN Step 5: Initiate write. 0000 84 A6 BSF EECON1.PIC18F2XXX/4XXX FAMILY TABLE 3-7: 4-Bit Command PROGRAMMING DATA MEMORY Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 94 A6 BCF EECON1. 0000 0000 0000 0010 50 A6 6E F5 00 00 <MSB><LSB> MOVF EECON1. 0000 0000 9E A6 9C A6 BCF BCF EECON1. time P10. the ID locations must be erased before being modified. The ID registers are mapped in addresses. EEPGD EECON1.4 ID Location Programming The ID locations are programmed much like the code memory. 2. TABLE 3-8: 4-Bit Command WRITE ID SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. hold PGC high for time P9 and low for 2. 200000h through 200007h. 2. . refer to the methodology described in Section 3. Note: The user only needs to fill the first 8 bytes of the write buffer in order to write the ID locations. DS39622L-page 22  2010 Microchip Technology Inc. CFGS Step 2: Load write buffer with 8 bytes and write.PIC18F2XXX/4XXX FAMILY 3. 0000 0000 8E A6 9C A6 BSF BCF EECON1. In order to modify the ID locations.1 “Modifying Code Memory”. As with code memory.2. These locations read out normally even after code protection. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E 20 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB><LSB> <MSB><LSB> <MSB><LSB> <MSB><LSB> 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP 20h TBLPTRU 00h TBLPTRH 00h TBLPTRL 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and start programming. Table 3-8 demonstrates the code sequence required to write the ID locations. but only 8 bits of the following 16-bit payload will be written. Always write all the Configuration bits before enabling the write protection for Configuration bits. FIGURE 3-8: CONFIGURATION PROGRAMMING FLOW Start Start Load Even Configuration Address Load Odd Configuration Address Program LSB Program MSB Delay P9 and P10 Time for Write Delay P9 and P10 Time for Write Done Done  2010 Microchip Technology Inc. The code sequence to program two consecutive configuration locations is shown in Table 3-9. Begin Programming 4-bit command (‘1111’) is used. 0000 0000 8E A6 8C A6 BSF BSF EECON1. DS39622L-page 23 . Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of the Configuration bits. The LSB of the payload will be written to even addresses and the MSB will be written to odd addresses.hold PGC high for time P9 and low for time P10. Note: The address must be explicitly written for each byte programmed. except that the address used in “Step 2” will be in the range of 000000h to 0007FFh. The addresses can not be incremented in this mode.5 Boot Block Programming 3.(1) 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 1111 0000 Note 1: 0E 30 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB ignored><LSB> 00 00 0E 01 6E F6 <MSB><LSB ignored> 00 00 MOVLW 30h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPRTH MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming. Write even/odd addresses.PIC18F2XXX/4XXX FAMILY 3. MOVLW 01h MOVWF TBLPTRL Load 2 bytes and start programming. CFGS Step 2: Set Table Pointer for configuration byte to be written. EEPGD EECON1.6 Configuration Bits Programming The code sequence detailed in Table 3-5 should be used. The Table Write. NOP . NOP . TABLE 3-9: 4-Bit Command SET ADDRESS POINTER TO CONFIGURATION LOCATION Data Payload Core Instruction Step 1: Enable writes and direct access to configuration memory. the Configuration bits are programmed a byte at a time.hold PGC high for time P9 and low for time P10. Unlike code memory. LSb first. LSb to MSb. ‘1001’ (Table Read. This technique will work to read any memory in the 000000h to 3FFFFFh address space. LSb to MSb.PIC18F2XXX/4XXX FAMILY 4. The read is executed during the next 8 clocks. PGC must be held low (see Figure 4-1). 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Addr[21:16] TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Read memory and then shift out on PGD. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. .1 READING THE DEVICE Read Code Memory. ID Locations and Configuration Bits Code memory is accessed. During this time. This operation also increments the Table Pointer by one. 1001 00 00 TBLRD *+ FIGURE 4-1: 1 2 3 TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001) 4 P5 1 2 3 4 5 6 7 8 P6 P14 9 10 11 12 13 14 15 16 P5A 1 2 3 4 PGC PGD 1 0 0 1 LSb 1 2 3 4 5 6 MSb n n n n Shift Data Out Fetch Next 4-Bit Command PGD = Input PGD = Output PGD = Input DS39622L-page 24  2010 Microchip Technology Inc. The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD. post-increment). via the 4-bit command. one byte at a time. The 4-bit command is shifted in. TABLE 4-1: 4-Bit Command READ CODE MEMORY SEQUENCE Data Payload Core Instruction Step 1: Set Table Pointer. pointing to the next byte in code memory for the next read. so it also applies to the reading of the ID and Configuration registers. then shifted out on PGD during the last 8 clocks.0 4. The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. so two bytes must be read to compare against the word in the programmer’s buffer. DS39622L-page 25 . FIGURE 4-2: VERIFY CODE MEMORY FLOW Start Set TBLPTR = 0 Set TBLPTR = 200000h Read Low Byte with Post-Increment Read Low Byte with Post-Increment Read High Byte with Post-Increment Increment Pointer Read High Byte with Post-Increment Does Word = Expect Data? Yes No All code memory verified? Yes No Failure. Refer to Section 4. 010000h.1 “Read Code Memory. The post-increment feature of the Table Read 4-bit command may not be used to increment the Table Pointer beyond the code memory space.2 Verify Code Memory and ID Locations The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified.PIC18F2XXX/4XXX FAMILY 4. FFFFh. Report Error Does Word = Expect Data? Yes No All ID locations verified? Yes Done No Failure. a post-increment read of address. In a 64-Kbyte device. will wrap the Table Pointer back to 000000h. Memory reads occur a single byte at a time. for example. Report Error  2010 Microchip Technology Inc. ID Locations and Configuration Bits” for implementation details of reading code memory. rather than point to the unimplemented address. ‘1001’. EEPGD EECON1. one byte at a time. 0000 80 A6 BSF EECON1. . PGC must be held low (see Figure 4-4). ‘0010’ (Shift Out Data Holding register). The data will be loaded into EEDATA.1 “Read Code Memory. 0000 0000 0000 0000 0E 6E OE 6E <Addr> A9 <AddrH> AA MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH Step 3: Initiate a memory read.4 Read Data EEPROM Memory Move to TABLAT Data EEPROM is accessed. 0000 0000 0000 0010 Note 1: 50 A8 6E F5 00 00 <MSB><LSB> MOVF EEDATA. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. where it may be serially output on PGD via the 4-bit command. Shift Out Data No Done? Yes Done TABLE 4-2: 4-Bit Command READ DATA EEPROM MEMORY Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0 MOVWF TABLAT NOP Shift Out Data(1) The <LSB> is undefined. W. 0000 0000 9E A6 9C A6 BCF BCF EECON1. The result may then be immediately compared to the appropriate configuration data in the programmer’s memory for verification. During this time. The command sequence to read a single byte of data is shown in Table 4-2. via an Address Pointer (register pair: EEADRH:EEADR) and a data latch (EEDATA).PIC18F2XXX/4XXX FAMILY 4. so it is not necessary to merge two bytes into a word prior to a compare.3 Verify Configuration Bits FIGURE 4-3: A configuration address may be read and output on PGD via the 4-bit command. The <MSB> is the data. Data EEPROM is read by loading EEADRH:EEADR with the desired memory location and initiating a memory read by appropriately configuring the EECON1 register. Configuration data is read and written in a byte-wise fashion. ID Locations and Configuration Bits” for implementation details of reading configuration data. DS39622L-page 26  2010 Microchip Technology Inc. Refer to Section 4. CFGS Step 2: Set the data EEPROM Address Pointer. READ DATA EEPROM FLOW Start Set Address Read Byte 4. RD Step 4: Load data into the Serial Data Holding register. FIGURE 4-5: Start BLANK CHECK FLOW 4. All memories must be verified: code memory. Blank Checking a device merely means to verify that all bytes read as FFh.4 “Read Data EEPROM Memory” and Section 4. The result may then be immediately compared to the appropriate data in the programmer’s memory for verification.5 Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command. A “blank” or “erased” memory cell will read as ‘1’. ‘0010’ (TABLAT register). DS39622L-page 27 . Therefore. Unused (reserved) Configuration bits will read ‘0’ (programmed). refer to Section 4. ID locations and Configuration bits.PIC18F2XXX/4XXX FAMILY FIGURE 4-4: 1 2 3 SHIFT OUT DATA HOLDING REGISTER TIMING (0010) 4 P5 1 2 3 4 5 6 7 8 P6 P14 9 10 11 12 13 14 15 16 P5A 1 2 3 4 PGC PGD 0 1 0 0 LSb 1 2 3 4 5 6 MSb n n n n Shift Data Out Fetch Next 4-Bit Command PGD = Input PGD = Output PGD = Input 4. Is device blank? No Abort Yes Continue  2010 Microchip Technology Inc. except the Configuration bits. Refer to Section 4. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored.2 “Verify Code Memory and ID Locations” for implementation details. Refer to Figure 4-5 for blank configuration expect data for the various PIC18F2XXX/4XXX family devices.6 Blank Check Blank Check Device The term “Blank Check” means to verify that the device has no programmed memory cells. Given that Blank Checking is merely code and data EEPROM verification with FFh expect data.4 “Read Data EEPROM Memory” for implementation details of reading data EEPROM. data EEPROM. ‘0000’) and then output on PGD via the 4-bit command. These bits may be used by the programmer to identify what device type is being programmed and read out normally. mapped in 200000h:200007h. In some cases. The Device ID Word for the PIC18F2XXX/4XXX family devices is located at 3FFFFEh:3FFFFFh. See Table 5-2 for a complete list of Device ID values. 5. the ID data will execute as a NOP. will need to be examined to completely determine the device being accessed.1 ID Locations A user may store identification information (ID) in eight ID locations. It is recommended that the most significant nibble of each ID be Fh. See Table 5-1 for a list of Configuration bits and Device IDs. even after read or code protection. REV4 (DEVID1<4>). These bits can be set or cleared to select various device configurations. These bits may be read out normally.2 Device ID Word The PIC18F2XXX/4XXX family devices have several Configuration Words. All other memory areas should be programmed and verified prior to setting the Configuration Words. In doing so. if the user code inadvertently tries to execute from the ID space. the Most Significant bit of the device revision.PIC18F2XXX/4XXX FAMILY 5. and Table 5-3 for the Configuration bit descriptions. FIGURE 5-1: READ DEVICE ID WORD FLOW Start Set TBLPTR = 3FFFFE Read Low Byte with Post-Increment Read High Byte with Post-Increment Done DS39622L-page 28  2010 Microchip Technology Inc. even after code or read protection.0 CONFIGURATION WORD 5. . devices may share the same DEVID values. In such cases. Implemented on all devices with the exception of the PIC18FXX8X and PIC18F2450/4450 devices.-1-1(1) 1000 -1-1 LVP — STVREN 10-0 -1-1(3) 100.-----11 1111 -1-. DEVID registers are read-only and cannot be programmed by the user. it can be written only in Program mode.3 “Memory Maps”.---See Table 5-2 See Table 5-2 — IESO — FCMEN USBDIV — — VREGEN(1.8) — — ICPRT(1) BBSIZ1 CPUDIV1 — CPUDIV0 FOSC3 PLLDIV2 FOSC2 PLLDIV1 FOSC1 PLLDIV0 FOSC0 300002h 300003h 300005h CONFIG2L CONFIG2H CONFIG3H — — MCLRE — — — BORV1 WDTPS3 — — BBSIZ0 BBSIZ(3) — BBSIZ2(2) CP4(9) — WRT4(9) — EBTR4(9) — REV4 DEV7 BORV0 WDTPS2 — — — — BBSIZ(8) — CP3(4) — WRT3(4) — EBTR3(4) — REV3 DEV6 BOREN1 WDTPS1 LPT1OSC BOREN0 WDTPS0 PBADEN PWRTEN WDTEN CCP2MX(7) — 300006h CONFIG4L DEBUG XINST — ICPRT(8) BBSIZ1(2) CP5(10) — WRT5(10) WRTC(5) EBTR5(10) — DEV0 DEV8 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh 3FFFFEh 3FFFFFh Legend: Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H DEVID1(6) DEVID2(6) — CPD — WRTD — — DEV2 DEV10 — CPB — WRTB — EBTRB DEV1 DEV9 . DS39622L-page 29 .= unimplemented. Implemented on PIC18F2480/2580/4480/4580 devices only. Implemented only on PIC18F2455/2550/4455/4550 and PIC18F2458/2553/4458/4553 devices. Implemented on PIC18F2585/2680/4585/4680.01-1(8) 1000 -1-1(2) CP2(4) — WRT2(4) — EBTR2(4) — REV2 DEV5 CP1 — WRT1 — EBTR1 — REV1 DEV4 CP0 — WRT0 — EBTR0 — REV0 DEV3 --11 1111 11-. Implemented on PIC18F2450/4450 devices only. These bits are only implemented on specific devices based on available memory.PIC18F2XXX/4XXX FAMILY TABLE 5-1: File Name 300000h(1.-011(7) 1--. PIC18F2682/2685 and PIC18F4682/4685 devices only.8) CONFIG1L 300001h CONFIG1H CONFIGURATION BITS AND DEVICE IDS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value --00 0000 00-.-01100. Implemented on PIC18F2685/4685 devices only.0111 00-.-----11 1111 111. Refer to Section 2. Shaded cells are unimplemented.0101(1.  2010 Microchip Technology Inc.8) ---1 1111 --01 1111(1. In PIC18F2480/2580/4480/4580 devices. this bit is read-only in Normal Execution mode.8) ---1 1111 1--. Implemented on PIC18F2682/2685 and PIC18F4682/4685 devices only. read as ‘0’. . DEVID1 bit 4 is used to determine the device type (REV4 = 0).PIC18F2XXX/4XXX FAMILY TABLE 5-2: DEVICE ID VALUES Device ID Value Device DEVID2 PIC18F2221 PIC18F2321 PIC18F2410 PIC18F2420 PIC18F2423 PIC18F2450 PIC18F2455 PIC18F2458 PIC18F2480 PIC18F2510 PIC18F2515 PIC18F2520 PIC18F2523 PIC18F2525 PIC18F2550 PIC18F2553 PIC18F2580 PIC18F2585 PIC18F2610 PIC18F2620 PIC18F2680 PIC18F2682 PIC18F2685 PIC18F4221 PIC18F4321 PIC18F4410 PIC18F4420 PIC18F4423 PIC18F4450 PIC18F4455 PIC18F4458 PIC18F4480 PIC18F4510 PIC18F4515 PIC18F4520 PIC18F4523 PIC18F4525 PIC18F4550 PIC18F4553 PIC18F4580 PIC18F4585 PIC18F4610 Legend: Note 1: 2: 21h 21h 11h 11h 11h 24h 12h 2Ah 1Ah 11h 0Ch 11h 11h 0Ch 12h 2Ah 1Ah 0Eh 0Ch 0Ch 0Eh 27h 27h 21h 21h 10h 10h 10h 24h 12h 2Ah 1Ah 10h 0Ch 10h 10h 0Ch 12h 2Ah 1Ah 0Eh 0Ch DEVID1 011x xxxx 001x xxxx 011x xxxx 010x xxxx(1) 010x xxxx(2) 001x xxxx 011x xxxx 011x xxxx 111x xxxx 001x xxxx 111x xxxx 000x xxxx(1) 000x xxxx(2) 110x xxxx 010x xxxx 010x xxxx 110x xxxx 111x xxxx 101x xxxx 100x xxxx 110x xxxx 000x xxxx 001x xxxx 010x xxxx 000x xxxx 111x xxxx 110x xxxx(1) 110x xxxx(2) 000x xxxx 001x xxxx 001x xxxx 101x xxxx 101x xxxx 011x xxxx 100x xxxx(1) 100x xxxx(2) 010x xxxx 000x xxxx 000x xxxx 100x xxxx 101x xxxx 001x xxxx The ‘x’s in DEVID1 contain the device revision code. DS39622L-page 30  2010 Microchip Technology Inc. DEVID1 bit 4 is used to determine the device type (REV4 = 1). WRTB or WRT0. PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) 111x = HS oscillator. EC is used by USB 0101 = EC oscillator. CLKO function on RA6. HS is used by USB 1010 = Internal oscillator. HS is used by USB 1011 = Internal oscillator. PLL is enabled. port function on RA6. PLL is enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator. EC is used by USB 1000 = Internal oscillator. DS39622L-page 31 . port function on RA7 1000 = Internal RC oscillator. port function on RA6. CLKO function on RA6 1001 = Internal RC oscillator. PLL is enabled. EC is used by USB 0111 = EC oscillator. CLKO function on RA6. port function on RA6 0110 = HS oscillator. port function on RA6. HS is used by USB 110x = HS oscillator. EC is used by USB 0110 = EC oscillator. cannot be changed once any of the following code-protect bits are enabled: CPB or CP0. Not available in PIC18FXX8X and PIC18F2450/4450 devices. CLKO function on RA6. XT is used by USB FCMEN CONFIG1H FOSC<3:0> CONFIG1H FOSC<3:0> CONFIG1H Note 1: 2: The BBSIZ bits. DEVID1 bit 4 is used to determine the device type (REV4 = 0). port function on RA6 0100 = EC oscillator. DEVID1 bit 4 is used to determine the device type (REV4 = 1). PLL is enabled. EC is used by USB 001x = XT oscillator. CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Oscillator Selection bits  (PIC18F2455/2550/4455/4550. CLKO function on RA6. port function on RA6.  2010 Microchip Technology Inc. EC is used by USB 0100 = EC oscillator. TABLE 5-3: Bit Name IESO PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS Configuration Words CONFIG1H Description Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled Oscillator Selection bits 11xx = External RC oscillator. PLL is enabled.PIC18F2XXX/4XXX FAMILY TABLE 5-2: DEVICE ID VALUES (CONTINUED) Device ID Value Device DEVID2 PIC18F4620 PIC18F4680 PIC18F4682 PIC18F4685 Legend: Note 1: 2: 0Ch 0Eh 27h 27h DEVID1 000x xxxx 100x xxxx 010x xxxx 011x xxxx The ‘x’s in DEVID1 contain the device revision code. XT is used by USB 1001 = Internal oscillator. EBTRB or EBTR0. CLKO function on RA6 0011 = External RC oscillator. XT is used by USB 000x = XT oscillator. port function on RA7 0111 = External RC oscillator. BBSIZ<1:0> and BBSIZ<2:1> bits. CLKO function on RA6 101x = External RC oscillator. 0V 10 = VBOR is set to 2. WRTB or WRT0. PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) 1 = USB voltage regulator is enabled 0 = USB voltage regulator is disabled Brown-out Reset Voltage bits 11 = VBOR is set to 2. PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) Divider must be selected to provide a 4 MHz input into the 96 MHz PLL: 111 = Oscillator divided by 12 (48 MHz input) 110 = Oscillator divided by 10 (40 MHz input) 101 = Oscillator divided by 6 (24 MHz input) 100 = Oscillator divided by 5 (20 MHz input) 011 = Oscillator divided by 4 (16 MHz input) 010 = Oscillator divided by 3 (12 MHz input) 001 = Oscillator divided by 2 (8 MHz input) 000 = No divide – oscillator used directly (4 MHz input) USB Voltage Regulator Enable bit  (PIC18F2455/2550/4455/4550. Not available in PIC18FXX8X and PIC18F2450/4450 devices.  no divide CPU System Clock Selection bits  (PIC18F2455/2550/4455/4550. EBTRB or EBTR0. cannot be changed once any of the following code-protect bits are enabled: CPB or CP0.7V 01 = VBOR is set to 4. . PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) Selects the clock source for full-speed USB operation: 1 = USB clock source comes from the 96 MHz PLL divided by 2 0 = USB clock source comes directly from the OSC1/OSC2 oscillator block.2V 00 = VBOR is set to 4. DS39622L-page 32  2010 Microchip Technology Inc.5V Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode SBOREN is disabled) 01 = Brown-out Reset is enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset is disabled in hardware and software Power-up Timer Enable bit 1 = PWRT is disabled 0 = PWRT is enabled CPUDIV<1:0> CONFIG1L PLLDIV<2:0> CONFIG1L VREGEN CONFIG2L BORV<1:0> CONFIG2L BOREN<1:0> CONFIG2L PWRTEN CONFIG2L Note 1: 2: The BBSIZ bits. BBSIZ<1:0> and BBSIZ<2:1> bits. PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) 11 = CPU system clock divided by 4 10 = CPU system clock divided by 3 01 = CPU system clock divided by 2 00 = No CPU system clock divide Oscillator Selection bits  (PIC18F2455/2550/4455/4550.PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name USBDIV PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words CONFIG1L Description USB Clock Selection bit  (PIC18F2455/2550/4455/4550. MCLR pin is disabled Low-Power Timer1 Oscillator Enable bit 1 = Timer1 is configured for low-power operation 0 = Timer1 is configured for high-power operation PORTB A/D Enable bit 1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset 0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset PORTB A/D Enable bit (PIC18FXX8X devices only) 1 = PORTB A/D<4:0> and PORTB A/D<1:0> pins are configured as analog input  channels on Reset 0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1(2) 0 = CCP2 input/output is multiplexed with RB3 Background Debugger Enable bit 1 = Background debugger is disabled.024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit) MCLR Pin Enable bit 1 = MCLR pin is enabled. BBSIZ<1:0> and BBSIZ<2:1> bits. cannot be changed once any of the following code-protect bits are enabled: CPB or CP0. DS39622L-page 33 .048 1010 = 1:1. RE3 input pin is disabled 0 = RE3 input pin is enabled. Not available in PIC18FXX8X and PIC18F2450/4450 devices. RB6 and RB7 are configured as general  purpose I/O pins 0 = Background debugger is enabled.PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name WDPS<3:0> PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words CONFIG2H Description Watchdog Timer Postscaler Select bits 1111 = 1:32.384 1101 = 1:8.768 1110 = 1:16.192 1100 = 1:4. EBTRB or EBTR0.  2010 Microchip Technology Inc. WRTB or WRT0. RB6 and RB7 are dedicated to In-Circuit  Debug Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode are enabled 0 = Instruction set extension and Indexed Addressing mode are disabled  (Legacy mode) WDTEN CONFIG2H MCLRE CONFIG3H LPT1OSC CONFIG3H PBADEN CONFIG3H PBADEN CONFIG3H CCP2MX CONFIG3H DEBUG CONFIG4L XINST CONFIG4L Note 1: 2: The BBSIZ bits.096 1011 = 1:2. Not available in PIC18FXX8X and PIC18F2450/4450 devices. . BBSIZ<1:0> and BBSIZ<2:1> bits. WRTB or WRT0. DS39622L-page 34  2010 Microchip Technology Inc. RB5 is an I/O pin Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow is enabled 0 = Reset on stack overflow/underflow is disabled Code Protection bit (Block 5 code memory area)  (PIC18F2685 and PIC18F4685 devices only) 1 = Block 5 is not code-protected 0 = Block 5 is code-protected Code Protection bit (Block 4 code memory area)  (PIC18F2682/2685 and PIC18F4682/4685 devices only) 1 = Block 4 is not code-protected 0 = Block 4 is code-protected Code Protection bit (Block 3 code memory area) 1 = Block 3 is not code-protected 0 = Block 3 is code-protected LVP CONFIG4L STVREN CONFIG4L CP5 CONFIG5L CP4 CONFIG5L CP3 CONFIG5L Note 1: 2: The BBSIZ bits. RB5 is the PGM pin 0 = Low-Voltage Programming is disabled. EBTRB or EBTR0. PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) 1 = ICPORT is enabled 0 = ICPORT is disabled Boot Block Size Select bits (PIC18F2585/2680/4585/4680 devices only) 11 = 4K words (8 Kbytes) Boot Block 10 = 4K words (8 Kbytes) Boot Block 01 = 2K words (4 Kbytes) Boot Block 00 = 1K word (2 Kbytes) Boot Block Boot Block Size Select bits (PIC18F2682/2685/4582/4685 devices only) 11 = 4K words (8 Kbytes) Boot Block 10 = 4K words (8 Kbytes) Boot Block 01 = 2K words (4 Kbytes) Boot Block 00 = 1K word (2 Kbytes) Boot Block Boot Block Size Select bits (PIC18F2321/4321 devices only) 11 = 1K word (2 Kbytes) Boot Block 10 = 1K word (2 Kbytes) Boot Block 01 = 512 words (1 Kbyte) Boot Block 00 = 256 words (512 bytes) Boot Block Boot Block Size Select bits (PIC18F2221/4221 devices only) 11 = 512 words (1 Kbyte) Boot Block 10 = 512 words (1 Kbyte) Boot Block 01 = 512 words (1 Kbyte) Boot Block 00 = 256 words (512 bytes) Boot Block BBSIZ<1:0>(1) CONFIG4L BBSIZ<2:1>(1) CONFIG4L BBSIZ<1:0>(1) CONFIG4L BBSIZ(1) CONFIG4L Boot Block Size Select bits  (PIC18F2480/2580/4480/4580 and PIC18F2450/4450 devices only) 1 = 2K words (4 Kbytes) Boot Block 0 = 1K word (2 Kbytes) Boot Block Low-Voltage Programming Enable bit 1 = Low-Voltage Programming is enabled. cannot be changed once any of the following code-protect bits are enabled: CPB or CP0.PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name ICPRT PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words CONFIG4L Description Dedicated In-Circuit (ICD/ICSP™) Port Enable bit  (PIC18F2455/2550/4455/4550.  2010 Microchip Technology Inc. cannot be changed once any of the following code-protect bits are enabled: CPB or CP0. DS39622L-page 35 .PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name CP2 PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words CONFIG5L Description Code Protection bit (Block 2 code memory area) 1 = Block 2 is not code-protected 0 = Block 2 is code-protected Code Protection bit (Block 1 code memory area) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected Code Protection bit (Block 0 code memory area) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected Code Protection bit (Data EEPROM) 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected Code Protection bit (Boot Block memory area) 1 = Boot Block is not code-protected 0 = Boot Block is code-protected Write Protection bit (Block 5 code memory area)  (PIC18F2685 and PIC18F4685 devices only) 1 = Block 5 is not write-protected 0 = Block 5 is write-protected Write Protection bit (Block 4 code memory area)  (PIC18F2682/2685 and PIC18F4682/4685 devices only) 1 = Block 4 is not write-protected 0 = Block 4 is write-protected Write Protection bit (Block 3 code memory area) 1 = Block 3 is not write-protected 0 = Block 3 is write-protected Write Protection bit (Block 2 code memory area) 1 = Block 2 is not write-protected 0 = Block 2 is write-protected Write Protection bit (Block 1 code memory area) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected Write Protection bit (Block 0 code memory area) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected Write Protection bit (Data EEPROM) 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected Write Protection bit (Boot Block memory area) 1 = Boot Block is not write-protected 0 = Boot Block is write-protected Write Protection bit (Configuration registers) 1 = Configuration registers are not write-protected 0 = Configuration registers are write-protected CP1 CONFIG5L CP0 CONFIG5L CPD CONFIG5H CPB CONFIG5H WRT5 CONFIG6L WRT4 CONFIG6L WRT3 CONFIG6L WRT2 CONFIG6L WRT1 CONFIG6L WRT0 CONFIG6L WRTD CONFIG6H WRTB CONFIG6H WRTC CONFIG6H Note 1: 2: The BBSIZ bits. BBSIZ<1:0> and BBSIZ<2:1> bits. WRTB or WRT0. EBTRB or EBTR0. Not available in PIC18FXX8X and PIC18F2450/4450 devices. REV<4:0> DEVID1 Revision ID bits These bits are used to indicate the revision of the device. The REV4 bit is  sometimes used to fully specify the device type. cannot be changed once any of the following code-protect bits are enabled: CPB or CP0. Not available in PIC18FXX8X and PIC18F2450/4450 devices. EBTRB or EBTR0. BBSIZ<1:0> and BBSIZ<2:1> bits. WRTB or WRT0.PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name EBTR5 PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words CONFIG7L Description Table Read Protection bit (Block 5 code memory area)  (PIC18F2685 and PIC18F4685 devices only) 1 = Block 5 is not protected from Table Reads executed in other blocks 0 = Block 5 is protected from Table Reads executed in other blocks Table Read Protection bit (Block 4 code memory area)  (PIC18F2682/2685 and PIC18F4682/4685 devices only) 1 = Block 4 is not protected from Table Reads executed in other blocks 0 = Block 4 is protected from Table Reads executed in other blocks Table Read Protection bit (Block 3 code memory area) 1 = Block 3 is not protected from Table Reads executed in other blocks 0 = Block 3 is protected from Table Reads executed in other blocks Table Read Protection bit (Block 2 code memory area) 1 = Block 2 is not protected from Table Reads executed in other blocks 0 = Block 2 is protected from Table Reads executed in other blocks Table Read Protection bit (Block 1 code memory area) 1 = Block 1 is not protected from Table Reads executed in other blocks 0 = Block 1 is protected from Table Reads executed in other blocks Table Read Protection bit (Block 0 code memory area) 1 = Block 0 is not protected from Table Reads executed in other blocks 0 = Block 0 is protected from Table Reads executed in other blocks Table Read Protection bit (Boot Block memory area) 1 = Boot Block is not protected from Table Reads executed in other blocks 0 = Boot Block is protected from Table Reads executed in other blocks Device ID bits These bits are used with the DEV<2:0> bits in the DEVID1 register to identify part number. . DS39622L-page 36  2010 Microchip Technology Inc. EBTR4 CONFIG7L EBTR3 CONFIG7L EBTR2 CONFIG7L EBTR1 CONFIG7L EBTR0 CONFIG7L EBTRB CONFIG7H DEV<10:3> DEVID2 DEV<2:0> DEVID1 Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify part number. Note 1: 2: The BBSIZ bits. are used for this calculation.6. unimplemented bits in Configuration Words should be ignored as such bits always read back as ‘1’s. Similarly. When embedding Configuration Word information in the hex file.6 Checksum Computation The LVP bit in Configuration register. a simple warning message should be issued. The contents of program memory. 5. Note 1: The High-Voltage ICSP mode is always available. CONFIG4L.6. When ANDed with the value read out of a Configuration Word. only implemented bits remain. If the user uses the preprotected checksum. from 000000h to the end of the last program memory block. the LVP bit may only be programmed by entering the High-Voltage ICSP mode. even when the device is fully code-protected. then a simple warning message should be issued. all Configuration Word information must be included. If data EEPROM information is not present. each 16-bit word is added to the checksum. 5. appropriately masked • ID locations (if any block is code-protected) The Least Significant 16 bits of this sum is the checksum. the RB5 pin can no longer be used as a general purpose I/O. provided by MPLAB IDE. and if the ID locations should be used for checksum calculations.5 Embedding Data EEPROM Information In the HEX File To allow portability of code. the contents of these locations are defined by the user. 5.3 ID LOCATIONS Normally. feels strongly that this feature is important for the benefit of the end customer. Similarly. An option to not include the data EEPROM information may be provided. 5. of the program memory blocks can be read. or a ‘1’ where a choice can be made. the LVP bit can be programmed to a ‘0’ and RB5/PGM becomes a digital I/O pin.PIC18F2XXX/4XXX FAMILY 5. it should start at address. where MCLR/VPP/RE3 is raised to VIHH. it should start at address. if any. then the contents of the ID locations are included in the checksum calculation.6. 5.2 CONFIGURATION WORDS For checksum calculations.4 CODE PROTECTION Blocks that are code-protected read back as all ‘0’s and have no effect on checksum calculations. nothing about protected blocks can be known. Each 8-bit Configuration Word is ANDed with a corresponding mask to prevent unused bits from affecting checksum calculations. This is the sum of all program memory contents and Configuration Words (appropriately masked) before any code protection is enabled. while saving a hex file. a PIC18F2XXX/4XXX family programmer is required to read the Configuration Word locations from the hex file. If Configuration Word information is not present in the hex file.6.3 Single-Supply ICSP Programming 5.1 PROGRAM MEMORY When program memory contents are summed. Microchip Technology Inc. an indirect characteristic of the programmed code is provided. 2: While in Low-Voltage ICSP mode. If Single-Supply Programming mode is not used. Microchip Technology Inc. The lower 16 bits are not used and remain clear. An option to not include the Configuration Word information may be provided. All Configuration Words and the ID locations can always be read out normally. If any block is code-protected. 300000h. believes that this feature is important for the benefit of the end customer. but MPLAB® IDE provides the option of writing the device’s unprotected 16-bit checksum in the 16 Most Significant bits of the ID locations (see MPLAB IDE Configure/ID Memory” menu). by applying VIHH to the MCLR/VPP/RE3 pin. Once the LVP bit is programmed to a ‘0’. The mask contains a ‘0’ in unimplemented bit positions. a PIC18F2XXX/4XXX family programmer is required to read the data EEPROM information from the hex file. However.  2010 Microchip Technology Inc. The LVP bit defaults to a ‘1’ (enabled) from the factory. F00000h. A list of suitable masks is provided in Table 5-5. 5. Checking the code protection settings in Configuration Words can direct which. The checksum is calculated by summing the following: • The contents of all code memory locations • The Configuration Words. regardless of the state of the LVP bit.4 Embedding Configuration Word Information in the HEX File To allow portability of code. When embedding data EEPROM information in the hex file. all data EEPROM information must be included. when saving a hex file. only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. If the user elects to define the contents of the ID locations. The contents of the data EEPROM are not used. DS39622L-page 37 . Overflows from bit 15 may be ignored. enables Single-Supply (Low-Voltage) ICSP Programming. PIC18F2XXX/4XXX FAMILY TABLE 5-4: Device DEVICE BLOCK LOCATIONS AND SIZES Ending Address Boot Block 0001FF 0003FF 0001FF Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Boot Block 512 1024 512 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1024 2048 2048 2048 2048 2048 4096 2048 2048 2048 4096 2048 2048 2048 2048 2048 2048 2048 2048 4096 2048 — — — — — — — — — 4096 8192 2048 2048 2048 4096 8192 2048 — 4096 8192 2048 4096 8192 0007FF 000FFF — — — — 512 1024 512 — — — — — — — — — — — — — — — — — — — — 1024 2048 2048 2048 2048 2048 4096 Size (Bytes) Block 0 1536 1024 3584 3072 2048 6144 6144 6144 6144 4096 6144 6144 6144 4096 6144 14336 14336 14336 14336 6144 6144 6144 4096 14336 12288 8192 14336 14336 14336 12288 8192 14336 12288 8192 14336 12288 8192 1536 1024 3584 3072 2048 6144 6144 6144 6144 4096 8192 8192 8192 8192 16384 16384 16384 16384 4096 8192 2048 4096 81920 98304 65536 81920 49152 65536 49152 49152 65536 65536 32768 49152 8192 8192 8192 8192 16384 16384 8192 24576 32768 16384 16384 32768 24576 24576 24576 16384 16384 16384 16384 24576 24576 16384 32768 49152 32768 32768 49152 32768 32768 32768 4096 8192 Remaining Device Blocks Total 2048 4096 Memory Size Pins (Bytes) 4K 28 PIC18F2221 0007FF 000FFF — — — — PIC18F2321 PIC18F2410 PIC18F2420 PIC18F2423 PIC18F2450 PIC18F2455 PIC18F2458 PIC18F2480 PIC18F2510 PIC18F2515 PIC18F2520 PIC18F2523 PIC18F2525 PIC18F2550 PIC18F2553 PIC18F2580 8K 16K 16K 16K 16K 24K 24K 16K 32K 48K 32K 32K 48K 32K 32K 32K 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 0003FF 000FFF 001FFF 0007FF 0007FF 001FFF 003FFF 0007FF 001FFF 003FFF 0007FF 001FFF 003FFF 0007FF 000FFF 001FFF 003FFF 0007FF 001FFF 003FFF 005FFF 0007FF 001FFF 003FFF 005FFF 0007FF 000FFF 001FFF 003FFF — 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 003FFF 007FFF 00BFFF — 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 003FFF 007FFF 00BFFF — 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 000FFF 0007FF 001FFF 003FFF 005FFF 007FFF PIC18F2585 PIC18F2610 PIC18F2620 PIC18F2680 48K 64K 64K 64K 28 28 28 28 000FFF 003FFF 007FFF 00BFFF 001FFF 0007FF 003FFF 007FFF 00BFFF 00FFFF 0007FF 003FFF 007FFF 00BFFF 00FFFF 0007FF 000FFF 003FFF 007FFF 00BFFF 00FFFF 001FFF 0007FF PIC18F2682 80K 28 000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF 001FFF 0007FF PIC18F2685 96K 28 000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF 017FFF 001FFF 0001FF 0003FF 0001FF PIC18F4221 4K 40 PIC18F4321 PIC18F4410 PIC18F4420 PIC18F4423 PIC18F4450 Legend: 8K 16K 16K 16K 16K 40 40 40 40 40 0003FF 000FFF 001FFF 0007FF 0007FF 001FFF 003FFF 0007FF 001FFF 003FFF 0007FF 001FFF 003FFF 0007FF 000FFF 001FFF 003FFF — = unimplemented. . DS39622L-page 38  2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY TABLE 5-4: Device DEVICE BLOCK LOCATIONS AND SIZES (CONTINUED) Ending Address Boot Block Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 — — — — — — — — — — — — — — — — — — — — — — — — — Boot Block 2048 2048 2048 4096 2048 2048 2048 2048 2048 2048 2048 2048 4096 2048 — — — — — — — — — 4096 8192 2048 2048 2048 4096 8192 2048 — 4096 8192 2048 4096 8192 Size (Bytes) Block 0 6144 6144 6144 4096 6144 14336 14336 14336 14336 6144 6144 6144 4096 14336 12288 8192 14336 14336 14336 12288 8192 14336 12288 8192 14336 12288 8192 81920 98304 65536 81920 49152 65536 49152 49152 65536 65536 32768 49152 Remaining Device Blocks Total 16384 16384 8192 24576 32768 16384 16384 32768 24576 24576 24576 24576 24576 16384 32768 49152 32768 32768 49152 32768 32768 32768 Memory Size Pins (Bytes) 24K 24K 16K 32K 48K 32K 32K 48K 32K 32K 32K 40 40 40 40 40 40 40 40 40 40 40 PIC18F4455 PIC18F4458 PIC18F4480 PIC18F4510 PIC18F4515 PIC18F4520 PIC18F4523 PIC18F4525 PIC18F4550 PIC18F4553 PIC18F4580 0007FF 001FFF 003FFF 005FFF 0007FF 001FFF 003FFF 005FFF 0007FF 000FFF 001FFF 003FFF — 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 003FFF 007FFF 00BFFF — 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 003FFF 007FFF 00BFFF — 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 001FFF 003FFF 005FFF 007FFF 0007FF 000FFF 0007FF 001FFF 003FFF 005FFF 007FFF PIC18F4585 PIC18F4610 PIC18F4620 PIC18F4680 48K 64K 64K 64K 40 40 40 40 000FFF 003FFF 007FFF 00BFFF 001FFF 0007FF 003FFF 007FFF 00BFFF 00FFFF 0007FF 003FFF 007FFF 00BFFF 00FFFF 0007FF 000FFF 003FFF 007FFF 00BFFF 00FFFF 001FFF 0007FF PIC18F4682 80K 40 000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF 001FFF 0007FF PIC18F4685 Legend: 96K 44 000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF 017FFF 001FFF — = unimplemented. DS39622L-page 39 .  2010 Microchip Technology Inc. . DS39622L-page 40  2010 Microchip Technology Inc.PIC18F2XXX/4XXX FAMILY TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS Configuration Word (CONFIGxx) Device 1L 1H 2L 2H 3L 3H 4L 4H 5L 5H 6L 6H 7L 7H Address (30000xh) 0h PIC18F2221 PIC18F2321 PIC18F2410 PIC18F2420 PIC18F2423 PIC18F2450 PIC18F2455 PIC18F2458 PIC18F2480 PIC18F2510 PIC18F2515 PIC18F2520 PIC18F2523 PIC18F2525 PIC18F2550 PIC18F2553 PIC18F2580 PIC18F2585 PIC18F2610 PIC18F2620 PIC18F2680 PIC18F2682 PIC18F2685 PIC18F4221 PIC18F4321 PIC18F4410 PIC18F4420 PIC18F4423 PIC18F4450 PIC18F4455 PIC18F4458 PIC18F4480 PIC18F4510 PIC18F4515 PIC18F4520 PIC18F4523 PIC18F4525 PIC18F4550 PIC18F4553 PIC18F4580 PIC18F4585 PIC18F4610 Legend: 00 00 00 00 00 3F 3F 3F 00 00 00 00 00 00 3F 3F 00 00 00 00 00 00 00 00 00 00 00 00 3F 3F 3F 00 00 00 00 00 00 3F 3F 00 00 00 1h CF CF CF CF CF CF CF CF CF 1F CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF 2h 1F 1F 1F 1F 1F 3F 3F 3F 1F 1F 1F 1F 1F 1F 3F 3F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 3F 3F 3F 1F 1F 1F 1F 1F 1F 3F 3F 1F 1F 1F 3h 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 4h 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5h 87 87 87 87 87 86 87 87 86 87 87 87 87 87 87 87 86 86 87 87 86 86 86 87 87 87 87 87 86 87 87 86 87 87 87 87 87 87 87 86 86 87 6h F5 F5 C5 C5 C5 ED E5 E5 D5 C5 C5 C5 C5 C5 E5 E5 E5 C5 C5 C5 C5 C5 C5 F5 F5 C5 C5 C5 ED E5 E5 D5 C5 C5 C5 C5 C5 E5 E5 E5 C5 C5 7h 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8h 03 03 03 03 03 03 07 07 03 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 3F 3F 03 03 03 03 03 03 07 07 03 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 9h C0 C0 C0 C0 C0 40 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 40 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 Ah 03 03 03 03 03 03 07 07 03 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 3F 3F 03 03 03 03 03 03 07 07 03 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F Bh E0 E0 E0 E0 E0 60 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 60 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 Ch 03 03 03 03 03 03 07 07 03 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 3F 3F 03 03 03 03 03 03 07 07 03 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F Dh 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 Shaded cells are unimplemented. PIC18F2XXX/4XXX FAMILY TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS (CONTINUED) Configuration Word (CONFIGxx) Device 1L 1H 2L 2H 3L 3H 4L 4H 5L 5H 6L 6H 7L 7H Address (30000xh) 0h PIC18F4620 PIC18F4680 PIC18F4682 PIC18F4685 Legend: 00 00 00 00 1h CF CF CF CF 2h 1F 1F 1F 1F 3h 1F 1F 1F 1F 4h 00 00 00 00 5h 87 86 86 86 6h C5 C5 C5 C5 7h 00 00 00 00 8h 0F 0F 3F 3F 9h C0 C0 C0 C0 Ah 0F 0F 3F 3F Bh E0 E0 E0 E0 Ch 0F 0F 3F 3F Dh 40 40 40 40 Shaded cells are unimplemented. DS39622L-page 41 .  2010 Microchip Technology Inc. This can cause spurious program executions to occur.6 — 50 1. . HS/PLL and XT modes only) +  2 ms (for HS/PLL mode only) + 1.5 5.7 — — 100 1 TPGCL Serial Clock (PGC) Low Time TPGCH Serial Clock (PGC) High Time TSET1 Input Data Setup Time to Serial Clock  THLD1 Input Data Hold Time from PGC TDLY1 Delay Between 4-Bit Command and Command Operand TDLY1A Delay Between 4-Bit Command Operand and Next 4-Bit Command TDLY2 Delay Between Last PGC  of Command Byte to First PGC  of Read of Data Word TDLY5 PGC High Time (minimum programming time) TDLY6 PGC Low Time After Programming (high-voltage discharge time) TDLY7 Delay to Allow Self-Timed Data Write or  Bulk Erase to Occur 40 400 40 400 15 15 40 40 20 1 100 5 Max 12.00 3. refer to the Electrical Characteristics section of the device data sheet for the particular device.0 mA @ 4.0V VDD = 5.5V IOH = -3. this specification also applies to ICVPP.2 VDD VDD 0. At 0°C-50°C.00 2. DS39622L-page 42  2010 Microchip Technology Inc.PIC18F2XXX/4XXX FAMILY 6.50 5. Row Erases and all writes Self-timed. HS.0V VDD = 2.5 s (for EC mode only) where TCY is the instruction cycle time. D110 Sym VIHH Characteristic High-Voltage Programming Voltage on  MCLR/VPP/RE3 Low-Voltage Programming Voltage on  MCLR/VPP/RE3 Supply Voltage During Programming Min VDD + 4.50 300 10 0.0V VDD = 2.5 mA @ 4.0V VDD = 2.0 D112 D113 D031 D041 D080 D090 D012 P1 P2 P2A P2B P3 P4 P5 P5A P6 P9 P10 P11 IPP IDDP VIL VIH VOL VOH CIO TR TPGC Programming Current on MCLR/VPP/RE3 Supply Current During Programming Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Capacitive Loading on I/O pin (PGD) MCLR/VPP/RE3 Rise Time to Enter  Program/Verify mode Serial Clock (PGC) Period — — VSS 0. TPWRT is the Power-up Timer period and TOSC is the oscillator period.0V VDD = 5. 2) VDD = 5.0 — — — — — — — — — — — — — — Units V V V V A mA V V V V pF s ns s ns ns ns ns ns ns ns ns ns ms s ms Externally timed IOL = 8. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS  FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25C is recommended Param No. Bulk Erases only (Note 3) (Note 2) D110A VIHL D111 VDD Note 1: 2: 3: Do not allow excess time when transitioning MCLR between VIL and VIHH.8 VDD — VDD – 0. When ICPRT = 1.5V To meet AC specifications (Notes 1. For specific values.0 2.0V Conditions (Note 2) (Note 2) Externally timed.50 5. DS39622L-page 43 .  2010 Microchip Technology Inc.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS  FOR PROGRAM/VERIFY TEST MODE (CONTINUED) Standard Operating Conditions Operating Temperature: 25C is recommended Param No. P11A P12 P13 P14 P15 P16 P17 P18 Sym Characteristic Min 4 2 100 10 2 0 — 0 Max — — — — — — 100 — Units ms s ns ns s s ns s (Note 2) (Note 2) Conditions TDRWT Data Write Polling Time THLD2 Input Data Hold Time from MCLR/VPP/RE3  TSET2 VDD Setup Time to MCLR/VPP/RE3  TVALID Data Out Valid from PGC  TSET3 PGM Setup Time to MCLR/VPP/RE3  TDLY8 Delay Between Last PGC  and MCLR/VPP/RE3  THLD3 MCLR/VPP/RE3 to VDD  THLD4 MCLR/VPP/RE3 to PGM  Note 1: 2: 3: Do not allow excess time when transitioning MCLR between VIL and VIHH.5 s (for EC mode only) where TCY is the instruction cycle time. refer to the Electrical Characteristics section of the device data sheet for the particular device. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP. When ICPRT = 1. This can cause spurious program executions to occur. HS.PIC18F2XXX/4XXX FAMILY 6. this specification also applies to ICVPP. TPWRT is the Power-up Timer period and TOSC is the oscillator period. HS/PLL and XT modes only) +  2 ms (for HS/PLL mode only) + 1. At 0°C-50°C. For specific values. PIC18F2XXX/4XXX FAMILY NOTES: DS39622L-page 44  2010 Microchip Technology Inc. . MPASM. UniWinDriver. FilterLab. SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U. microperipherals. If such acts allow unauthorized access to your software or other copyrighted work. nonvolatile memory and analog products. INCLUDING BUT NOT LIMITED TO ITS CONDITION.S. We at Microchip are committed to continuously improving the code protection features of our products. dsPIC. Microchip believes that its family of products is one of the most secure families of its kind on the market today.S. Arizona.S. claims. TSHARC. Microchip is willing to work with the customer who is concerned about the integrity of their code. MPLINK. the person doing so is engaged in theft of intellectual property. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. Select Mode. Printed on recycled paper. ECONOMONITOR. CodeGuard. Total Endurance. Omniscient Code Generation.net.net. MiWi. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. PICkit. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED. It is your responsibility to ensure that your application meets with your specifications. dsPICDEM.A. Trademarks The Microchip name and logo.S. STATUTORY OR OTHERWISE. MXDEV. PICtail. rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U. All of these methods. or expenses resulting from such use. Linear Active Thermistor.S. indemnify and hold harmless Microchip from any and all damages. PICC-18. © 2010. In-Circuit Serial Programming. KEELOQ® code hopping devices. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk. under any Microchip intellectual property rights. ECAN. PERFORMANCE. PICDEM. HI-TIDE.  2010 Microchip Technology Inc. when used in the intended manner and under normal conditions. mTouch. WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U. PIC.” • • • Code protection is constantly evolving. No licenses are conveyed. Hampshire.A. WRITTEN OR ORAL. and the buyer agrees to defend. There are dishonest and possibly illegal methods used to breach the code protection feature. HI-TECH C. MXLAB. MERCHANTABILITY OR FITNESS FOR PURPOSE. Analog-for-the-Digital Age. and other countries. Serial EEPROMs. design and wafer fabrication facilities in Chandler and Tempe. SQTP is a service mark of Microchip Technology Incorporated in the U. require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. ISBN: 978-1-60932-578-7 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters. KEELOQ. Oregon and design centers in California and India. suits. dsSPEAK. MPLIB. Code protection does not mean that we are guaranteeing the product as “unbreakable. RELATED TO THE INFORMATION. to our knowledge. and other countries. implicitly or otherwise. rfLAB. All other trademarks mentioned herein are property of their respective companies. Most likely. the Microchip logo. Application Maestro. MPLAB. FanSense.A. PICSTART. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs. ICSP.A. Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. In addition. PICDEM.A. PICmicro. Mindi. KEELOQ logo. PIC32 logo. you may have a right to sue for relief under that Act. dsPICDEM. QUALITY. REAL ICE. DS39622L-page 45 . dsPICworks. All Rights Reserved. PICC. MPLAB Certified logo. Gresham. Microchip Technology Incorporated. Microchip disclaims all liability arising from this information and its use..Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Printed in the U. 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