Assembler Tutorial - WiiBrew04/11/2014 create account page discussion view source history Log in WiiBrew recommends that you run the latest version of the HackMii Installer and then optionally update your Wii to 4.3 using Nintendo's official updater. Only update using the official update procedure. Downgrading or installing patched updates is unsupported, dangerous, and may permanently brick your Wii. navigation Main Page FAQ Glossary Recent changes Random page Wiki help WiiBrew forum homebrew News Releases Applications Homebrew channel Assembler Tutorial Contents [hide] 1 Introduction 2 The registers 3 Variables 4 Constants 5 Instructions and Mnemonics 5.1 Integer Instructions 5.1.1 Integer Arithmetic Instructions 5.1.1.1 ADD 5.1.1.2 SUBF - Subtract From 5.1.1.3 MUL - Multiply 5.1.1.4 DIV - Divide 5.1.2 Integer Compare und Logical Instructions 5.1.2.1 OR 5.1.2.2 AND 5.1.3 Integer shift and rotate instructions 5.2 Floating point instructions 5.3 Load and Store Instructions 5.4 Branch instructions 5.5 Various instructions 6 Application Binary Interface (SVR4 ABI) search Search Go Search resources Salesforce AppExchange salesforce.com/A… Customize Your Salesforce w / Apps to Boost Productivity! Try Today. community Hackmii Other sites Introduction This introduction for PowerPC assembler assumes that you are somewhat familiar with the Intel assembler. It is not written as a tutorial for beginners in assembly programming. Hopefully it is possible to understand this tutorial if you just have programed in C before. This tutorial will allow you to write applications in PowerPC assembler. Disassembling compiled code is not covered, however, knowing assembler is a prerequisite to disassemble code. The PowerPC is a RISC (Reduced Instruction Set Computing) processor architecture. PowerPC is an acronym which shall stand for Performance Optimization With Enhanced RISC / Performance Chip or Power Performance Computing. The specification for it was released in 1993 and is a 64-bit specification with a 32-bit subset. Almost all PowerPC processors are 32-bit now but feature a 64-bit data bus. The PowerPC was developed jointly by Apple, IBM and Motorola (now named Freescale). There are many different PowerPC processors available. Apple has been using the PowerPC in the Macintosh systems, IBM is using it in its RS/6000 and pSeries computers und Nintendo used it in its Gamecube and in Wii playstations. There are many embedded applications using the PowerPC. The PowerPC is a Superscalar microprocessor which means it has separate execution units. This are an integer unit, a floatingpoint unit, a branching unit, and even more depending on the processor type. These units can execute instructions in parallel within one clock cycle. toolbox What links here Related changes Special pages Printable version Permanent link The registers The PowerPC has many more registers than the Intel processors and these are named differently. All registers are 4 bytes or 32bits long on the 32-bit versions of the PowerPC. There are 32 (0-31) General Purpose Registers (GPRs or rX), 32 Floating point registers (FPRs or fX) and special purpose registers (SPRs) like the program counter PC or IAR (instruction address register). This keeps track which instruction needs to be executed next. There is a link register (LR) which can hold the address of a procedure for branch instructions, the condition register (CR) which has eight (0-7) 4 bit fields holding the result of e.g. a compare instruction. The count register for loops is called CTR. XER is the fixed-point exception register. FPSCR is the floating point status and control register. http://wiibrew.org/wiki/Assembler_Tutorial 1 / 11 0. 4.16 bits Word .13. You have to read the data into a register first and then store the contents of the register at the destination address in memory.init zero wordvar: . Mnemonics are specializations of a more general instruction. A mnemonic may have two parameters and this will be converted by the assembler to an instruction which may require three or more parameters.0. Integer instructions Floating point instructions Load and store instructions Branch and flow control instructions Various instructions The most common instructions of each group will be discussed here.15 #an array of five variables of one byte each endof_fivebytevar: #specifies the address immediately following the array stringvar: . TASM etc.Assembler Tutorial . Here are examples how to define variables. 2.org/wiki/Assembler_Tutorial 2 / 11 .set GPR0.init zero shortvar: .32 bits An integer value of 12 can also be specified as 0x0C in hexadecimal or01100 in binary.GPR0. They are defined for frequently used instructions.init to "Hello" plus newline . As an example for an addi instruction this 32-bit integer is divided in the following fields: Opcode: 6 bits Source register: 5 bits Destination register: 5 bits Immediate value: 16 bits So to fill a 32bit register with an immediate value you have to use two instructions moving 16 bits each. Without defining constants the assembler will also accept addi %r0.0 in the code.byte 11. These will be replaced by the assembler before assembling the code. They are used as simplified instructions for easier coding of assembly language programs. Instructions and Mnemonics Assembler instructions for Intel processors have up to two parameters separated by a comma. since the registers are specified as numbers just like immediate values in the instructions. This design shall allow the processor to operate more efficiently. Typically the first parameter is modified with the second. however.-stringvar #length of stringvar Constants The AS assembler allows to define constants.short 0 #length of two byte . The most significant byte (MSB) value is stored at the memory location with the lowest address. Variables The 32-bit version of the PowerPC supports the following data sizes: Byte .WiiBrew 04/11/2014 On the PowerPC you cannot move data from one memory address to another. bytevar: . This can enhance the readability of the code. Example: . This will replace all occurences of GPR0 in the code by the number zero.g. The PowerPC uses fixed-length 32-bit instructions.byte 0 #length of one byte .string "Hello\n" #string variable .long 0 #length of four byte .size stringvarlen. Variables are defined either in the data section or in the bss section which takes uninitialised data only.0 can be written as addi GPR0. The available instructions for the PowerPC can be grouped as follows: 1. So the bit numbering is reversed compared to an Intel processor. So using constants e. The PowerPC uses the big-endian format to store data in memory. 3.14. For the PowerPC. Samples of mnemonics can be found among the described instructions below. In case of a 64bit processor you need even more instructions since you have to shift the bits here too. The name of the variable is always set as a label followed by a colon.%r0. 5.8 bits Halfword . the instruction addi 0.0 This will define the constant "GPR0" having the value zero. . http://wiibrew.init zero fivebytevar: . the first operand is used as the destination register and there can be up to five parameters separated by commas. The AS assembler will do this for Intel processors in the opposite direction compared with MASM.12. ADD Syntax: add rD.3. 5.6.0.: . These are explained below.5. This is the case for several instructions. To improve the readability of the code you can define constants for the registers.3.1..like an Intel move instruction.0. To move a pointer to an address of a variable or function into a register there are the @ha/@h and @l modifiers available.hello@ha addi 3.hello@l With these two instructions the absolute 32-bit address of the string variable hello is moved into the GPR 3 register.2.4 In this example GPR6 and the value 4 are added and the result is put into GPR3.. . Mnemonics for the ADD instruction The following mnemonics are converted into ADD instruction by the assembler: LI . Example: addis 3.0.6.g. In effect the dot adds a cmpwi rD. 2.set r1. It adds a 16-bit signed integer (SIMM) to register rA. e.Add Immediate Syntax: addi rD.SIMM This command adds a 16-bit signed integer (SIMM) to register rA and puts the result into the register rD (destination).6. Example: add 3.set r0.org/wiki/Assembler_Tutorial 3 / 11 .6. If the second parameter is a zero here this does not mean a GPR0 but the value zero.rA. To achieve this you have to apped a dot to the instruction. . If the second parameter is a zero this does not mean a GPR0 but the value zero. If you then execute an addi 3. If you append these to the variable name you get the lower (@l) 16 bit of the absolute 32-bit address of the variable and with @ha you get the higher 16 bit of the absolute 32-bit address.set r4. ADDI .3 In this example GPR6 and GPR3 are added and the result is put into GPR3.4 This sets GPR3 to the value 4.4 In this example GPR6 and GPR4 are added and the result is put into GPR3. Example: add 3. 3.set r5. Example: addis 3. .set r3.Load Immediate http://wiibrew.0 instruction to the ADD instruction. Then the above command can be written as: addi r3.0. As you can see the registers are specified as a number and the integer is specified as a number. These bits will then reflect a signed comparison of the result to zero.3.. So add. then GPR3 is shifted 16 bits to the left and the result is put into GPR3. .rA. ADDIS .Add Immediate Shifted Syntax: addis rD. Example: addi 3.4.set r6. 4. ADD.rB This command adds two registers (rA and rB) and puts the result into the register rD (destination).4 In this example GPR3 and the value 4 are added.WiiBrew 04/11/2014 Integer Instructions Integer Arithmetic Instructions ADD This instructions has several variants: 1. then shifts left register rA by 16 bits and then puts the result into the register rD (destination). .0. . . . Instead of addis/addi the mnemonics lis/la are often used. A dot can be added to many PowerPC instructions.4 command GPR3 will contain 0x00040004 in hexadecimal.4 You can also use the addi command as a move instruction: addi 3. Otherwise the lower 16 bits would be cleared again by the addis command.Assembler Tutorial . The lower 16 bits are cleared by this command. Example: add 3. will set the CR bits 0-3 (CR0) in the CR register..ADD with CR Update Contrary to the Intel processors the ADD instruction will not modify any flags.rA. This will then contain 0x00040000 in hexadecimal.r6.set r2. So to fill a 32 bit register with an immediate 32-bit value you first have to use addis to fill the upper 16 bits and then addi to fill the lower 16 bits.4 Here the value in GPR4 is moved into GPR3 .SIMM This command is used to add a 16-bit immediate value to the upper 16 bits of a 32bit register. rA.SIMM Example: subfic 3.Divide http://wiibrew.100 Sets GPR3 to 100 and clears the higher 16 bits. SUBF . SUBF Syntax: subf rD.Assembler Tutorial .5 This will multiply the contents of GPR4 with the integer 5 and place the lower 32 bits of the result in GPR3. To load an immediate 32-bit value in a register you can use: lis 3.5 This will multiply the contents of GPR4 and GPR5 and place the lower 32 bits of the result in GPR3. 3.SIMM Example: mullh 3.value = ori rA.100(9) Adds 100 to the address in GPR9 and loads the result in GPR3.100 Sets higher 16 bits of GPR3 to 100 and clears the lower 16 bits.Load Immediate Shifted Syntax: lis rD.Subtract From 1.4.rA.WiiBrew 04/11/2014 Syntax: li rD.5 This will multiply the contents of GPR4 and GPR5 and place the higher 32 bits of the result in GPR6.0.Multiply Low Immediate Syntax: mulli rD.UIMM (UIMM = unsigned integer value) So OR immediate can be used to load an immediate too as long as the value is unsigned.rB Example: mullw 3.5 This will subtract GPR4 from signed integer value 5 and place the result in GPR3.Multiply Multiplying two 32-bit values will often result in a 64-bit value. LIS .Load Address Syntax: la rD. As a side note this is also equivalent: li rD.0. 2.4. MULLI .rB Example: subf 3. So the higher 32 bits if any . MULLW . DIV . So there are separate instructions to put the 64-bit result into two 32bit registers: 1.d Example: la 3.Multiply High Word Syntax: mullh rD.200 This loads 100 into the higher 16 bits and 200 into the lower 16 bits. 2.rA.value Example: li 3.0.value This is equivalent to addis rD.rA. MUL .4. CRO is modified.d(rA) This is equivalent to addi rD.rA. Subfic .5 Similar to the ADD instruction SUBF will subtract GPR4 from GPR5 and place the result in GPR3. LA .Subtract from Immediate Carrying Syntax: subf rD.4.4.rB Example: mullh 6.rA.Multiply Low Word Syntax: mullw rD.value Example: lis 3.0.are lost.value This is equivalent to addi rD.100 ori 3. MULLH .org/wiki/Assembler_Tutorial 4 / 11 . Assembler programmers somehow design their tasks so that they only need to multiply and divide by powers of two.org/wiki/Assembler_Tutorial 5 / 11 . 3.1 This will move the value in GPR1 to GPR31. Integer Compare und Logical Instructions 1.4.UIMM Example: ori 3.Compare Syntax: cmp crfD.g. Mnemonics for OR MR .Compare Immediate Syntax: cmpi crfD.L.move [to] register Syntax: mr rA. If rA<4 then bit 0 of CR7 will be set. ORIS .rB Example: or 3. (+dot) will update CR too. 4.SIMM This is equivalent to cmpi crD. The remainder is lost. The second parameter has to be set to zero for 32bit processors.rS. as a breakpoint for a debugger.rA.rB Example: cmp 7.rA.3.0.rS.0. This way they can use the shift instructions instead of multiply and divide.rA.5 This instruction will OR the contents of GPR4 with the unsigned integer 5 and place the result in GPR3. Mnemonics for CMP Sometimes the following mnemonics are used: CMPWI .Assembler Tutorial .SIMM Example: cmpi 7.5 This will divide the contents of GPR4 with the contents of GPR5 and place the result in GPR3. 2. The variant OR.rA. If rA=4 then bit 2 of CR7 will be set.rB Example: divw 3.Compare Logical word immediate Syntax: cmplwi crD. If rA=rB then bit 2 of CR7 will be set.3.UIMM (UIMM = unsigned integer value) OR 1.5 This instruction will OR the contents of GPR4 and GPR5 and place the result in GPR3.0 can be used as a NOP (no operation) instruction.L.0.0.SIMM CMPLWI .4.WiiBrew 04/11/2014 divw . ori 0.UIMM Example: oris 3.rS.4. If rA<rB then bit 0 of CR7 will be set.rS Example: mr 31. 3.OR Immediate Syntax: ori rA.5 This instruction will OR the upper 16 bits contained in GPR4 with the unsigned integer 5 and place the result in GPR3. ORI .0.4.rS. 2.rA.compare word immediate Syntax: cmpwi crD. CMPI . CMP . This could be used e.Divide Word Syntax: divw rD.4 This will compare the signed contents of the GPR3 register with the value 4 and set the CR7 field of the CR register accordingly.rA.4 This will compare the signed contents of the GPR3 and GPR4 registers and set the CR7 field of the CR register accordingly. The second parameter has to be set to zero for 32bit processors.rS This is equivalent to: or rA.OR Immediate Shifted Syntax: ori rA. OR Syntax: or rA. http://wiibrew. If rA>rB then bit 1 of CR7 will be set.UIMM This is equivalent to cmpli crD. If rA>4 then bit 1 of CR7 will be set.rA. 24. the CR register is updated.5.ME Example: rlwinm 3.31 Here the contents in GPR4 will be rotated left by 5 bits (the immediate value of 5 . RLWINM .5 The contents of the GPR4 register are shifted right by the value placed in the low-order six bits of the GPR5 register.rB Example: slw 3.Shift left word Syntax: slw rA.29.5 This instruction will AND the contents of GPR4 and GPR5 and place the result in GPR3. .5 This instruction will AND the upper 16 bits contained in GPR4 with the unsigned integer 5 and place the result in GPR3.SH.Rotate Left Word Immediate then AND with Mask Syntax: rlwinm rA. The higher 16 bits will be cleared.0. In effect all but the last two bits of GPR4 are cleared in this example. SRW . 3. 4. The result will then be0011100 or 28. rA.rS.0b00000011 This instruction will AND the contents of GPR4 with the unsigned integer 3 (binary 000011) and place the result in GPR3.rS.Shift right word Syntax: srw rA. AND Syntax: and rA. Mnemonics for shift SLWI .4. Since this instruction ends with a dot.0b11111111 rlwinm 3.Assembler Tutorial .3.4. The lower 16 bits will be cleared. If the third parameter is a zero there is no rotation and this command is just used as an AND mask.rS. Use the shift mnemonics for that which are described below. The 32-bit result is placed in GPR3.4. 3. In this example the begin is 0 and the end is 31. The 32-bit result is placed in GPR3.org/wiki/Assembler_Tutorial 6 / 11 .24 will clear all bits except bit 24 (big-endian format) in register GPR3. So if you have a value of 31 which is0011111 and you want to clear the lower two bits you have to AND this with a mask of 0.AND Immediate Syntax: andi.Shift Left Word Immediate http://wiibrew. This is not equal to a division by 2 since a bit may be moved into the sign bit by the rotation.0.0. 4. rA. the CR register is updated.4.4.UIMM Example: andis.31 will rotate GPR4 right by one bit. This is often done by gcc since this allows to execute AND with an immediate 32-bit value. 2.UIMM Example: andi.WiiBrew 04/11/2014 AND 1.4. A rotate right can be done by specifying a value of 32-n as the third parameter. Integer shift and rotate instructions 1. The fourth parameter specifies the beginning of the 1-bits in the mask and the fifth parameter specifies the end of the 1-bits in the mask. ANDI. NAND etc. ANDIS.rS. After rotating GPR4 and before placing the result into GPR3 the value is ANDed with the mask specified in the last two parameters.MB.rS.rB Example: srw 3.rB Example: and 3. So register GPR3 will then contain 128 or10000000. So rlwinm 3. So all 32 bits are set in the AND mask. 3.rS.4. Then bits 30 and 31 are set to zero in the mask and these bits will be cleared in the value of 31.5 The contents of the GPR4 register are shifted left by the value placed in the low-order six bits of the GPR5 register. . Example: li 3. SLW . There are equivalent instructions for XOR. Since this instruction ends with a dot.31.AND Immediate Shifted Syntax: andis. 3. This causes no bits to be cleared by the mask. 2. The PowerPC stores the data in big-endian format.parameter three) and the result placed into GPR3. Shift Right Word Immediate Syntax: srwi rD.Floating Move Register Syntax: fmr frD.rS.Load Word and Zero Syntax: lwz rD.4.5 Shifts GPR4 right by 5 bits and places the result in GPR3.frB Copies the contents of the floating-point register frB into the Floating-Point Status and Control Register (FPSCR) under the control of the field mask in FM. You cannot copy directly from one memory location to another. 4. SRWI .0(4) Stores the doubleword of data in the floating-point register FPR3 at the location in memory specified in GPR4. 1. STFS .WiiBrew 04/11/2014 Syntax: slwi rD. 3.org/wiki/Assembler_Tutorial 7 / 11 .0(4) Loads the word of data from the location in memory specified in GPR4 into floating-point register FPR3 and thereby converting it to floating-point double-precision.32 – n.Load Floating-Point Double Syntax: lfd frD. Load and Store Instructions The PowerPC allows you to move data from register to memory and from memory to register.Move to FPSCR Bit 1 Syntax: mtfsb1 crbD Example: mtfsb1 4 Sets bit 4 of the FBSCR register to 1.Store Floating-Point Single Syntax: stfs frS.4.5 Shifts GPR4 left by 5 bits and places the result in GPR3. 7.rS.d(rA) Example: stfd 3.frB Example: fmr 3.n. 5. 6.0(4) Converts the contents of FPR3 to single-precision and stores it at the location in memory specified in GPR4. LWZ . FMR .d(rA) Example: lwz 3. LFS . MTFSB1 .0.Assembler Tutorial . This is equal to dividing GPR4 by 32 (2**5).rA.4 The integer value in the FPR4 will be moved into the FPR3 (FPR=Floating point register) 2. There are equivalent instructions for reading a byte (LBZ) and a halfword (LHZ) or storing a byte (STB) and a halfword (STH).31–n Example: slwi 3. This is equal to multiplying GPR4 with 32 (2**5). Floating point instructions 1.d(rA) Example: lfd 3.Store Floating-Point Double Syntax: stfd frD. STFD.SIMM (SIMM<32) This is equivalent to: rlwinm rA.31 Example: srwi 3. MTFSF .10(4) http://wiibrew.rA.Load Floating-Point Single Syntax: lfs frD.Move to FPSCR Fields Syntax: mtfsf FM.0(4) Loads the doubleword of data from the location in memory specified in GPR4 into floating-point register FPR3. Described here are the instruction for word operations.d(rA) Example: lsd 3. LFD.d(rA) Example: stfs 3.n.SIMM (SIMM<32) This is equivalent to: rlwinm rA. 10(4) This will store the value in GPR3 at the memory location specified in GPR4 plus an "offset" of 10.SPR Example: mfpsr 3.5 This will store the value in GPR3 at the memory location computed by adding the values in GPR4 and GPR5. 3. 6.Load Word and Zero Indexed Syntax: lwzx rD.10(4) This will store the value in GPR3 at the memory location specified in GPR4 plus an "offset" of 10. 2. MFSPR .Move from Special-Purpose Register Syntax: mfspr rD.Store Word Syntax: stw rD.rB Example: lwzx 3. 4.5 Here the word at the memory address computed by adding the values in GPR4 and GPR5 is read and placed in GPR3.Move to Special-Purpose Register Syntax: mtspr SPR.Store Word Indexed Syntax: stwx rD.org/wiki/Assembler_Tutorial 8 / 11 .4.d(rA) Example: lwzu 3. MTSPR . http://wiibrew. Mnemonics for MFSPR and MTSPR a) MFLR . This instruction is frequently used to set up a stack frame.rB Example: stwx 3.rA. STWX . So the value of this register first has to be moved into a GPR register.Load Word and Zero Update Syntax: lwzu rD. Then the computed memory address is placed in GPR4. 8.Move to Count Register Example: li 4.d(rA) Example: stwu 3. LWZX .4. 10. 5. b) MTLR .d(rA) Example: stw 3. 7.100 mtctr 4 The count register is set to 100 via the GPR4.Store Word with Update Syntax: stwu rD.rS Example: mtspr 912.Move to Link Register Example: mtlr 0 Here the value in GPR0 is written into the link register. registers.rA.3 Here the value in GPR3 is moved to the special register 912. In the case of LBZ and LHZ the higher bits are cleared to zero when moving the value into a 32-bit register. CTR etc. STWU .10(4) This will read the word at the memory location specified in GPR4 plus an "offset" of 10 and place it in GPR3.Move from Link Register It is not possible to use the standard instructions on the link register. LWZU .Assembler Tutorial . Example: mflr 0 This will read the value in the link register into GPR0. Then the computed memory address is placed(updated) in GPR4. C) MTCTR .920 Here the value from the special register 920 is moved to GPR3. XER.WiiBrew 04/11/2014 This will read the word at the memory location specified in GPR4 plus an "offset" of 10 and place it in GPR3. There are equivalent instructions for the CR. You cannot load an immediate value into the CTR. 9. STW . This instruction can be compared to a "near jmp" in Intel syntax.if statements..testlabel bge . The bl instruction will save the next instruction address in the link register after branching to allow the called subroutine to return.0. If bl is executed in a subroutine itself. BDNZT .Branch Decrement not Zero Syntax: bdnz target Example: li 4. Then the bdnz instruction will decrement the CTR register and branch to looplabel as long as the CTR (count register) is not zero..branch if equal | example: beq 7.5 instruction which compares the value in GPR3 with the integer 5 and places the resulting flags in the CR7 field of the CR register.branch if not equal | example: bne 7.branch if greater of equal | example: bge 7. Syntax: bdnzt BI.100 /* Compare value in GPR4 with 100 */ bne else_label /*if not 100 goto else */ .Branch on Link Register This instruction is frequently used as a return command from a subroutine or function.. endif_label: 3..some statements.testlabel Example: cmpwi 4..else statements.branch if less than | example: blt 7.. BLR .testlabel bgt . bdnz looplabel In this example the count register (CTR) is loaded with the value 100 first via GPR4. the link register value has to be saved first before executing a bl instruction since that register will be overwritten by the bl instruction.testlabel bne . 1.branch if greater than | example: bgt 7. Conditional branch instructions (mnemonics) Following a cmpi 7. B .target Example: li 4. The link register is filled with the 32-bit return address when a bl (branch then link) instruction is executed (see above). cmpwi 5.testlabel blt . 100 mtctr 4 looplabel: .. Otherwise it will just continue.org/wiki/Assembler_Tutorial 9 / 11 ..testlabel ble .branch if less or equal | example: ble 7. 6. Its absolute address has to be loaded into the link register before executing the bl instruction.Branch then Link Syntax: bl target_addr Example: bl testsubroutine This instruction can be used to call a subroutine or function. b endif_label /* jmp over else part */ else_label: . beq . BL . The blr instruction will read that return address from the link register and return to the next instruction in the calling routine.Assembler Tutorial . 100 mtctr 4 looplabel: ..10 http://wiibrew.Branch Syntax: b target_addr Example: b testlabel Here the execution will continue at the label "testlabel". 4.WiiBrew 04/11/2014 Branch instructions The PowerPC branch instructions are similar to the Intel Processor's jmp and call commands.. 5...... If the condition is true the program will continue at "testlabel" within the code segment..Branch Decrement not Zero True This mnemonic adds a conditional branch test to the BDNZ instruction.some statements. 2. BDNZ .3. the following conditional branch instructions can be executed. 7.6 instruction. volatile. Application Binary Interface (SVR4 ABI) On Intel processors external subroutines and functions are usually called by pushing the arguments to be passed to the subroutine on the stack. Here the Sytem V R4 ABI or SVR4 ABI is described since the GCC compiler for 32bit PowerPC's uses this ABI. f31 lr ctr xer fpscr cr0 cr1 cr2 . The PowerPC has lots of registers but none is defined by the PowerPC architecture as a stack pointer.8th int args volatile. To enable interoperatibility between different compilers and object files or libraries an ABI has been defined.2nd ints volatile.crbA.. If this is not the case this bit can be cleared using the CRXOR 6.. Then the bdnzt instruction will decrement the CTR register and branch to looplabel as long as the CTR (count register) is not zero. r11 . The subroutine then sets up a stack frame and reads the parameters from the stack. 9.rS. pass 1st float arg. CLRLWI .Clear left word immediate Syntax: clrlwi rA.. r13 r14 . CRXOR . may be used by function linkage small data area pointer saved volatile volatile.Return from interrupt returns from an interrupt service routine Various instructions 1..looplabel In this example the count register (CTR) is loaded with the value 100 first via GPR4. 8.6. f9 . f14 .8th float args volatile saved saved. the instruction will also test if the condition is TRUE. BEQLR . may be used by function linkage stack pointer reserved for system volatile. So if the cmpwi instruction has determined that GPR5 has the value 10.. pass 2nd . f0 f1 f2 . There a slightly different versions of ABI's available. RFI .16 Clear the high-order 16 bits of rS and place the result into rA. cr5 . volatile. The registers are used as follows: r0 r1 r2 r3 . However.. r5 .Branch then Link if not Equal Syntax: bnelr target_addr This mnemonic can be used to call a subroutine or function if the preceeding cmp instruction determined NOT equal. return 1st float volatile.. return address volatile volatile volatile volatile volatile saved volatile r4 r10 r12 r31 f8 f13 f30 cr4 cr7 http://wiibrew. GPR1 is specified to be used as the stack frame pointer. pass 1st . pass 3rd .org/wiki/Assembler_Tutorial 10 / 11 .. The programmer can select any register to be a stack register. the loop will be terminated before CTR has reached zero..6 Clears bit 6 of the CR register 2.2nd int args.crbB Example: crxor 6.Condition Register XOR Syntax: crxor crbD.WiiBrew 04/11/2014 bdnzt eq.6. The SVR4 ABI specifies that arguments are not passed on the stack but in registers beginning with GPR3. static chain if needed. Since the PowerPC has several instruction queues this can make sure that an instruction is executed before the next in the code.Branch then Link if Equal Syntax: beqlr target_addr This mnemonic can be used to call a subroutine or function if the preceeding cmp instruction determined equal. 3. BNELR .Assembler Tutorial . return 1st . ISYNC Delay all following instructions until all previous instructions required for context. Bit 6 of the CR register indicates that a floating point argument is passed in the registers. Category: Development This page was last modified on 29 July 2013. To free the stack frame again the SP has to be set back to point to the back chain field of the previous stack frame. SP+28. SP+36 In the "Hello world" example GCC saved GPR31 in SP+36.-40(1) instruction. Hereby the current stack pointer passed from the calling function in GPR1 is stored at SP-40 which then becomes the back link field. In its own stack frame the called subroutine will store the link register in the "LR save word" field. To set up this stack frame the subroutine first decrements the passed SP. SP+32. In this field the stack pointer of the previous stack frame set up by the calling function has just been stored before setting SP to SP-40.44(1) instruction after moving the link register into GPR0. - Privacy policy About WiiBrew Disclaimers http://wiibrew. SP+16. GPR3 in SP+28 and GPR4 in SP+24.Assembler Tutorial .1. SP+24. Subtracting two for the back chain and LR save word fields leaves eight words to save data in the stack frame. The ABI also defines the stack frame which should be set up by the called subroutine. SP+20. This a table showing how it shall be set up: SP----> +---------------------------------------+ | back chain to caller | +---------------------------------------+ | saved LR | +---------------------------------------+ | Parameter save area (P) | +---------------------------------------+ | Alloca space (A) | +---------------------------------------+ | Local variable space (L) | +---------------------------------------+ | saved CR (C) | +---------------------------------------+ | Save area for GP registers (G) | +---------------------------------------+ | Save area for FP registers (F) | +---------------------------------------+ old SP->| back chain to caller's caller | +---------------------------------------+ 0 4 8 8+P 8+P+A 8+P+A+L 8+P+A+L+C 8+P+A+L+C+G GCC uses the . So the calling function must save these registers before calling a subroutine. GCC writes the link register value into the "LR save word" field of the preceeding stack frame with the stw 0.align 2 command to align the SP to two words or 8 bytes. GCC will call its exit function instead. the back link field. SP+12. If the stack frame has a size of 40 bytes. This is done using the stwu 1.40 will do this in our case here. This depends how many local variables shall be put into the stack frame. These fields could be addressed by: SP+8. This sets up a linked list of stackframes. lets assume the SP is decremented by 40 bytes here. saved means that a called function must restore its value before returning. Following that this instruction will set the SP in GPR1 to point to GPR1-40. this results in 10 fields of word size. It allows to follow this list and write into the preceeding stack frame. at 16:32. The instruction addi 1.WiiBrew 04/11/2014 Volatile means that a called function does not have to preserve its value when it returns.org/wiki/Assembler_Tutorial 11 / 11 .