0ELECTRONIC CIRCUITS - II (EE 352) LAB MANUAL Prepared by Sk M Subhani Lecturer in ECE T. Srinivasa Rao Lecturer in ECE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING BAPATLA ENGINEERING COLLEGE, BAPATLA. Electronic Circuits II Bapatla Engineering College, Bapatla. 1 INDEX 1. Two Stage RC coupled Amplifier. 2. Design of voltage shunt feed back amplifier. 3. Clacc B push pull amplifier. 4. Complimentary symmetry push pull amplifier. 5. Design of RC phase shift oscillator. 6. Design of LC oscillators. a.Colpitts oscillators. b.Hartley oscillators. 7. Design of series voltage regulator. 8. Linear wave shaping. 9. Non-linear wave shaping. 10. Bistable multivibrator. 11. Monostable multivibrator. 12. Astable multivibrator. 13. Schmitt trigger. 14. UJT relaxation oscillator. 15. Blocking oscillator. 24 29 34 41 44 47 50 53 57 2 6 9 11 15 18 NOTE: A minimum of 10(Ten) experiments have to be performed and recorded by the candidate to attain eligibility for University Practical Examination. Electronic Circuits II Bapatla Engineering College, Bapatla. 2 1. RC COUPLED AMPLIFIER Aim: To plot the frequency response characteristics of two stages RC coupled amplifier. Apparatus Required: S. No Name of the Component/ Equipment 1 Two stage RC Coupled Amplifier Circuit Board 2 3 4 Cathode Ray Oscilloscope Signal Generator Regulated Power Supply 20 MHz 0 -1MHZ 0-30V,1A 1 1 1 ___ 1 Specifications Quantity. Theory: To improve gain characteristics of an amplifier, two stages of CE amplifier can be cascaded. While cascading, the output of one stage is connected to the input of another stage. If R and C elements are used for coupling, that circuit is named as RC coupled amplifier. Each stage of the cascade amplifier should be biased at its designed level. It is possible to design a multistage cascade in which each stage is separately biased and coupled to the adjacent stage using blocking or coupling capacitors. In this circuit each of the two capacitors C1 & C2 isolate the separate bias network by acting as open circuits to dc and allow only signals of sufficient high frequency to pass through cascade. Electronic Circuits II Bapatla Engineering College, Bapatla. 2. 3.axis. From graph calculate bandwidth. Apply supply voltage. Now feed an ac signal of 20mV peak-peak at the input of the amplifier with different frequencies ranging from 20Hz to 1MHz and measure the amplifier output voltage. Electronic Circuits II Bapatla Engineering College.3 Circuit Diagram: Fig A: Two stage RC Coupled Amplifier Procedure: 1. 4. Draw a graph with frequencies on X. Connect the circuit as per the circuit diagram.axis and gain in dB on Y. Vo. 5. . Now calculate the gain in dB for various input signal frequencies using AV = 20 log10 (V0/VS). Bapatla. Vcc= 12V. VS = 20mV peak-peak Output Input Frequency S. 3.5 KHz Gain bandwidth product = Av (B. The applied voltage and current should not exceed the maximum ratings of the given transistor.56dB Lower cutoff frequency (Fl) = 4. Connections must be given very carefully. .W) = 30. Av = 20log(Vo/Vs) (dB) Model Graph: Observations: Maximum gain (Av) = 52. No (Hz) Voltage peak-peak Vo (mV) Gain. Bapatla. Readings should be noted without any parallax error. Result: Frequency response of RC Coupled Amplifier Characteristics of was observed.4 Tabular Form: Input voltage.W) = (FH – FL) = 575.5 KHz Upper cutoff frequency (FH) =580 KHz Band width (B. 2. Electronic Circuits II Bapatla Engineering College.24M Hz Precautions: 1. .47µF.10µF 20 MHz 3 1 1 6 Specifications Quantity. Bapatla.2K . Apparatus Required: S.1K 3 4 Capacitor Cathode Ray Oscilloscope 5 6 Signal Generator Regulated Power Supply 0 -1MHZ 0-30V. .8.5 2.68K . 506 . CIRCUIT DIAGRAM: Electronic Circuits II Bapatla Engineering College.VOLTAGE SHUNT FEEDBACK AMPLIFIER Aim: To plot the frequency response characteristics of voltage shunt feed back amplifier. No Name of the Component/ Equipment 1 2 Transistor Resisters BC107 100 .220 .1A 1 1 10µF. Bapatla. .6 MODEL WAVE FORMS Electronic Circuits II Bapatla Engineering College. .No. By removing the feed back resistor (Rf) in the amplifier ckt .No. Calculate the voltage gain in Db. 2. By keeping V i to be constant value and vary its frequency such that note down the corresponding output! Signal’s amplitude and tabulate them. 4. 6. 3. Now plot the graphs for gain in dB Vs frequency and calculate themaximum gain bandwidth with feedback & with out feedback and compare the values OBSERVATION: At input voltage (Vi) = 50mV With Feedback Av in Sl.repeal [lie above procedure.7 PROCEDURE: 1. Frequency (Hz) Vo(V) Av=Vo/Vi dB With out Feedback (by removing Rr in the circuit) Sl. Apply an input signal V s (sinusoidal) and measure Vi to be min value to get an undistorted output waveform. Frequency (Hz) Vo(V) Av=Vo/Vi Av in dB CALCULATIONS: With out feed back (when Rf is removed) & With feed back (when Rf in the ckt) 1) Av max = 2) Band width = f2-f1 = Result: Hz Electronic Circuits II Bapatla Engineering College. Connections are made as per the circuit diagram. Bapatla. 5. 8 3. Apparatus: Sl.No Name of the Component /equipment 1 2 3 5 6 7 Power transistor (BD139) Resistor (designed values) Center tap Transformers Function Generator Cathode Ray Oscilloscope Regulated Power Supply Specifications VCE =60V VBE = 100V IC = 100mA hfe = 40 -160 Power rating=0. Bapatla.5W Carbon type Operating temp =ambient 0 -1MHZ 20MHZ 0-30V.CLASS B PUSH-PULL AMPLIFIER Aim: To Design a Class B Push pull power amplifier. .1Amp Qty 2 4 2 1 1 1 CIRCUIT DIAGRAM: CLASS B Push-pull power amplifier Electronic Circuits II Bapatla Engineering College. Connect the circuit as per the circuit diagram. . 3. Apply input voltage and find the input power & output power. Result: Class B Push-Pull power amplifier is designed &Efficiency is calculated. Bapatla. Observe the input and output wave forms across each transistor on CRO. Electronic Circuits II Bapatla Engineering College. Calluculate efficiency of amplifier.9 Design Equations: Power input: Pi = 2 Im Vcc / ∏ Power out put: p = Im Vm / 2 = (Im/ 2)(Vcc − V min) Collector citcuit Efficiency= ( P / Pi ) X 100 = (∏ / 4)(Vm / Vcc) = ∏ / 4(1 − V min ) X 100 Vcc Procedure: 1. 2. 4. 5W Carbon type Electrolytic type Voltage rating= 1. The same signal gets applied to the base of the Q2. 4 Compare simulation results with practical results. Apparatus: Sl. During the negative half cycle of the signal the transistor Q2 p-n-p gets biased into conduction. 2. Hence only Q2 conducts during negative half cycle of the input. Develop the hard ware for design circuit. In the positive half cycle of input signal the transistor Q1 gets driven into active region and starts conducting. Design a complementary symmetry power amplifier to deliver maximum power to 10 Ohm load resistor.No Name of the Component /equipment 1 2 3 4 5 6 Power transistor (BD139) Resistor (designed values) Capacitors(designed values) Function Generator Cathode Ray Oscilloscope Regulated Power Supply Specifications VCE =60V VBE = 100V IC = 100mA hfe = 40 -160 Power rating=0.10 4. 3. While Q1 gets driven into cut off region. it . during the positive half cycle. producing negative half cycle across the load. Simulate the design circuit.1Amp Qty 1 4 3 1 1 2 Theory: In complementary symmetry class B power amplifier one is p-n-p and other transistor is n-p-n.6v 0 -1MHZ 20MHZ 0-30V. . CLASS B COMPLEMENTARY SYMMETRY POWER AMPLIFIER Aim: 1. Electronic Circuits II Bapatla Engineering College.remains in off condition. Bapatla. 35K Capacitor calculations:To provide low reactances almost short circuit at the operating frequency f=1KHZ.1 CC1 = CC2 = 1/ 2 π f XCC1 = 11. .11 Circuit Diagram: Design Equations: Given data: PL (MAX) =5 W. Bapatla. RL= 10 . XCC1 = XCC2 = (R \\ RB) / 10 = (150)(2350)/(10)(2550) = 14.R / (R+RB) 0. f = 1KHZ 1. assume R = 150 VBB=VCC.6V . Selection of VCC:PL (MAX) = VCC ² / 2RL VCC ² = PL (MAX) 2RL = 100V VCC = 10V Selection R and RB:VBB = VBE = 0.6 = 10*150/ (150+RB) RB = 2.28µF Electronic Circuits II Bapatla Engineering College. Calculate the power sensitivity at a maximum power o/p using the relation. Apply the AC signal at the input and keep the frequency at 1 KHz and connect the power o/p meter at the output.12 Procedure: 1. Plot the graph between o/p power and load impedance. This is the value of optimum load. Select load impedance which is equal to 0V or near about the optimum load. . 2. Connect the circuit diagram and supply the required DC supply.R. Change the Load resistance in steps for each value of impedance and note down the output power. See the wave form of the o/p of the C.O.No Output Impedance( ) Input power (pi) (W) Output Power(po) (W) N=(Po)/( Pi) x100 Electronic Circuits II Bapatla Engineering College. 3. Bapatla. 4. Tabular Form: Simulation: Input power = 2 VCC2 / (πRL) = 6. From this graph find the impedance for which the output power is maximum.36W S. 5. Bapatla. Connections should be made care fully. . 4. Electronic Circuits II Bapatla Engineering College. 3.13 Practical: Input power = 360mW S. 2. Avoid loose connections. Result: Class B complementary symmetry amplifier is designed for given specifications and its performance is observed. Take the readings with out parallax error.No Output Impedance( ) Input power (pi) (mW) Output Power(po) (mW) N=(Po)/( Pi) x100 Model Graph: Precautions: 1. Simulation switch must be off while changing the values. Apparatus Required: S.01µF 4 5 6 Potentiometer Regulated Power Supply Cathode Ray Oscilloscope 0-10K 0-30V. Each RC section provides a phase shift of 600.100K .14 5.1A 20 MHz Theory: In the RC phase shift oscillator.6v 1 2 Resistors 56K .2K . The frequency of oscillations is given by F=1/2π RC (6+4K)1/2 Where. The output of amplifier goes to a feedback network consists of three identical RC sections. Thus a total of 1800 phase shift is provided by the feedback network.2.0. Electronic Circuits II Bapatla Engineering College.10K 1 3 2 3 1 1 1 3 Capacitors 10µF/25V . RC PHASE SHIFT OSCILLATOR Aim: To determine the frequency of oscillations of an RC Phase shift oscillator. The output of this circuit is in the same phase as the input to the amplifier. Bapatla. The phase of the signal at the input gets reverse biased when it is amplified by the amplifier. .5w Carbon type Electrolytic type Voltage rating=1. No Name of the Component/Equipment Specifications Quantity 1 Transistor( BC107) Icmax=100mA PD=300mw Vceo=45V Vbeo=50V Power rating=0. R1=R2=R3=R. the combination RC provides self-bias for the amplifier. C1=C2=C3=C and K=RC/R. Compare the theoretical and practical values. Switch on the power supply. Connect the circuit as shown in Fig A. .01µF) √6+4(0.59Hz Electronic Circuits II Bapatla Engineering College. Bapatla. 5. Measure the Amplitude and Frequency. 4. Plot the graph amplitude versus frequency Theoretical Values: f = 1 / 2 π RC √6+4K =1 / 2 π (10K) (0. 6.01) = 647. RC Phase shift Oscillator Procedure: 1. 2. 3. Connect the CRO at the output of the circuit. 7. Adjust the RE to get undistorted waveform.15 Circuit Diagram: Fig A. Electronic Circuits II Bapatla Engineering College.NO Theoretical Frequency(Hz) Practical Frequency(Hz) % Error Model Graph: Result: The frequency of RC Phase Shift Oscillator is determined.16 Tabular Form: S. . Bapatla. a transient current is produced in the tank circuit. the transistor provides the phase difference of 1800 between the input and output. Apparatus Required: S. Z1. HARTLEY OSCILLATOR Aim: To design a Hartley oscillator and to measure the frequency of oscillations. If terminal is at positive potential with respect to 3 at any instant. . The current in tank circuit produces AC voltages across L1 and L2 .No Name of the Component/Equipment 1. 3. and Z2 are inductors and Z3 is an capacitor. Capacitor C determine the frequency of the oscillator. 2. Bapatla. Thus the phase difference between the terminals 1 and 2 is always 1800. When the supply voltage +Vcc is switched ON. CE is a bypass capacitor CC1 and CC2 are coupling capacitors. it will be at zero potential.17 6A. Electronic Circuits II Bapatla Engineering College. As terminal 3 is earthed. The feedback network consisting of inductors L1 and L2 . and consequently damped harmonic oscillations are setup in the circuit. The frequency of oscillations is f = 1/2π√LC where L= L1 + L2. Hartley Oscillator Circuit Board Cathode Ray Oscilloscope Decade Inductance Boxes ___ 20MHz ___ 1 1 2 Specifications Quantity Theory: In the Hartley oscillator shown in Fig A. The resistors R and R2 and RE provide the necessary DC bias to the transistor. In the CE mode. then terminal 2 will be at negative potential with respect to 3 at the same instant. Therefore the total phase shift is 3600. Tabulate the results as below. Electronic Circuits II Bapatla Engineering College.18 Circuit Diagram:- Fig A: Hartley oscillator Procedure: 1. 3. . adjust the potentiometer RE on the front panel until we get an undistorted output. Compute fO = 1/T (RE can adjust the gain of the amplifier). Repeat the steps 2 to 4 for the second pair of inductors L1 and L2 . Calculate the theoretical frequency of the circuit using the formulae. 2. Switch on the power supply by inserting the power card in AC mains. Bapatla. 4. Connect one pair of inductors as L1 and L2 as shown in the dotted lines of Fig A. Observe the output of the oscillator on a CRO. 5. Note down the repetition period (T) of observed signal. Electronic Circuits II Bapatla Engineering College. Result: The frequency of Hartley oscillator is practically observed.7 1 S. Connections must be done very carefully.032 1 2 Model Graph: Fig B: Frequency of oscillations Precautions: 1.558 5.19 Tabular Form: Frequency . Bapatla. 2. Readings should be taken without parallax error. fo Condition L1 = L2 = 100mH L1 = L2 = 50mH Practical 3.246 4.No Theoretical 3.98 (KHz) % Error 8. . Thus the phase difference between the terminals 1 and 2 is always 1800. Cathode Ray Oscilloscope 20 MHz 1 ___ 1 Specifications Quantity Theory: In the Colpitts oscillator shown in fig 1. Therefore the total phase shift is 3600. and Z2 are capacitors and Z3 is an inductor. COLPITTS OSCILLATOR Aim: To measure the frequency of the Colpitts Oscillator Apparatus Required: S. Bapatla. The feedback network consisting of capacitors C1 and C2 . a transient current is produced in the tank circuit. When the supply voltage +Vcc is switched ON. The resistors R and R2 and RE provide the necessary DC bias to the transistor. . inductor L determine the frequency of the oscillator. Electronic Circuits II Bapatla Engineering College. No Name of the Component/Equipment 1. and consequently damped harmonic oscillations are setup in the circuit. As terminal 3 is earthed. it will be at zero potential. then terminal 2 will be at negative potential with respect to 3 at the same instant. Colpitts Oscillator Circuit Board 2. CE is a bypass capacitor CC1 and CC2 are coupling capacitors. the transistor provides the phase difference of 1800 between the input and output. Z1.20 6B. The current in tank circuit produces AC voltages across C1 and C2 . The frequency of oscillations is f = 1/2π√LC where 1/C = 1/C1 + 1/C2. If terminal is at positive potential with respect to 3 at any instant. In the CE mode. Adjust the potentiometer RE on the front panel until we get an undistorted output. Note down the repetition period (T) of observed signal. Compute fO= 1/T (RE can adjust the gain of amplifier).21 Circuit Diagram: Fig A: Colpitts Oscillator Procedure: 1. 3. Calculate the theoretical frequency of the circuit using formulae. Repeat the step 2 and 4 for the second pair of capacitors C1 and C2. 4. Electronic Circuits II Bapatla Engineering College. . Observe the output of the oscillator on a CRO. 5. Switch on the power supply by inserting the power card in AC mains 2. Connect one pair of capacitors as C1 and C2 as shown in the dotted lines of Fig A. Tabulate the results as below. Bapatla. 1µF 7.No Condition Theoretical Frequency (KHz) Practical frequency(KHz) %Error 1 C1=C2=0.01µF 22.117 7.727 0. . Bapatla.97 2 C1=C2=0.23 1. Readings should be taken without parallax error. Result: The frequency of Colpitts Oscillators is practically determined. Electronic Circuits II Bapatla Engineering College. 2.507 22. Connections must be done very carefully.22 Tabular Form: S.5 Model Graph: Precautions: 1. 1Amp Qty 1 1 Transistors (BC 107) 3 4 Resistors(designed values) Regulated power supply 1 1 Theory: A regulator is an electronic circuit which maintains a constant output irrespective of change in input voltage. that gets to the output. Series voltage regulator is one type of regulator. Apparatus: S. 2.No Name of the component/equipment 1 2 Zener diode (Bz6. The control element controls the input voltage.5w Carbon type Tolerance ±5% 0-30 V. VCEO =45v. SERIES VOLTAGE REGULATOR Aim: 1. 3. . Pd(min) =300mw Power dissipation=0. the control element is connected in series with the load . Design series voltage regulator to operate on supply of 15v. load resistance and change in temperature. The unregulated d.5v I c max =100ma. 4.c voltage is the input to the circuit. Simulate the design of regulator. If in a voltage regulator circuit . Compare the practical results with theoretical results.23 7. In a transistorized series feedback type regulator the output voltage is given by Vo = (1+R1/R2) (VBE2+Vz) Electronic Circuits II Bapatla Engineering College.5) Specifications Vz=6. Develop the hardware for design of voltage regulator. The sampling circuit provides the necessary feed back signal.then the circuit is called series voltage regulator circuit. Bapatla. The comparator circuit compares the feed back with the reference voltage to generate appropriate control signal. IB =1mA. IC2 = 3mA 5 6 I2 = I1-IB2 ( Since hfe = IC2/IB2 ) I2= 3. RL=VL/IL = 9/(40 X 10-3) = 225 VO=VL=R3I3+VZ R3=VL-VZ/I3 = 375 R1I1+VBE2+VZ=VO R1=VO-(VBE2+VZ)/I1 = 220 4 R2I2 = VBE2 + VZ R2 = 2.98K 7 Electronic Circuits II Bapatla Engineering College. IE1=I1+I3+IL = 48mA 3. Bapatla.97mA I4= IB1 + IC2 IB1 = IC1 / hfe1 (IC1 = IE1) I4 = 3. IZ = 1mA. .48mA Vi = I4R4 + VBE1 + VO R4 = 2.5V Vi =15V.04K 5. Assume the current flowing through the resistor R1 & R3 is 1/10 of the IL I1=I3=IL/10 =40mA / 10 = 4mA 2. hfe = 100.24 Circuit Diagram: Design Equations: Given data: VL= 9V. VZ = 6. IL = 40mA. 4. hfe=100 1. Bapatla. Apply the input voltage of 15V 3. . Keep the input Voltage constant. Plot the graph between Load current versus Load Resistance and Output Voltage versus Load resistance.No Load resistance RL (Ohms) Output Voltage (v) Output Current IL (mA) Electronic Circuits II Bapatla Engineering College. Vary the load resistance and measure the output Voltage and output current 4. Tabular forms: Simulation: S.25 Procedure: 1. Tabulate the readings 5. Connect the Circuit diagram as shown in the fig: 2. .No Load resistance (RL in Ohms) o/p voltage (v) o/p current IL (mA) Electronic Circuits II Bapatla Engineering College. Bapatla.26 Practical S. Connections should me made care fully. Take the readings with out parallax error. Bapatla. Electronic Circuits II Bapatla Engineering College. 2.27 Model graph: Precautions: 1. Result: A series voltage regulator of 9V output is designed and verified. . . it is called a high pass circuit. T=RC and T>>RC. ii) To observe the response of the designed low pass RC circuit for the given square waveform for T<<RC. An ideal low pass circuit is one that allows all the input frequencies below a frequency called cutoff frequency fc and attenuates all those above this frequency. Bapatla.28 8. Linear Wave Shaping Aim: i) To design a low pass RC circuit for the given cutoff frequency and obtain its frequency response.1) cutoff is set to occur at a frequency where the gain of the circuit falls by 3 dB from its maximum at very high frequencies the capacitive reactance is very small. For practical low pass circuit (Fig.2K . Electronic Circuits II Bapatla Engineering College. Since circuit attenuates low frequency signals and allows high frequency signals with little or no attenuation.16 K 0.T=RC and T>>RC. iv) To observe the response of the designed high pass RC circuit for the given square waveform for T<<RC.01µF 20MHz 1MHz 1 1 1 1 1 Specifications Quantity Theory: The process whereby the form of a non sinusoidal signal is altered by transmission through a linear network is called “linear wave shaping”. iii) To design a high pass RC circuit for the given cutoff frequency and obtain its frequency response. so the output is almost equal to the input and hence the gain is equal to 1. Apparatus Required: Name of the Component/Equipment Resistors Capacitors CRO Function generator 1K 2. . Vary the frequency of input signal in suitable steps 100 Hz to 1 MHz and note down the p-p amplitude of output signal. Bapatla.1 and apply a sinusoidal signal of amplitude of 2V p-p as input. Find the cutoff frequency fc by noting the value of f at 3 dB down from the maximum gain Electronic Circuits II Bapatla Engineering College.Connect the circuit as shown in Fig.29 Circuit Diagram: Low Pass RC Circuit : High Pass RC Circuit : Procedure: A) Frequency response characteristics: 1 . 4. 2. 3. Obtain frequency response characteristics of the circuit by finding gain at each frequency and plotting gain in dB vs frequency. Vo (V) Gain = 20log(Vo/Vi) (dB) High Pass RC Circuit: S. Sample readings Low Pass RC Circuit Input Voltage: Vi=2 V(p-p) S. Draw the input and output wave forms for different cases. 3. Vo (V) Gain = 20log(Vo/Vi) (dB) Model Graphs and wave forms Low Pass RC circuit frequency response: High Pass RC circuit frequency response: Electronic Circuits II Bapatla Engineering College. Bapatla. T=RC.T<<RC and observe the output in each case. Apply a square wave of 2v p-p amplitude as input.30 B) Response of the circuit for different time constants: Time constant of the circuit RC= 0. . 2. Adjust the time period of the waveform so that T>>RC.No Frequency (Hz) O/P Voltage.0198 ms 1.No Frequency (Hz) O/P Voltage. Bapatla.31 Low Pass RC circuit Electronic Circuits II Bapatla Engineering College. . frequency response and response at different time constants is observed. Verify the circuit connections before giving supply. Result: RC low pass and high pass circuits are designed. Take readings without any parallax error. 3. 2. . Electronic Circuits II Bapatla Engineering College.32 High Pass RC Circuit Precautions: 1. Connections should be made carefully. Bapatla. above or below certain levels as per the requirements. Thus the circuits which are used to clip off unwanted portion of the waveform.1A Quantity 1 1 1 1 1 Theory: The basic action of a clipper circuit is to remove certain portions of the waveform.33 9. The clipper circuits are also called limiters or slicers. Non Linear Wave Shaping-Clippers Aim: To obtain the output and transfer characteristics of various diode clipper circuits. Bapatla. Circuit diagrams: Positive peak clipper with reference voltage. V=2V Electronic Circuits II Bapatla Engineering College. . without distorting the remaining part of the waveform are called clipper circuits or Clippers. The half wave rectifier is the best and simplest type of clipper circuit which clips off the positive/negative portion of the input signal. Apparatus required: Name of the Component/Equipment Resistors Diode Cathode Ray Oscilloscope Function generator Regulated power supply Specifications 1K 1N4007 20MHz 1MHz 0-30V. .34 Positive Base Clipper with Reference Voltage.V=-2V Negative peak clipper with reference voltage. V=2V Negative Base Clipper with Reference Voltage. Bapatla. V=-2v Electronic Circuits II Bapatla Engineering College. Repeat the steps 1 to 5 for all other circuits. V=2V S. Plot the transfer characteristics between output and input voltages. .1 2.No I/p voltage(v) O/p voltage(v) Electronic Circuits II Bapatla Engineering College.35 Slicer Circuit: Procedure: 1. To obtain the transfer characteristics apply dc voltage at input terminals and vary the voltage insteps of 1V up to the voltage level more than the reference voltage and note down the corresponding voltages at the output. 4. Obtain a sine wave of constant amplitude 8 V p-p from function generator and apply as input to the circuit. 3. Bapatla. Draw the observed output waveforms. 6 .No I/p voltage (v) O/p voltage (v) Positive base clipper: Reference voltage V= 2V S. 5 . 7. Observe the output waveform and note down the amplitude at which clipping occurs. Sample Readings: Positive peak clipper: Reference voltage. Connect the circuit as per circuit diagram shown in Fig. Negative base clipper: Vr=2v.No I/p voltage(v) O/p voltage(v) Slicer Circuit: S.6v When the diode is forward biased Vo=Vr –Vγ = 2v-0.No I/p voltage(v) O/p voltage(v) Negative peak clipper: Reference voltage= 2 V S.6v = 1.6v = 2. Vγ=0. Vγ=0. .4v When the diode is reverse biased Vo=Vi .36 Negative base clipper: Reference voltage= 2V S. Bapatla. Vγ=0.6v When the diode is reverse biased the Vo=Vi Positive base clipper: Vr=2v.No I/p voltage(v) O/p voltage(v) Theoretical calculations: Positive peak clipper: Vr=2v.6v When the diode is forward biased Vo =Vr+ Vγ =2v+0.6v Electronic Circuits II Bapatla Engineering College. Slicer: When the diode D1 is forward biased and D2 is reverse biased Vo= Vr+ Vγ =2. Model wave forms and Transfer characteristics Positive peak clipper: Reference voltage= 2V Electronic Circuits II Bapatla Engineering College.6v When the diodes D1 &D2 are reverse biased Vo=Vi .6)v =-2. . Negative peak clipper: Vr=2v. Vγ=0.6v When the diode is reverse biased Vo=Vi .6v When the diode is forward biased Vo= -(Vr+ Vγ) = -(2+0.37 When the diode is forward biased Vo = -Vr+ Vγ =-2v+0.6v When the diode D2 is forward biased and D2 is reverse biased Vo=-(Vr+ Vγ) = -(2+0.6)v =-2.4v When the diode is reverse biased Vo=Vi .6v =-1. Bapatla. 38 Positive base clipper: Reference voltage= 2V Negative base clipper: Reference voltage= 2v Negative peak clipper: Reference voltage= 2 V Electronic Circuits II Bapatla Engineering College, Bapatla. 39 Slicer Circuit: Precautions: 1. Connections should be made carefully. 2. Verify the circuit before giving supply. 3. Take readings without any parallax error. Result: Performance of different clipping circuits is observed and their transfer characteristics are obtained. Electronic Circuits II Bapatla Engineering College, Bapatla. 40 10. BISTABLE MULTIVIBRATOR Aim: To Observe the stable states voltages of Bistable Multivibrator. Apparatus required: Name of the Component/Equipment Transistor Resistors Regulated Power Supply BC 107 2.2K 12K 0-30V, 1A 2 2 2 1 Specifications Quantity Theory: The circuit diagram of a fixed bias bistable multivibrator using transistors. The output of each amplifier is direct coupled to the input of the other amplifier. In one of the stable states transistor Q1 and Q2 is off and in the other stable state. Q1 is off and Q2 is on even though the circuit is symmetrical; it is not possible for the circuit to remain in a stable state with both the transistors conducting simultaneously and caring equal currents. The reason is that if we assume that both the transistors are biased equally and are carrying equal currents i1 and i2 suppose there is a minute fluctuation in the current i1-let us say it increases by a small amount .Then the voltage at the collector of q1 decreases. This will result in a decrease in voltage at the base of q2. So q2 conducts less and i2 decreases and hence the potential at the collector of q2 increases. This results in an increase in the base potential of q1.So q1 conducts still more and i1 is further increased and the potential at the collector of q1 is further decreased, and so on . So the current i1 keeps on increasing and the current i2 keeps on decreasing till q1 goes in to saturation and q2 goes in to cut-off. This action takes place because of the regenerative feed –back incorporated into the circuit and will occur only if the loop gain is greater than one. Electronic Circuits II Bapatla Engineering College, Bapatla. Verify the state by measuring voltages at collector and also note down voltages at each base.65V VCE2=0. . Observations : Sample Readings Before Triggering Q1(OFF) VBE1=0.01V VCE2=5.65V VCE1=0.03V Q1(OFF) VBE2=0.6V Q1(ON) VBE2=0. 5. Connect the circuit as shown in figure. Note down the corresponding base voltages of the same state (say state-1).03V VCE1=5. apply negative voltage (say-2v) to the base of on transistor or positive voltage to the base of transistor (through proper current limiting resistance).03V Electronic Circuits II Bapatla Engineering College. Verify the stable state by measuring the voltages at two collectors by using multimeter. To change the state. 3.6V After Triggering Q1(ON) VBE1=0. 4. 2.41 Circuit Diagram: Procedure: 1. Bapatla. Connections should be made carefully. Note down the parameters carefully. Result: The stable state voltages of a bistable multivibrator are observed. . 2. Bapatla. The supply voltage levels should not exceed the maximum rating of the transistor.42 Precautions: 1. 3. Electronic Circuits II Bapatla Engineering College. but automatically reverse switches back to its origional stable state without any triggering pulse. It remains in the quasi stable state for a short duration. .5K Resistors 2. the other state being quasi stable state. The duration of quasi stable state is termed as delay time (or) pulse width (or) gate time. it switches from the stable to the quasi stable state. Electronic Circuits II Bapatla Engineering College. bistable has only one stable state. Bapatla.It is denoted as ‘t’.The monostable multivibrator is also referred as ‘one shot’ or ‘uni vibrator’ since only one triggering signal is required to reverse the original stable state.43 11. MONOSTABLE MULTIVIBRATOR Aim: To observe the stable state and quasi stable state voltages in monostable multivibrator. Normally the multivibrator is in stable state and when an externally triggering pulse is applied.2K 68K 1K Capacitor Diode CRO Function generator Regulated Power Supply 1µF 0A79 20MHz 1MHz 0-30V. 1A Specifications Quantity 2 1 2 1 1 2 1 1 1 1 Theory: A monostable multivibrator on the other hand compared to astable. Apparatus Required: Name of the Component/Equipment Transistor (BC 107) 1. 4 Observe the wave forms at base of each transistor simultaneously. 7 Note down the time period and compare it with theoretical values. Verify the stable states of Q1 and Q2 3. 8. T = 0. .693RC = 0. Note down the parameters carefully. 6.44 Ciircuiitt Diiagram:: C rcu D agram Procedure: 1..047 m sec Frequency. 1KHz signal to the trigger circuit. 2. Apply the square wave of 2v p-p . Observe the wave forms at collectors of each transistors simultaneously. 5.01x10-6 = 47µ sec = 0. Connect the circuit as per the circuit diagram. Vb2.Vc1 & Vc2 with respect to time .693x68x103x0. Bapatla. Calculations: Theoretical Values: Time Period. f = 1/T = 21 kHz Electronic Circuits II Bapatla Engineering College. Plot wave forms of Vb1. Note down the parameters without parallax error. 3. Result: Stable state and quasi stable state voltages in monostable multivibrator are observed Electronic Circuits II Bapatla Engineering College. Connections should be made carefully.45 Model waveforms: Precautions: 1. Bapatla. . 2. The supply voltage levels should not exceed the maximum rating of the transistor. 9K 100K 0. The astable multivibrator cannot remain indefinitely in any one of the two states . Bapatla. An Astable Multivibrator has two quasi stable states and it keeps on switching between these two states by itself . ASTABLE MULTIVIBRATOR Aim: To Observe the ON & OFF states of Transistor in an Astable Multivibrator. 1A 2 2 2 2 1 Specifications Quantity Theory :.46 12. The astable multivibrator may be to generate period. No external triggering signal is needed .38RC. Apparatus required: Name of the Component/Equipment Transistor (BC 107) Resistors Capacitor Regulated Power Supply BC 107 3.The two amplifier stages of an astable multivibrator are regenerative across coupled by capacitors. .1.01µF 0-30V. a square wave of Circuit Diagram Electronic Circuits II Bapatla Engineering College. f = 1/T = 10. T = 1. 2. 6. Calculations: Theoritical Values : RC= R1C1+ R2C2 Time Period.368RC = 1. Note down the values of wave forms carefully. 5. Bapatla.47 Procedure : 1.368x100x103x0. 4. Observe the voltage wave forms at each base simultaneously with corresponding collector voltage.01x10-6 = 93 µ sec = 0. Compare the theoratical and practical values.75kHz Electronic Circuits II Bapatla Engineering College. 3 Observe the voltage wave forms at both collectors of two transistors simultaneously.093 m sec Frequency. . Calculate the theoratical frequency of oscillations of the circuit.Connect the circuit as per the circuit diagram. Readings should be noted without parallax error.48 Model waveforms : Precautions : 1. Connections should be made carefully. Bapatla. Result : The wave forms of astable multivibrator has been verified. 2. . Electronic Circuits II Bapatla Engineering College. SCHMITT TRIGGER Aim: To Generate a square wave from a given sine wave using Schmitt Trigger Apparatus Required: Name of the Component/Equipment Transistor BC 107 100 2 1 Values/Specifications Quantity Resistors 6.49 13. One way of adjusting the loop gain is by varying Rc1.7K 2. .01µF 20MHz 30V 1MHz Theory: Schmitt trigger is a bistable circuit and the existence of only two stable states results form the fact that positive feedback is incorporated into the circuit and from the further fact that the loop gain of the circuit is greater than unity. So the output voltage is Vo=Vcc-Ic2Rc2 is at its lower level.8K 3.9K 2. Electronic Circuits II Bapatla Engineering College. Under quiescent conditions Q1 is OFF and Q2 is ON because it gets the required base drive from Vcc through Rc1 and R1. There are several ways to adjust the loop gain. Untill then the output remains at its lower level. Bapatla.2K 1 1 1 1 1 1 1 1 Capacitor CRO Regulated Power Supply Function generator 0. 50 Circuit diagram : Procedure: 1 Connect the circuit as per circuit diagram. . 1 KHz frequency wave as input to the circuit. 4 Note down the input voltage levels at which output changes the voltage level. Electronic Circuits II Bapatla Engineering College. 5 Draw the graph between votage versus time of input and output signals. 2 Apply a sine wave of peak to peak amplitude 10V. Bapatla. 3 Observe input and output waveforms simultaneously in channel 1 and channel 2 of CRO. Electronic Circuits II Bapatla Engineering College. and from the further fact that the loop gain of the circuit is greater than unity.51 Model Graph: Precautions: 1. Squaring circuit 3. Question & Answers: 1. and existence of only two stable states results from the fact that positive feedback is incorporated into the circuit. Connections should be made carefully. 2. UTP is defined as the input voltage at which Q1 starts conducting. Result: Schmitt trigger is constructed and observed its performance. Inference: Schmitt trigger circuit is a emitter coupled bistable circuit. Readings should be noted carefully without any parallax error. LTP is defined as the input voltage at which Q2 resumes conduction. What is the other name of the Schmitt trigger? Ans Emitter coupled Binary 2. Define the terms UTP & LTP? Ans. . Bapatla. What are the applications of the Schmitt trigger? Ans Amplitude Comparator. When the voltage Vo exceeds voltage Vp.Vbb.Vp. UJT RELAXATION OSCILLATOR Aim: To obtain the characteristics of UJT Relaxation Oscillator. Where. Here UJT is used as a switch to obtain the sweep voltage. Bapatla.1µF Capacitor 0. As long as the capacitor voltage is less than peak Voltage.UJT. This process is repeated until the power supply is available. Vγ = Cut in voltage of diode. Vp =ηVbb + Vγ where. The Capacitor starts discharging through R1 + Rb1.001µF Diode Inductor CRO Function generator Regulated Power Supply 0A79 130mH 20MHz 1MHz (0-30V). the emitter appears as an open circuit.R towards supply Voltage. Apparatus Required: Name of the Component/Equipment UJT Specifications Quantity 2N 2646 220 1 1 1 1 1 1 1 1 1 1 1 1 Resistors 68K 120 0. Rb1 is the internal base resistance.52 14.1A Theory: Many devices such as transistor. the UJT fires. .01µF 0. Capacitor C charges through the resistor. Electronic Circuits II Bapatla Engineering College.η = stand off ratio of UJT. FET can be used as a switch. Vv/ Vbb. When C=0.1µF Tc =RC ln(Vbb.7+(120/120+220)10 =8.Vv/ Vbb.1µF) (12/12-8.1µ)=12 µsec.5) = 365µs Electronic Circuits II Bapatla Engineering College.6ms Td =R1C=(120)( 0. When C=0. Bapatla.Vp) =(68K) (0.53 Circuit diagram: Design equations: Theoretical Calculations: Vp = Vγ+(R1/ R1 R2 )Vbb =0.01µF Tc =RC ln(Vbb.57V 1. 2.01µF) (12/12-8.Vp) =(68K) (0. .57) = 3. 001µF) (12/12-8. 3) Change the time constant by changing the capacitor values to 0.NO Capacitance value (µF) Theoretical time period Practical time period Procedure: 1) Connect the circuit as shown in figA. 2) Observe the voltage waveform across the capacitor.Vv/ Vbb. 3.charging and discharging periods of the wave forms 5)Compare the theoretical and practical time periods.01µ)=1.001 µF and observe the wave forms.12 µsec S.54 Td =R1C=(120)( 0. Bapatla. 6)Plot the graph between voltage across capacitor with respect to time Model graph: Electronic Circuits II Bapatla Engineering College.01µ)=0.Vp) =(68K) (0. 4) Note down the parameters. .5µs Td =R1C=(120)( 0. amplitude. When C=0.1µF and 0.001µF Tc =RC ln(Vbb.C.2 µsec.5) = 36. .Connections should be given carefully. Result: Performance and construction of UJT Relaxation Oscillator is observed. Bapatla. Electronic Circuits II Bapatla Engineering College. 2. Readings should be noted without parallox error.55 Precautions: 1. and the simple tones are sufficient for applications such as alarms or a morsecode practice device. but it can serve to flash lights or LEDs. and one amplifying component.56 15. Some cameras use a blocking oscillator to strobe the flash prior to a shot to reduce the red-eye effect.1µF NPN 20MHz 1MHz (0-30V). transformer. Bapatla. requiring only a capacitor. The Non-sinusoidal output is not suitable for use as a radio-frequency Local oscillator. The name is Derived from the fact that the transistor (or tube) is cut-off or "blocked" for most of the duty-cycle. . Electronic Circuits II Bapatla Engineering College. Apparatus Required: Name of the Component/Equipment transfotmer Resistors Capacitor Transistor CRO Function generator Regulated Power Supply Specifications Quantity 1 220 0. producing periodic pulses.Blocking oscillator Aim: To obtain the characteristics of Blocking Oscillator.1A 1 1 1 1 1 1 Theory: A blocking oscillator is the minimal configuration of discrete electronic Components which can produce a free-running signal. . but at low resistances the transistor will be overdriven. Due to the simplicity of the circuit. The frequency of the oscillator is also affected by the supply voltage Circuit diagram: Model graph: Blocking oscillator out put wave form Electronic Circuits II Bapatla Engineering College. A secondary winding of the transformer can be fed to a speaker. A potentiometer placed in parallel with the timing capacitor permits the frequency to be adjusted.57 . The output signal will jump in amplitude and be greatly distorted. or the windings of a relay. and possibly damaged. Bapatla. a lamp. it forms the basis for many of the learning projects in commercial electronic kits. 3) Change the time constant by changing the capacitor values to 0.1µF and 0.charging and discharging periods of the wave forms Result: Study of blocking oscillator is done.001 µF and observe the wave forms.58 Procedure: 1) Connect the circuit as per the circuit diagram. . 2) Observe the voltage waveform across the collector of transistor. amplitude. 4) Note down the parameters. Bapatla.. ---------------------------------------------------------------------------------------------------------- Electronic Circuits II Bapatla Engineering College. Bapatla. .59 Electronic Circuits II Bapatla Engineering College. 60 Electronic Circuits II Bapatla Engineering College. . Bapatla.