2007 12 ICC Incremental Training

IC Compiler 2007.12 Incremental Training IC Compiler CAE Predictable Success IC Compiler 2007.12 Update Training Agenda • • • • • • Timing/SI MCMM Hierarchical Flow (Includes ILM) Low Power DFM & Routing User Interface New commands/options added in 2007.12 highlighted in Blue © 2007 Synopsys, Inc. (2) (2) Predictable Success IC Compiler 2007.12 – Timing/SI • IC Compiler Feasibility flow Design Setup Design Setup Floorplanning Floorplanning • Min Chip Technology • Optimization runtime improvement • Improved report_congestion place_opt place_opt clock_opt clock_opt route_opt route_opt • Integrated clock global router • Fix DRCs beyond exceptions mark_clock_tree • Layer based GR congestion map – User Interface • Mixed mode extraction • Auto extraction Chip Finishing Chip Finishing signoff_opt signoff_opt • Min delta delay correlation • SI run time improvement • User Interface improvements for noise © 2007 Synopsys, Inc. (3) (3) Predictable Success (4) (4) Predictable Success . Inc.check_library • Overview Data consistency check between Logical v/s Physical libraries Physical library database consistency check Enhanced Tech File checking and man pages • User Interface check_library -mw_library_name {phys_library_name_list} logic_library_name {logical_library_name_list} –cell_list {cell_list} • User Benefit • • Identifies the library problems earlier and provided the details reports to user Helps the turn around time and avoids late detection of library issues © 2007 Synopsys. Inc. (5) (5) Predictable Success .IC Compiler Feasibility Flow • Overview The feasibility flow should be run before detail implementation It helps to eliminate potential issues in early design stages There are three main checks in the flow: • Routeability • Power network integrity • Timing • • User Interface N/A User Benefit Gives faster turn around time (TAT) Gives early prediction of timing closure © 2007 Synopsys. IC Compiler Feasibility Flow Read Netlist / Constraints Initialize Floorplan Virtual Flat Placement PNA/PNS Power OK •read_verilog_to_cel •read_io_constraints •read_sdc Floorplan refinement Refine PG mesh •initiialize_floorplan •create_fp_placement •analyze_fp_rail •synthesize_fp_rail Global Route Routability OK Update SDC Check Timing Environment Timing Optimization Timing OK NO NO Yes Bad floorplan •route_fp_protp •report_congestion • check_fp_timing_environment Identifies unconstrained paths. zero wire delay timing violations. timing with virtual optimization to quickly identify bad timing paths. Inc. bottleneck cells. (6) •optimize_fp_timing quick optimization (6) Predictable Success . modules Bad SDC NO psynopt place_opt clock_opt route_opt © 2007 Synopsys. including on rectilinear edges) Min chip supports proportional sizing of voltage areas Min chip accounts for power routing using Power Network Synthesis • Each voltage area may have different mesh patterns (strap pitch. rings) Min chip supports complex I/O (multi-height.Min Chip Technology • Overview Min chip preserves user’s investment in floorplan • Floorplan is preserved (block shape. (7) (7) Predictable Success . multi-ring. blockages) • Pins preserved (relative side and order. Inc. layers. staggered) • User Interface Run the Tcl command estimate_fp_area or GUI: Floorplan Estimate Area • User Benefit Search for smallest routable de size • Preserves floor planning investment • Eliminates costly resizing iterations Improves designer productivity © 2007 Synopsys. macro placements. Inc.Min Chip Technology Flow Recommendations Design Data Design Data (Original Netlist) (Original Netlist) • • • Start with original netlist for P&R flow Minchip needs an optimized database as an input or results will be too optimistic Minchip produces the smallest routable new floorplan After Minchip use original netlist and new floorplan for P&R flow Design Planning Design Planning Detailed Implementation Detailed Implementation • MinChip MinChip Design Data Design Data (Original Netlist ++New (Original Netlist New MinChip Floorplan) MinChip Floorplan) Detailed Implementation Detailed Implementation © 2007 Synopsys. (8) (8) Predictable Success . psynopt.Optimization Runtime Improvement • • • Overview Improved buffering runtime for optimization User Interface No User Interface changes are required User Benefit Average 30% runtime improvement @ place_opt stage No QoR impact Works with any optimizations • Pre route optimization place_opt. (9) (9) Predictable Success . clock_opt • Post route optimization route_opt © 2007 Synopsys. Inc. (10) (10) Predictable Success . Inc.12 with the integrated clock global router replaces virtual route for optimize_clock_tree and balance_inter_clock_delay • In prior releases clock tree implementation used virtual route for wire delay and capacitance estimation which caused correlation issues between clock and signal route • User Interface cts_integrated_global_router <true|false:default> © 2007 Synopsys.Integrated Clock Global Router (ICGR) • Overview 2007. Integrated Clock Global Router (ICGR) • User Benefit Compared to virtual route based CTS flow. Inc. (11) (11) Predictable Success . ICGR has shown improved clock tree correlation between • Post-cto and post clock route (average correlation within 10%) • Post-cto and post clock/signal route( average correlation within 10%) • CTO with ICGR run time: +20% Note: Correlation can be further improved with clock spacing and shielding and also the Non Default Rules © 2007 Synopsys. Integrated Clock Global Router (ICGR) compile_clock_tree set cts_integrated_global_router true Enable ICGR before CTO (default: false) optimize_clock_tree Set clock routing variables set droute_wrongWayExtraCost 20 set groute_incremental 2 route_group –all_clock_nets Reset clock routing variables set droute_wrongWayExtraCost 0 set groute_incremental 0 © 2007 Synopsys. (12) (12) Predictable Success . Inc. sync and exclude pins • User Interface No Change • User Benefit DRC fixing is done by default during CTS Improve TTR & QoR © 2007 Synopsys. (13) (13) Predictable Success . reports and removes the DRCs beyond exceptions – stop.Fix DRC Beyond Exceptions • Overview CTS fixes. Inc. Fix DRC Beyond Exceptions • Flow log example compile_clock_tree CTS: clock tree synthesis summary CTS: 2 buffer trees inserted CTS: 17 buffers used (total size = 217.. 3 buffer(s) and 0 inverter(s) are removed © 2007 Synopsys. (14) (14) Predictable Success .689) CTS: summary of DRC fixing beyond exception pin CTS: 1 buffer trees inserted CTS: 3 buffers used (total size = 41. Inc..1845) report_clock_tree –structure shows the structure of new clock tree including beyond exceptions remove_clock_tree SUMMARY 14 buffer(s) & 0 inverter(s) are removed Removing cells added for drc fixing beyond exceptions. mark_clock_tree • Overview Modify clock related attributes on clock cells and nets • Clock net NDR and routing layer • Clock tree imported from Astro or 3rd party tool • Fix or soft-fix sinks for routing resource adjustment • User Benefit Mark clock tree to identify imported clock tree and continue clock optimization Modify existing clock tree attributes for subsequent optimization and routing © 2007 Synopsys. (15) (15) Predictable Success . Inc. (16) (16) Predictable Success .mark_clock_tree • User Interface •mark_clock_tree -clock_trees -clock_net -clock_synthesized -fix_sinks -routing_rule -use_default_routing_for_sinks -layer_list -ideal_net -remove © 2007 Synopsys. Inc. mark_clock_tree • Flow recommendations Use this command to mark clock attributes on imported clock tree structures for sub-sequent IC Compiler clock operations To modify NDR rules applied on a already synthesized clock network • Known Limitations ETM model internal clock pin are not supported © 2007 Synopsys. Inc. (17) (17) Predictable Success . (18) (18) Predictable Success .Mixed Mode Extraction • • Overview Enhance extract_rc to perform detail route extraction and virtual route estimation User Interface Set the following variable to true • set complete_mixed_mode_extraction true • Default: false • When mixed mode extraction will be ON by default. -routed_nets_only option will be added to extract_rc and write_parasitics commands • User Benefit Minimized number of commands when extracting a partially routed design (clock routed stage). extract_rc Please keep in mind that place_opt currently doesn’t support mixed mode extraction © 2007 Synopsys. Inc. then for backward compatibility. • extract_rc • can now be replaces • extract_rc –estimate. Fixes issues in auto-extraction for not to extract if the design is not re-linked.12 when timing constraints need to be removed (SDC) . (19) (19) Predictable Success . tluplus files and temperatures are not changed • User Interface Option –keep_parasitics is added to remove_sdc command • User Benefit Parasitics need not be re-extracted after remove_sdc Ease of use and reduced runtime by not having to re-extract the parasitics © 2007 Synopsys. Inc.Auto Extraction • Overview Preserving parasitic is possible in 2007. (20) (20) Predictable Success . Inc.Auto Extraction • Usage /GUI Use the -keep_parasitics option to retain the parasitics information during remove_sdc • remove_sdc –keep_parasitics • Flow Recommendations Use remove_sdc –keep_parasitics when removing CTS SDC after clock_opt © 2007 Synopsys. Ignore Layers Support In Virtual Route • Overview To honor ignored layers in virtual route topology creation • User Interface No change in User Interface • User Benefit Improved correlation of virtual route and detail route topology when ignored layers are used • Ex. virtual route will now detour around it (consistent with detail router topology) © 2007 Synopsys. Inc. if M6 and M7 are ignored. (21) (21) Predictable Success . On a 7-metal layer design. and there is a Macro that blocks layers M1-M5. Ignore Layers Support In Virtual Route • Usage /GUI No change in User Interface extract_rc –estimate (executed stand-alone and also invoked during pre-route optimization commands) will now honor the ignored layers © 2007 Synopsys. Inc. (22) (22) Predictable Success . (23) (23) Predictable Success . Inc.Improved report_congestion • Overview report_congestion is updated to use the IC Compiler global route to ensure consistency and convergence • User Interface report_congestion • Changes to this feature are explained later • User Benefit Global router based congestion map and correlates with GUI display of hotspots/overflows Good correlation between pre route and post route stage © 2007 Synopsys. Inc. report_congestion automatically runs groute to generate congestion map -grc_based • Reports GRC base. If this option is specified.Improved report_congestion • Usage report_congestion -search_repair -no_reroute -grc_based -coordinate -search_repair • Controls groute iteration.coordinate • Specify the region to report. Entire design reported by default © 2007 Synopsys. Worse 10 GRC reported . Default is 1 iteration. (24) (24) Predictable Success . groute runs 4 iterations -no_reroute • In default. (25) (25) Predictable Success .Improved report_congestion © 2007 Synopsys. Inc. (26) (26) Predictable Success . Inc.Layer-Based Global Route Congestion Map • Overview The old congestion map for display is two dimensional (x & y) The global router is a 3 dimensional routing engine with metal layer being the third dimension • The demand and capacity of metal layers on the same direction is added and displayed as one single demand and capacity Hence. the old congestion map does not reflect the realistic picture of congestion • This is true if some metal layers have significant congestion and some metal layers don’t • User Benefit The new congestion map allows user to display and view congestion information per layer basis • Congestion map is consistent with log file report • Studying congestion on a specific layer is possible © 2007 Synopsys. Inc.Layer-Based Global Route Congestion Map • User Interface / GUI (Examples) M2 congestion hot spot is shown in the new congestion map Almost no congestion is shown in the old congestion map Overflow on M2 is cancelled out by underflow on M4 and M6 (27) © 2007 Synopsys. (27) Predictable Success . Layer-Based Global Route Congestion Map • User Interface / GUI There is no User Interface change GUI: Route -> Global Route Congestion Map NEW © 2007 Synopsys. Inc. (28) (28) Predictable Success . (29) (29) Predictable Success . Inc.Min Delta Delay Correlation • Overview Coupling capacitance is partially grounded for min crosstalk delta delay calculation to improve correlation with PTSI • User Interface set si_use_partial_grounding_for_min_analysis false Feature not ON by default • User Benefit Better correlation in min-corner (Hold) timing • Percentage of paths with arrival time difference less than 3% is improved from 89% to 97% © 2007 Synopsys. SI Runtime Improvement • • Overview Reduce SI analysis runtime in low effort crosstalk mode while improving the correlation with PTSI User Interface No NEW User Interface change To Enable: • set_si_options –analysis_effort low • Default: medium • User Benefit Reduced runtime in update_timing. Inc.2% Improved IC Compiler-PT-SI correlation in low effort mode © 2007 Synopsys. (30) (30) Predictable Success . route_opt with SI low effort mode • update_timing runtime reduced by 8% • route_opt runtime reduced by 3. Xtalk User Interface Improvement • Overview Improved SI delta delay user interface in IC Compiler • You get detail information on the individual aggressor contribution • Report the details of the active and screened aggressors • User Interface report_delay_calculation –crosstalk • User Benefit Ease of use for debugging PT-SI delta delay correlation on specific timing arcs © 2007 Synopsys. Inc. (31) (31) Predictable Success . 000396 n32835 0.242500 Reporting for Crosstalk: Victim net name: n12228 Number of aggressors: 4 Number of effective (non-filtered) aggressors: 4 Victim driver rail voltage(VDD): 1.aggressor is screened Victim is rising: Victim Net -------------n12228 is Active aggressor is a composite aggressor aggressor is screened due to user Exclusion aggressor has Infinite arrival with respect to the victim aggressor is screened due to Logical correlation aggressor does Not overlap for the worst case alignment aggressor is screened for Small bumps aggressor/victim RC calculation is skipped aggressor is screened due to aggressor eXclusion Coupling Cap --------0.aggressor C E I L N S U X - PTSI report_delay_calculation -crosstalk Annotated max rise net delta delay: 0. Inc.011469 Annotated max fall net delta delay: 0.011469 Annotated max fall net delta delay: 0.002741 Driver Lib Cell -----------OAI21D1 Driver Lib Cell Clocks --------------FE_CLK Clocks Victim is rising: Victim Net -------------n12228 Aggressor Net -------------n3397 n32801 n32807 Coupling Cap --------0.010078 pin transition: 0.000000 arc delay: 0.001798 0.242500 Reporting for Crosstalk: Victim net name: n12228 Number of aggressors: 4 Number of effective (non-filtered) aggressors: 4 Victim driver rail voltage(VDD): 1.000000 pin transition: 0.000396 Driver Lib Cell -----------OAI21D1 Driver Lib Cell ----------INVD1 ND3D0 ND3D0 Clocks --------------FE_CLK Clocks ------------FE_CLK FE_CLK FE_CLK Attributes -----------A S S Switching Bump (ratio of VDD) ---------------0.080000 si_xtalk_analysis_effort_level: medium si_xtalk_delay_analysis_mode: all_paths si_analysis_logical_correlation_mode: true Crosstalk composite aggressor mode: disabled Attributes: A .000800 Annotated max rise net delta transition: 0.010671 arc delay: 0.024420 - Aggressor Coupling Attributes Switching Bump Net Cap (ratio of VDD) ------------------------.010078 pin transition: 0.000348 © 2007 Synopsys.000800 Annotated max rise net delta delay: 0.000000 arc delay: 0.450000 Annotated max fall net delta transition: 0. (32) n32835 ------------FE_CLK FE_CLK FE_CLK FE_CLK -------A S S S 0.080000 Attributes: A .Xtalk User Interface Improvement IC Compiler report_delay_calculation crosstalk Operating Conditions: WCCOM Library: tcbn90gthpwc Annotated max rise net delta transition: 0.---------------n3397 0.000199 n32807 0.024420 n32801 0.002741 Coupling Cap --------0.001798 0.aggressor is Active S .000000 pin transition: 0.000199 0.450000 Annotated max fall net delta transition: 0.010671 arc delay: 0.000348 NR2D0 FE_CLK S ----------INVD1 ND3D0 ND3D0 NR2D0 (32) Predictable Success . Noise User Interface Improvement • Overview Improve SI static noise user interface in IC Compiler • You get detail information on the individual aggressor contribution • Report the details of active and screened aggressors • User Interface report_noise -verbose -all_violators slack_lesser_than slack_limit report_noise_calculation -from from_pin -to to_pin -significant_digits digits • User Benefit Ease of use for debugging PT-SI static noise correlation on specific timing arcs © 2007 Synopsys. Inc. (33) (33) Predictable Success . 025 0. (34) (34) Predictable Success .080000 Noise derate height offset : 0.025 0.009 A exetop0/e_rndm0/n19178 0.Noise User Interface Improvement IC Compiler report_noise_calculation Analysis mode Region Victim driver pin Victim driver library cell Victim net Steady state resistance source Driver voltage swing Attributes: A .aggressor X .082 0.012 A exetop0/e_rndm0/n10 0.029 0.603) Actual 0.603) --------------------------------------------------------------------Slack 0.000 S exetop0/e_rndm0/n18454 0.000 0.aggressor E .702 0.082 (0.028 0.aggressor is Active S .843 0.567 (0.025 Noise slack calculation: Constraint type: user margin Height Area --------------------------------------------------------------------Required Time 0.009 A exetop0/e_rndm0/n19178 0.aggressor I .082 * 0.702 0.000000 Noise effort threshold : 0.000 0.000 0.082 * 0.aggressor G .282 0.620 PTSI report_noise_calculation Analysis mode Region Victim driver pin Victim driver library cell Victim net Steady state resistance source Driver voltage swing : : : : : : : report_at_source below_high exetop0/e_dptop0/e_flag0/I27/Y MX4X4 exetop0/e_dptop0/e_flag0/N194 estimation set value 1.004 A exetop0/s_AEI2_0_ 0. Inc.603) Actual 0.567 * 0.282 0.603 0.000 0.aggressor is active is a composite aggressor is analyzed with detailed engine is screened due to user exclusion is analyzed with gate level simulator has infinite window is screened due to logical correlation is screened due to small bump height is screened due to aggressor exclusion Height Width Area Aggressor Attributes --------------------------------------------------------------------------Aggressors: exetop0/e_rndm0/n35 0.004 A exetop0/s_AEI2_0_ 0.012 A exetop0/e_rndm0/n10 0.293 © 2007 Synopsys.000 S Total: 0.000 0.000000 Noise composite aggressor mode : disabled Noise calculations: Attributes: A .082 0.620 Driver voltage swing : 1.000 0.029 0.000 0.000 S exetop0/e_rndm0/n18454 0.000000 Noise derate height scale factor : 1.000 0.aggressor D .025 Noise slack calculation: Constraint type: user margin Height Area --------------------------------------------------------------------Required Time 0.aggressor C .567 * 0.000 S Total: 0.aggressor S .aggressor L .603) --------------------------------------------------------------------Slack 0.567 (0.082 (0.000000 Noise derate width scale factor : 1.485 0.485 0.843 0.028 0.293 : : : : : : : report_at_source below_high exetop0/e_dptop0/e_flag0/I27/Y MX4X4 exetop0/e_dptop0/e_flag0/N194 estimation set value 1.603 0.aggressor is screened Height Width Area Aggressor Attributes --------------------------------------------------------------------------Aggressors: exetop0/e_rndm0/n35 0. 12 Update Training 1. 5. Inc. 6. 4.12 highlighted in Blue © 2007 Synopsys. 3. (35) (35) Predictable Success . Timing/SI MCMM Hierarchical Flow (includes ILM) Low Power DFM & Route Rules User Interface New commands/options added in 2007.IC Compiler 2007. 2. Inc.IC Compiler 2007.12 – MCMM Design Setup Design Setup Floorplanning Floorplanning place_opt place_opt clock_opt clock_opt route_opt route_opt •More Than 3 TLUPlus Support •Support For Netlist ECO Commands •MCMM Reporting Enhancements Chip Finishing Chip Finishing signoff_opt signoff_opt © 2007 Synopsys. (36) (36) Predictable Success . the user can now use as many TLUPlus as needed in a MCMM session. The user will use more than 3 TLUPlus files by creating more scenarios. With 2007. Inc.More Than 3 TLUPlus Support • Overview • This feature addresses the previous limitation of using up to 3 TLUPlus in one MCMM session. (37) (37) Predictable Success . • User Benefit The users can see significant improvements in usage as they can now optimize their design across any number of TLUPlus corners.12. • User Interface No change in User Interface. © 2007 Synopsys. Inc.More Than 3 TLUPlus Support • Usage TLUPlus files must be set by the set_tlu_plus_files command under the scope of each scenario • Flow Recommendations First create a scenario Then set TLUPlus files for that scenario © 2007 Synopsys. (38) (38) Predictable Success . db file name>:<library name>/<lib_cell name> • <library name>/<lib_cell name> • <lib_cell name> to specify the lib_cell © 2007 Synopsys. Inc. user can use one of • <. (39) (39) Predictable Success .Netlist ECO Commands To Support MCMM • Overview insert_buffer/size_cell are MCMM compatible • User Interface The command selects the lib_cel from the library based on the operating condition setting (associated with scenario). current. operating conditions.MCMM Reporting Enhancements • New report_scenario command Lists scenarios status • all. active. CTS and leakage scenarios Returns libraries. Inc. TLUPlus per scenario • Enhancements to existing commands Increased number of commands supporting a scenario list Commands working on current scenario only • Scenario now reported in report header © 2007 Synopsys. (40) (40) Predictable Success . 12-IC Compiler-ALPHA3 Date : Thu Sep 20 13:10:18 2007 **************************************** All scenarios (Total=4): s1 s2 s3 s4 All Active scenarios (Total=2): s1 s2 Current scenario : s2 CTS scenario : s3 Leakage-only scenario: not defined. Scenario #0: s1 is active. Library(s) Used: xx_worst (File: /des/90nm/LM/xx_worst.tf Tech2ITF mapping file: /remote/tf2itf.map Scenario #1: s2 is active.10 Max Temperature: 85.db) Operating condition(s) Used: Max Operating Condition: xx_worst:WORST Max Process : 1.00 Max Voltage : 1.00 Min Operating Condition: xx_best:BEST Min Process : 1.30 Min Temperature: 0.00 Tlu Plus Files Used: Max TLU+ file: /des/xx_worst_TLUP.00 Min Voltage : 1. Inc.00 Min Operating Condition: xx_worst:WORST Min Process : 1.00 Tlu Plus Files Used: Max TLU+ file: /des/xx_worst_TLUP.lib_T85.10 Min Temperature: 85.00 Min Voltage : 1. (41) (41) Predictable Success .tf Min TLU+ file: /des/xx_best_TLUP.tf Min TLU+ file: /des/xx_best_TLUP.tf Tech2ITF mapping file: /remote/tf2itf. Library(s) Used: xx_worst (File: /des/90nm/LM/xx_worst.00 Max Voltage : 1.map © 2007 Synopsys.10 Max Temperature: 85.db) Operating condition(s) Used: Max Operating Condition: xx_worst:WORST Max Process : 1.lib_T85.report_scenarios Command **************************************** Report : scenarios Design : small_test Scenario(s): s1 s2 Version: A-2007. MCMM Reporting Enhancements Commands supporting -scenario {scenario list}: • report_timing • report_timing_derate • report_clock • report_path_group • report_net (scenario specific info only eg. (42) (42) Predictable Success . -transition_times) • report_power • report_extraction_options • report_tlu_plus_files • report_constraint -all_violators/-verbose © 2007 Synopsys. Inc. 12-IC Compiler-ALPHA3 Date : Thu Sep 20 13:54:16 2007 **************************************** Critical Group Name Weight Range Scenario ---------------------------------------------reg2reg 1.00 0.MCMM Reporting Enhancements report_path_group **************************************** Report : path_group Design : small_test report_path_group -scenario [all_scenarios] **************************************** Report : path_group Design : small_test Scenario(s): s2 Version: A-2007. Inc.00 clk 1.00 0.00 0.00 0. (43) (43) Predictable Success .12-IC Compiler-ALPHA3 Date : Thu Sep 20 13:54:16 2007 **************************************** Critical Group Name Weight Range Scenario ---------------------------------------------reg2reg 1.00 0.00 0.00 Path Group clk: (Scenario: s2) -to clk s1 s1 s2 s2 © 2007 Synopsys.00 s2 clk 1.00 s2 Path Group clk: (Scenario: s2) -to clk Scenario(s): s1 s2 s3 s4 Version: A-2007.00 clk 1.00 Path Group clk: (Scenario: s1) -to clk Critical Group Name Weight Range Scenario ---------------------------------------------reg2reg 1. MCMM Reporting Enhancements • Commands reporting only on current scenario now have scenario information in the report header •report_annotated_check •report_annotated_transition •report_annotated_delay •report_attribute •report_case_analysis •report_ideal_network •report_internal_loads •report_clock_gating_check •report_clock_tree •report_clock_tree_power •report_delay_calculation •report_delay_estimate_options •report_transitive_fanout •report_disable_timing •report_latency_adjustment_options •report_net •report_power •report_power_calculation •report_noise •report_signal_em •report_timing_derate •report_timing_requirements •report_transitive_fanin •report_crpr •report_clock_timing © 2007 Synopsys, Inc. (44) (44) Predictable Success MCMM Reporting Enhancements **************************************** Report : net Design : small_test Scenario(s): s2 Version: A-2007.12-IC Compiler-ALPHA3 Date : Thu Sep 20 14:30:40 2007 **************************************** Parasitic source Parasitic mode Extraction mode Extraction derating : : : : LPE RealRC MIN_MAX 85/85 Library: xx_worst Operating Conditions: WORST Wire Load Model Mode: top Attributes: c - annotated capacitance r - annotated resistance Net Fanout Fanin Load Resistance Pins Attributes -------------------------------------------------------------------------------a 1 1 11.14 0.00 2 c, r b 1 1 7.76 0.00 2 c, r c 1 1 16.32 0.00 2 c, r c1 1 1 9.21 0.00 2 c, r c2 2 1 13.53 0.00 3 c, r … w17 1 1 9.25 0.00 2 c, r w18 1 1 7.04 0.00 2 c, r -------------------------------------------------------------------------------Total 40 nets 43 40 433.19 0.00 83 Maximum 2 1 34.03 0.00 3 Average 1.08 1.00 10.83 0.00 2.08 © 2007 Synopsys, Inc. (45) (45) Predictable Success IC Compiler 2007.12 Update Training 1. 2. 3. 4. 5. 6. Timing/SI MCMM Hierarchical Flow (includes ILM) Low Power DFM & Route Rules User Interface New commands/options added in 2007.12 highlighted in Blue © 2007 Synopsys, Inc. (46) (46) Predictable Success Inc.12 – Hierarchical Flow Design Setup Design Setup Floorplanning Floorplanning place_opt place_opt clock_opt clock_opt route_opt route_opt Chip Finishing Chip Finishing •Hierarchical Flow •Plan Group Based Placement •Plan Group Shaping •Clock Planning •Pin Assignment •Budgeting Flow •Black Box Support •ILM Enhancement •Hierarchical Verilog Netlist signoff_opt signoff_opt © 2007 Synopsys. (47) (47) Predictable Success .IC Compiler 2007. Hierarchical Design Flow • • Overview 2007.12 IC Compiler provides hierarchical design methodology to divide and conquer large designs User Interface Use IC Compiler Design Planning to perform hierarchical floorplanning. check design feasibility. (48) (48) Predictable Success . Inc. generate hierarchical design database Use standard IC Compiler flow to finish block implementation Generate ILM and FRAM models for blocks Implement top level using ILM/FRAM • User Benefit Manage capacity and run time Support hierarchical design methodology in different scenarios • Black Box flow. © 2007 Synopsys. MCMM etc. Lower power. Inc. (49) route_opt (49) Predictable Success .Hierarchical Design Flow Hierarchical Design Planning Read Netlist/constraints Initial floorplan Virtual Flat Placement Load Design/SDC Create plan group shaping/refinement PNA/PNS plangroup aware routing route_opt In Place Optimization ILM/FRAM Generation Set Pin Assignment Constraints Block level Top level Load Design/ILM Replace CEL wt FRAM place_opt read_SDC clock_opt place_opt clock_opt Pin Assignment Timing Budgeting Commit Hierarchy © 2007 Synopsys. shapes and sizes of the physical blocks © 2007 Synopsys. (50) (50) Predictable Success .Plan Group Based Placement • Overview Plan Group: • Represents a module in the logical hierarchy that needs to be physically implemented • Physical implementation block inherits the shape and size of the PlanGroup Virtual Flat Placement in design with Plan Groups • Place cells and hard macros of same physical implementation block together • • User Interface Run the Tcl Command create_plan_groups or GUI: Floorplan Create Plan Group User Benefit Placement result can be used to decide • Hard macro locations • Locations. Inc. black boxes and other soft macros in the core area © 2007 Synopsys.Plan Group Shaping • Overview Plan Group Shaping feature : • Places the Plan Groups based on cell distribution • Can create both “rectangular” and “rectilinear” shapes for Plan Groups • Run virtual flat placement again to put cells into plan group area • User Interface Run the Tcl Command shape_fp_blocks or GUI: Placement Place and Shape Plan Groups • User Benefit Automatically Place and Shape plan group boundaries. Inc. (51) (51) Predictable Success . Generates the top-level clock tree. (52) (52) Predictable Success . Performs detail routing on the clock interface nets • User Interface set_fp_clock_plan_options clock tree synthesis engine report_fp_clock_plan_options planning clock tree synthesis engine compile_fp_clock_plan GUI: Clock Sets options for the clock planning Reports options for the clock Performs clock planning Set Clock Plan Options Compile Clock Plan © 2007 Synopsys. Inc. Defines the input pin of each anchor cell to be a float pin.Clock Planning • Overview Clock planning performs the following tasks: Inserts anchor cells on the plan group input ports. Generates the clock trees inside each plan group. Flow Recommendation On Clock Planning In Place Optimization Clock Planning Proto Route Extraction RC route_fp_proto Report Timing Timing Budget extract_rc report_timing check_fp_timing_environment allocate_fp_budgets optimize_fp_timing set_fp_clock_plan_options anchor_cell Anchor_Cell_Name report_fp_clock_plan_options compile_fp_clock_plan Commit Hierarchy © 2007 Synopsys. (53) (53) Predictable Success . Inc. Inc. check_fp_pin_assignment: reports whether pin assignment has observed pin constraints. • set_fp_pin_constraints: • • © 2007 Synopsys. check_fp_pin_alignment: check pin alignment (provide pin detour report).Pin Assignment • • • Overview Assignment of pins on the soft marco boundaries based on user defined constrains to achieve optimal timing and routablility User Interface set pin constraints (including TDF file) on soft macros analyze_fp_routing: use option “-list_feedthrough_nets” to output feedthrough (FT) nets. use option “-finalize” to finalize FT nets and pins and to cut pins based on Global Routing results. (54) (54) Predictable Success . preroute. © 2007 Synopsys. • push_down_fp_objects: push down objects (cells.Pin Assignment • place_fp_pins place pins of Soft Macros from top level or within block level • commit_fp_plan_groups: Creates Soft Macros and place pins on each Soft Macro • uncommit_fp_soft_macros: converts Soft Macros to plan group. Inc. … ) into Soft Macro • push_up_fp_objects: push up objects from Soft Macro back to plan group. (55) (55) Predictable Success . Inc. (56) (56) Predictable Success .Pin Assignment After placement and optimization: Plangroup Aware Global Route mark_clock_tree set_fp_pin_constraints (on Plan Groups) set_parameter -name readPlanGroup value 1 route_global analyze_fp_routing -finalize Analyze Routing Feedthrough IPO optimize_fp_timing feedthrough_buffering_only extract_rc allocate_fp_budgets commit_fp_plan_groups push_down_power_and_ground_straps Budgeting Commit © 2007 Synopsys. Inc.Timing Budgeting Flow • Overview The objective of this feature is to generate SDC timing constraints for block-level by • Distributing positive and negative slack in the path • Determines input and output delays by analyzing delays of interblock timing arcs • User Interface Run the Tcl Command allocate_fp_budgets or GUI: Timing Allocate Budgets • User Benefit • Early detection of feasibility of top-level timing closure • Good SDC achieves good implementation of blocks © 2007 Synopsys. (57) (57) Predictable Success . Budgeting Based On Crosstalk Effect • Overview Does budgeting using noise-induced delay Timer estimates coupling effect based on congestion map Hierarchical Signal Integrity information will be written out on plangroup pins Store top-level xtalk effect for block implementation • User Interface set enable_hier_si true allocate_fp_budgets Budgeter stores effective aggressor driving strength for input pins and coupling cap across block boundary into block CEL view Store into block MW CEL view Cc1 Cc2 Cc3 D Q Effective driving strength © 2007 Synopsys. Inc. (58) (58) Predictable Success . check_fp_budget_result • Post-Budgeting Analysis: Generate a report containing real and budgeted delays through a hierarchical block • Flop-to-flop paths within blocks are not reported • User Interface Tcl Command: check_fp_budget_result GUI: N/A Must be performed during the same session as allocate_fp_budgets © 2007 Synopsys. (59) (59) Predictable Success . Inc. (60) (60) Predictable Success . © 2007 Synopsys.Timing-Driven Black Box Flow • Overview The objective of this flow is to provide you a virtual flat timing-driven black box flow with • Tcl commands on how to identify black box • A complete virtual flat timing-driven black box flow with steps only for black box flow in different color from the color for steps of traditional virtual flat flow. or Flow can be executed using each individual GUI operation • User Benefit You start the floorplan early without a complete netlist for some modules (implemented as black boxes). Inc. • User Interface Flow can be executed with a script of sequence Tcl commands. Shaping. (61) z (61) Step for Black Box Only Predictable Success . Place Black Box Pins IPO import_fp_black_boxes estimate_fp_black_boxes save_mw_cel -hierarchy set fp_bb_flow true create_qtm_model … save_qtm_model write_qtm_model push_down_fp_objects (push down cell row and P/G on black box) set_fp_pin_constraints (on black box) place_fp_pins (on black box) Plangroup Aware Global Route Analyze Routing Feedthrough IPO Budgeting Commit © 2007 Synopsys. Estimate Size Initialize Floorplan QTM Timing Model Create Plan Group. Inc.Timing-Driven Black Box Flow Summary Read Netlist with Black Box Import Black Box. VF Placement Power Planning Set Black Box Pin Constraints. where feedthroughs may be the best solution (i.Feedthrough Net Support • Overview Starting with 2007. including ILM usage Prior to 2007. ILMs could not have feedthroughs or multiple-port nets.e. feedthroughs are supported throughout the IC Compiler hierarchical flow. for routing through blocks) Applies to both signal and clock nets • Top-level CTS supports the use of clock feedthroughs on ILM blocks © 2007 Synopsys.12.12. Inc. (62) (62) Predictable Success .12 • • User Interface No User Interface change User Benefit Provides consistent support throughout the hierarchical flow. • You had to use the set_fix_multiple_port_nets command before block level synthesis & model creation (FRAM and ILM) • No longer required in 2007. Nested ILM Support • Overview Nested ILMs are fully supported throughout the hierarchical flow from 2007. Inc.12 The feature targets very large designs where multiple levels of abstraction are used Block2 ILM1 Nested ILM • User Interface create_ilm • User Benefit Inner ILMs are transparently absorbed into upper level ILM. (63) Predictable Success © 2007 Synopsys. (63) . so that only the logic involved in the upper level ILM’s timing paths are retained from lower level ILMs This helps to minimize the size of the upper level ILM and keep the overall memory footprint small. Inc. min_rise. max_fall. retains only the most critical paths (i.Compact ILM Support • • Overview Reduces ILM size by including only the timing critical portion of the interface logic For each block-level port. (64) (64) Predictable Success . those related to max_rise.e. min_fall corners) • User Interface Block-level: create_ilm –compact Top-level: create_ilm_models –compact {list of reference blocks} • User Benefit Smaller memory footprint than regular ILMs is possible Results in faster top-level runtime © 2007 Synopsys. CTS Supports ILMs • Overview IC Compiler CTS now supports clocks created inside ILM and those going through ILM It also supports clock exceptions defined on ILM ports and inside ILM User Interface All new features are on by default • • User Benefit Faster runtime and uses less memory Ease of Use in the top level flow © 2007 Synopsys. (65) (65) Predictable Success . Inc. Inc. (66) (66) Predictable Success .CTS Support For ILM CLK Guide buffer Generated clock B Guide Buffer Top-level FFs driven by ILM generated clock A ILM Muxed clock C Top-level FFs driven by ILM muxed clock Top-level FFs driven by CLK • CTS adds guide buffers to ILM clock inputs & outputs • Nets between guide buffers are marked with a ‘dont_buffer_net’ • CTS honors clock definitions and clock exceptions inside ILM and/or on I/O ports of ILM • CTS synthesizes the tree for top-level FFs after ports B and C and driven by CLK © 2007 Synopsys. for handoff to PrimeTime) for hierarchical designs containing ILMs It only takes one command to do this: write_verilog -macro_definition Full_Design. Inc.g.vg CEL views (full block level designs) are written out for all blocks modeled by ILMs © 2007 Synopsys.Writing Out a Full Verilog Netlist • • You can write out a full Verilog netlist (e. (67) (67) Predictable Success . 12 Update Training 1. Inc. 2.12 highlighted in Blue © 2007 Synopsys. Timing/SI MCMM Hierarchical Flow (includes ILM) Low Power DFM & Route Rules User Interface New commands/options added in 2007. 6. 4.IC Compiler 2007. (68) (68) Predictable Success . 5. 3. Inc.12 – Low Power Design Setup Design Setup Floorplanning Floorplanning • Pre CTS Optimization • Simultaneous PNS/PNA • MTCMOS Design Planning & place_opt place_opt clock_opt clock_opt route_opt route_opt Chip Finishing Chip Finishing Exploration • UPF User Interface Enhancement UPF Flat Flow Recommendations In 2007.12 • MV Checker • Adaptive Leakage Optimization (ALO) signoff_opt signoff_opt © 2007 Synopsys.IC Compiler 2007. (69) (69) Predictable Success . By default both these options are false set_power_options –clock_gating true -low_power_placement true Run optimize_pre_cts_power optimize_pre_cts_power or clock_opt –power © 2007 Synopsys. (70) (70) Predictable Success . Inc.Optimize Pre CTS Design For Power • Overview The objective of this feature is to optimize the placed design for power by • Physical optimization of Integrated Clock Gating (ICGs) cells. and • Low power placement • User Interface Set options to enable clock gate optimization and low power placement. with minimal impact to timing and CTS QoR • Significant improvement is seen on designs with large number of clock gates which have small fan out • Power improvement comes with a cost of runtime © 2007 Synopsys. Inc.Optimize Pre CTS Design for Power • User Benefit Improvement in power (average 10%). (71) (71) Predictable Success . CTS is run under the hood during power aware placement By default. only leakage optimization is on by default when – power is used (72) Predictable Success . (72) Using this feature with IC Compiler low power flow IC Compiler pre placement CEL view Set clock options set_clock_tree_options Set clock tree references set_clock_tree_references Set clock tree exceptions set_clock_tree_exceptions set_power_options –clock_gating true –low_power_placement true –leakage true place_opt -power clock_opt -power route_opt -power Set clock options before power aware placement is done.Optimize Pre CTS Design For Power • Flow Recommendations Using this feature with IC Compiler default flow IC Compiler pre placement CEL view Set clock options set_clock_tree_options Set clock tree references set_clock_tree_references Set clock tree exceptions set_clock_tree_exceptions set_power_options –clock_gating true –low_power_placement true –leakage false place_opt clock_opt -power route_opt © 2007 Synopsys. Inc. both clock gate optimization and low power placement are disabled. (73) (73) Predictable Success .Power Network Synthesis.Power Network Analysis © 2007 Synopsys. PNS. PNA. common grounds transition smoothly among voltage areas. Inc. To create common ground over multiple voltage area. User Interface Set four groups of power network synthesis constraints for each voltage set_fp_rail_voltage_area_constraints -voltage_area -nets –layer –global –ring_nets Run synthesize_fp_rail -synthesize_voltage_area -power_budget • User Benefit To generate multiple power networks on different voltage area concurrent to reduce turn around time.Simultaneous PNS/PNA in MVDD Design • • Overview The objective of this feature is to synthesize multiple power networks on multiple voltage areas with user specified P/G constraints at same time. Inc. based on the inserted MTCMOS • User Benefit Insert and place MTCMOS array to explore if whole chip IR drop meets IR drop target with inserted MTCMOS array © 2007 Synopsys.MTCMOS Design Planning • Overview The objective of this feature is to explore MTCMOS planning • User Interface explore_header_footer To explore MTCMOS cell placement and IR drop. (74) (74) Predictable Success . MTCMOS Design Planning MW design lib & floorplan creation voltage area (power domain) creation and planning virtual flat placement create base power mesh power network creation and analysis MTCMOS cell explorer power switch insertion pre route power switch cell power network analysis LS / ISO insertion (recommend done in logic synthesis) placement refine and routeability check) place_opt / clock_opt / route_opt Additional Step © 2007 Synopsys. Inc. (75) explore_header_footer add_header_footer_cell_array connect_virtual_pg_net optimize_header_footer (preroute main and virtual pg net in physical) analyze_fp_rail (75) Predictable Success . com/retrieve/020279.12 User Guide for ICC UPF methodology © 2007 Synopsys.synopsys.html Switch Cell Modeling : https://solvnet.html Level Shifter and Isolation Cell Modeling : https://solvnet.Unified Power Format (UPF) • Overview UPF 1. Inc.com/retrieve/022443.synopsys.0 key commands supported in IC Compiler Binary flow through MW recommended Automatic pg derivation based on UPF power intent Special cells insertion (Isolation Cells.synopsys. Retention Register) must be done in Design Compiler as in non-upf mode • Libraries need to have power and ground (PG) pin definitions Customer Consumable Application Note on Library requirements for PG Pin syntax Modeling : https://solvnet.com/retrieve/020282.com/retrieve/022442.synopsys. (76) (76) Predictable Success .html Retention Cell Modeling: https://solvnet.html Always ON cell Modeling : https://solvnet.html • Please refer to IC Compiler 2007.com/retrieve/020281.synopsys. Inc.User Interface Enhancement For UPF Support •Overview New UPF objects have been added to Milkyway database and User Interface create_power_domain remove_power_domain report_power_domain create_supply_port remove_supply_port report_supply_port set_domain_supply_net create_supply_net connect_supply_net report_supply_net remove_supply_net create_power_switch remove_power_switch report_power_switch © 2007 Synopsys. (77) •User Interface 14 new Tcl User Interface commands are added to IC Compiler to manipulate those new UPF objects •Usage/GUI •New Tcl User Interface commands are: (77) Predictable Success . remove_*. © 2007 Synopsys. A design must be loaded before any of these new commands could be executed successfully Commands need GALAXY-MV feature license. • (i. set_domain_supply_net. Inc. otherwise these new 14 User Interface commands won’t be available. (78) (78) Predictable Success . and connect_supply_net) • Except all of the report_* commands Minimal runtime and memory impact for the new commands.User Interface Enhancement For UPF Support • Flow Recommendations IC Compiler must be in UPF mode.e. create_*. 12 User Guide for Flow Details Highlighted are only applicable to upf_mode © 2007 Synopsys. (79) (79) Predictable Success .UPF: Recommendation In 2007.12 MV Flat Flow (upf_mode) open_mw_cel •VA creation •Switch cell mapping + insertion •Secondary power pin routing •check_physical_design •derive_pg_connection Note: Libraries must have power and ground (PG) Pin Connections check_mv_design Design Planning phase place_opt clock_opt route_opt Chip finishing save_upf Please refer to 2007. Inc. Inc.MV Checker • Overview Existing check_mv_design addresses logical checking only Lack of physical analysis and checking capability for MV designs A debug utility to check the validity of user constraints • Usage /GUI check_physical_design –for_mv © 2007 Synopsys. (80) (80) Predictable Success . MV Checker •User Benefit The report from checking the physical constraints helps debug and guides your error corrections • Report and count of special cells (level shifters. (81) (81) Predictable Success .) in the design • Report of special cells that are fixed placement or in RP blocks • If the voltage area site rows contains the required site-types • Utilization of always-on power wells to determine the size of power wells • If voltage area contains fixed cells located outside • Absence of guard-band • Absence of power domain in association with voltage area © 2007 Synopsys. Inc. isolation cells etc. Inc.Adaptive Leakage Optimization (ALO) • Overview Improves leakage optimization QoR ALO makes place_opt. clock_opt and route_opt leakage aware • Enables optimization to use as many low leakage cells as possible • User Interface Off by default. (82) (82) Predictable Success . set adaptive_leakage_opto true • User Benefit Average 15% lower leakage power than 2007.03 after route_opt Note: Runtime hit of up to 10% is expected for overall flow © 2007 Synopsys. To enable ALO. Inc.db” … set_power_options –leakage true place_opt –power … clock_opt –power … route_opt –power … © 2007 Synopsys. (83) (83) Predictable Success .db lvt. the user interface remains the same set adaptive_leakage_opto true … set target_library “hvt.Adaptive Leakage Optimization (ALO) • Usage /GUI To use the ALO. 12 highlighted in Blue © 2007 Synopsys. 4.12 Update Training 1. 2. 6.IC Compiler 2007. Timing/SI MCMM Hierarchical Flow (Includes ILM) Low Power DFM & Route Rules GUI New commands/options added in 2007. 5. (84) (84) Predictable Success . 3. Inc. IC Compiler 2007.12 – Route Rules Design Setup Design Setup Floorplanning Floorplanning place_opt place_opt clock_opt clock_opt route_opt route_opt •Via Farm Rule •Poly Contact Enclosure •Area Based Antenna Rule •Coaxial Shielding •Via Enclosure •Parallel Length Dot Short Chip Finishing Chip Finishing signoff_opt signoff_opt © 2007 Synopsys. (85) (85) Predictable Success . Inc. Inc. (86) (86) Predictable Success .Via Farm Rule • Overview This is an enhancement for PG Route Via Farm Rule to honor the rule specified in technology file on via farms spacing and maximum number of rows only in the longer direction of wires intersection • User Benefit Design satisfies specified via farm rule on PG wires © 2007 Synopsys. (87) (87) Predictable Success . Inc.Via Farm Rule • Existing via farm rule maxNumRows = 2 viaFarmSpacing = spacing viaFarmSpacing • New via farm rule maxNumRows = 2 viaFarmSpacing = spacing viaFarmLongDirection = 1 viaFarmSpacing © 2007 Synopsys. Via Farm Rule • Usage For existing via farm rule. specify the following in the Contact Code section of the technology file: • maxNumRows = number • viaFarmSpacing = spacing • viaFarmLongDirection = 1 © 2007 Synopsys. specify the following in the ContactCode section of the technology file: • maxNumRows = number • viaFarmSpacing = spacing For the new via farm rule. Inc. (88) (88) Predictable Success . Inc.27 • User Benefit Drouter shifts the via to meet metal enclosure rule if the tech file variables and droute options were defined © 2007 Synopsys.Poly Contact Enclosure • • Overview In 45nm design. poly contact requires different metal enclosure with respect to metal width and projection/parallel length to the adjacent metals User Interface New droute options are added to trigger the metal extension rule set_droute_options set_droute_options –name M1FloatingSpaceForViaOffLimit \ –value 0.08 –name M1FloatingParaLenForViaOffLimit \ –value 0. (89) (89) Predictable Success . (90) (90) Predictable Success . 2) = ( 0.27 This rule is ignored if double contacts with cut spacing < 0.08 and projection/parallel length > 0. 0 ) S is defined in droute option M1FloatingSpaceForViaOffLimit = 0. 0.015. space < 0. Inc.08 P is defined in droute option M1FloatingParaLenForViaOffLimit = 0.21) = ( 2.Poly Contact Enclosure • Usage /GUI Metal enclosure of poly contact =0.015 if width of W1 or W2 >= 0.27 X1/X2: fatWireViaKeepoutEnclosure © 2007 Synopsys.11.11.11 W1 S X1 P W2 X2 DesignRule { layer1 layer2 endOfLineEncTblSize = 2 endOfLineEncSideThreshold fatWireViaKeepoutMinSize fatWireViaKeepoutEnclosure } = “METAL1" = “CO" = (0. • User Interface New Tcl command defines antenna area rule • define_antenna_area_rule -mode <ignore_lower_layers|include_lower_layers|inclu de_all_lower_layers> -max_area max_metal_area [-diode_distance diode_distance] © 2007 Synopsys. With this new enhancement. Inc. router is able to consider antenna by area and insert a diode at a specific distance to gate. (91) (91) Predictable Success . antenna is checked by considering antenna ratio (antenna_area/gate_size).Area Based Antenna Rule • Overview In general. then a diode must be placed within the diode_distance to protect the gate from excessive charges © 2007 Synopsys. Inc. (92) (92) Predictable Success .rule lib_name \ If area of metal3 violates max_area=50.Area Based Antenna Rule • Usage /GUI Metal2 VIA1 Metal1 Gate diode_distance = 200 Metal3 VIA2 Define/report antenna area rules in IC Compiler_shell: define_antenna_area_rule -mode ignore_lower_layers -max_area 50 -diode_distance 200 report_antenna_rules -output dump. (93) (93) Predictable Success . Inc.Area Based Antenna Rule • User Benefit Router detects the area-base-antenna violation and uses metal-splitting (route_search_repair) or insert a diode (insert_diode) to overcome the violation © 2007 Synopsys. The upper or lower shields are placed at one another track • User Interface New options are added to both GUI and Tcl command create_auto_shield • [-coaxial_below] • [-coaxial_above] • User Benefit Coaxial shielded nets can have better noise-resistance © 2007 Synopsys. shielding only takes place on the same layer IC Compiler shields a net with same. (94) (94) Predictable Success . Inc. upper and lower (coaxially) metal layers.Coaxial Shielding • Overview In general. Inc. (95) Top-view Cross-view (95) Predictable Success .Coaxial Shielding • Usage / GUI M3/M5 M2/M4 • Upper and lower shields are placed at one another track Clock net M4 Shielding Net M5 VIA34 M3 Clock Net M4 M3 © 2007 Synopsys. (96) (96) Predictable Success . Inc.Coaxial Shielding • • Flow Recommendations Route specific group of nets first and then do coaxial shielding Known Limitations Long runtime if coaxial shields are created in a complete routed design © 2007 Synopsys. Parallel Length Dot Short • Overview Provides the detection and fixing floating antenna violation with respect to floating metal’s area and parallel distance and spacing to the adjacent metal wire • User Interface report_antenna_ratio to report floating antenna violation • A new droute option is added to setup the detection/fixing mode: set_droute_options –name floatingWireMode –value 1 .. default=0. (97) (97) Predictable Success .2]. 2: fixing based on floating antenna conx only (ignore violations on user routes) © 2007 Synopsys. range [0. stored in cell.. Inc. .. 0: fixing based on antenna conx (if any) . 1: fixing based on floating antenna conx only .. (98) (98) Predictable Success .5 M1FloatingWirePLength3 -value 0.000 set_droute_options -name m1FloatingWireSpacing -value 10 set_droute_options set_droute_options set_droute_options set_droute_options set_droute_options set_droute_options set_droute_options -name -name -name -name -name -name -name ignoreFloatingWireSpacing -value 0 M1FloatingWirePLength1 -value 0. Inc.24 © 2007 Synopsys.6 M1FloatingWirePLMinSpc1 -value 3.Parallel Length Dot Short – User Interface set_droute_options -name m1FloatingWireArea -value 70.0 M1FloatingWirePLMinSpc2 -value 1.5 M1FloatingWirePLMinSpc3 -value 0.0 M1FloatingWirePLength2 -value 0. Parallel Length Dot Short • User Benefit Reports floating antenna violation Fixes floating antenna violation by Search & Repair • Flow Recommendations Set all constraints by drouter variable then fix “dot short” by Search and Repair • Known Limitations Floating antenna does not check on pre routes © 2007 Synopsys, Inc. (99) (99) Predictable Success DRC Rules Support In IC Compiler 2007.12 • For More details on the DRC Support in IC Compiler • 45 nm DRC Support in IC Compiler • • https://solvnet.synopsys.com/retrieve/021298.html • 65 nm DRC Support in IC Compiler https://solvnet.synopsys.com/retrieve/018370.html © 2007 Synopsys, Inc. (100) (100) Predictable Success IC Compiler 2007.12 Update Training 1. 2. 3. 4. 5. 6. Timing/SI MCMM Hierarchical Flow (Includes ILM) Low Power DFM & Route Rules User Interface New commands/options added in 2007.12 highlighted in Blue © 2007 Synopsys, Inc. (101) (101) Predictable Success (102) (102) Predictable Success . Inc.IC Compiler 2007.12 – User Interface Design Setup Design Setup Floorplanning Floorplanning place_opt place_opt clock_opt clock_opt route_opt route_opt • New Highlight tool • Show GUI Dialog •check_library Chip Finishing Chip Finishing signoff_opt signoff_opt © 2007 Synopsys. New Highlight Tool • Highlights Allows highlighting objects w/o making/changing selection Allows highlighting objects with their original object colors Allows highlighting nets of the chosen wire segments Allows query on highlighted objects • Usage Click on the “highlighter” tool icon in the “Mouse Tools” toolbar Check the options in the “Highlight Tool Options” command dialog Check on/off the menu item “Highlight->Highlight Using Object Color” Check on/off the menu item “View->InfoTip © 2007 Synopsys. (103) (103) Predictable Success . Inc. New Highlight Tool Highlight with highlight color © 2007 Synopsys. (104) Highlight with object color (104) Predictable Success . Inc. Inc. (105) (105) Predictable Success .New Highlight Tool © 2007 Synopsys. (106) (106) Predictable Success . Inc.Show GUI Dialog • Show GUI Dialog Or Menu Locations Bring up the corresponding GUI command dialog box of a given Tcl command (without knowing & choosing the menu item) Show the menu locations of a given group of Tcl commands • Usage icc_shell> GUI_show_form route* icc_shell> GUI_show_form place_opt © 2007 Synopsys. Show GUI Dialog © 2007 Synopsys, Inc. (107) (107) Predictable Success New Command Check_library •check_library • • • • command has been implemented in DC-T and IC Compiler in 2007.12 release Recommendation is to use this command before/after you setup your design and make sure the libraries do not have problems You can perform selective checks by setting the options using set_check_library_options If no options are set using set_check_library_options, check_library will perform default checking You can report the options set by set_check_library_options using the command report_check_library_options © 2007 Synopsys, Inc. (108) (108) Predictable Success Types Of Checks Currently Available Number 1 Checks performed ( Logical v/s Physical ) If no options are specified in set_check_library_options, by default, it will check for missing cells and pins and mismatched pins including pg_pin’s in .lib vs. Power and Ground pins in Milkyway Option No Option specified 2 Checks area attribute of cells in logical library vs. actual area by cell PR boundary in physical library -cell_area 3 Checks cell PR boundary and pins in physical library among a class of cells with the same cell_footprint attribute -cell_footprint 4 Checks and reports bus delimiters in logical and physical libraries -bus_delimiter © 2007 Synopsys, Inc. (109) (109) Predictable Success Types of Checks Currently Available Number 1 Checks performed ( Physical Library checks ) Cell view vs. preferred routing direction. rectilinear or rectangular. and coordinates Check and report physical properties (e. earlier FRAM views) reported Missing antenna property for cells and antenna rules in the layers. cell symmetry. pr_boundary. and wire_track) Option -view_comparison 2 -antenna -signal_em -same_name_cell 3 4 -rectilinear_cell 5 -phys_property {place route cell} © 2007 Synopsys. Inc. FRAM view in reference library with missing views and mismatched views (e.g.g. tile pattern. pin types. (110) (110) Predictable Success . Missing signal EM rule Cells with identical names in different reference libraries with names of cells reported Report boundaries for (macro) cells. Inc. (111) (111) Predictable Success . and corner cells) Option -physical_only_cell 7 TF consistency check enhancement between main and reference libraries -tech_consistency 8 technology data quality for a single library (from cmCheckLibrary) -tech 9 DRC checks for library cells (FRAM view) (from cmCheckLibrary) -drc 10 Routeability: physical pin access (pin on tracks) -routeability © 2007 Synopsys. diode cells with antenna props.Types of Checks Currently Available Number 6 Checks performed ( Physical Library Checks ) Report physical only cells (filler cells with and without metal. the reference libraries used in the current design will be checked -logic_library_name {logical_library_names} • Specifies one or more logical library names (filenames) to be checked. If not specified all the cells in the libraries will be checked. If not specified link libraries used in the current design will be checked -cell_list {cell_list} • Specifies a list of cell names that should be checked. Inc. © 2007 Synopsys.check_library •check_library -mw_library_name {phys_library_name_list} -logic_library_name {logical_library_name_list} –cell_list {cell_list} • Where -mw_library_name {phys_library_names} • Specifies Milkyway Reference library names to be checked. If not specified. (112) (112) Predictable Success . (113) (113) Predictable Success .set_check_library_options • You should set_check_library_options before running check_library command if you want to check specific options • If you don’t set any options using set_check_library_options the default behavior is to check for missing cells and pins and mismatched pins • In addition to the options mentioned in the tables there are 4 other options: • set_check_library_options [-physical] [-logic_vs_physical] [-reset] [-all] © 2007 Synopsys. Inc. (114) (114) Predictable Success .Thank You © 2007 Synopsys. Inc. (115) (115) Predictable Success .Appendix • Timing Budgeting Flow • Block Box Flow • Auto Orientation of Relative Placement Blocks • Relative Placement – Keep out GUI support • Relative Placement – size_only flows for clock_opt & place_opt • Scan Wire Length Reduction • Binary Scan DEF flow (Beta) • AHFS User Interface Update © 2007 Synopsys. Inc. floorplan pushdown etc get_cells with black box filters • First level filter "is_logical_black_box==true” Filter out black box before “import_fp_black_boxes” “is_pyhsical_black_box==true” Filter out black box after “import_fp_black_boxes” • Second level filter “black_box_type==Empty“ “black_box_type==Missing” “black_box_type==Tie-Off” “black_box_type==Feedthru” “black_box_type==DF” Example: • [get_cells -hier -filter "is_logical_black_box==true && black_box_type==Empty"] © 2007 Synopsys.Timing-Driven Black Box Flow: Identifying Black Box “import_fp_black_boxes” generates separate cel view for black box modules • Black box cel view is used for shaping. Inc. pin assigment. (116) (116) Predictable Success . Inc.Relative Placement Keep Out GUI Support • • Overview Request from customers to have the relative placement (RP) keepout displayed in GUI layout window Usage/GUI Added under “RP Keepout” in the layout “View Setting” toolbar Displayed in layout window Displayed in relative placement hierarchy view window • User Benefit Enable users to check the quality of keep out creation and placement Enable users to manipulate the RP keepouts during RP placement and optimization via GUI © 2007 Synopsys. (117) (117) Predictable Success . Relative Placement Keep Out GUI Support • Layout window: Three keepouts placed inside a RP group Use these arrows to browse the three RP keepouts © 2007 Synopsys. (118) (118) Predictable Success . Inc. (119) (119) Predictable Success . Inc.Relative Placement Keep Out GUI Support • Relative placement hierarchy view window: Two keepouts placed in the RP group Oprnd_B_reg Keepout placed at column0 row3 Keepout placed next to RP cell at column0 row1 © 2007 Synopsys. RP columns are always placed from left to right (i.Auto-Orientation of RP Blocks • Overview To enable the coarse placer to have more control to orient the relative placement groups according to data flow Before 2007. RP group orientation = FN) • Result in shorter wire length if data flow is from right to left By default. (120) (120) Predictable Success . orientation is automatically selected to minimize wire length © 2007 Synopsys.12.e. RP group orientation = N) • This may result in longer wire length if data flow is from right to left In 2007.12. RP columns can be placed starting from the last column to the first (i.e. Inc. Auto-Orientation of Relative Placement Blocks RP group orientations versus data flow set_rp_group_options[all_rp_g roups] –orient N set_rp_group_options [all_rp_groups] –orient FN © 2007 Synopsys. Inc. (121) (121) Predictable Success . Auto-Orientation of Relative Placement Blocks • User Benefit QoR changes with data flow • Left to right: no change • Right to left: 5% better Runtime impact is within 1% © 2007 Synopsys. (122) (122) Predictable Success . Inc. Inc. (123) (123) Predictable Success . route_opt • Overview Current implementation in the RP flow to preserve the RP structures • Fixes the RP cells in clock_opt and route_opt • Restricts optimizer from further optimizing the design This feature enables sizing after place_opt in addition to the fixed_placement option • Changes to set_rp_group_options and create_rp_group commands • Added size_only for -cts_option • Added in_place_size_only for -route_opt_option • User Benefit QoR improvement expected within 5% with a 1% runtime/memory hit © 2007 Synopsys.Size-Only Flows For clock_opt. Inc.tcl # create RP groups and constraints for placement & synthesis source rp. (124) (124) Predictable Success .tcl # avoid RP cells being removed during place_opt by set_size_only set_size_only [rp_group_references -leaf] place_opt # check if there is any RP violation check_rp_groups -all # allow size_only in clock_opt set_rp_group_options [all_rp_groups] -cts_option size_only clock_opt check_rp_group –all # check RP placement result in GUI GUI_start © 2007 Synopsys.Size-Only Flows For clock_opt. route_opt • Sample script for size_only in clock_opt source setup. # create RP groups source rp. route_opt • Sample script for in_place_size_only in route_opt # set up design ..tcl # avoid RP cells being removed during place_opt set_size_only [rp_group_references -leaf] place_opt set_rp_group_options [all_rp_groups] \ # allow size_only in clock_opt and in_place_size_only for route_opt cts_option size_only \ -route_opt_option in_place_size_only clock_opt check_rp_group -all route_opt check_rp_group -all © 2007 Synopsys..Size-Only Flows For clock_opt. Inc. (125) (125) Predictable Success . Inc. route_opt • Known Limitation size_only for -cts_option of set_rp_group_options and create_rp_group commands applies only to clock_opt core command but not to atomic commands • optimize_clock_tree • compile_clock_tree © 2007 Synopsys. (126) (126) Predictable Success .Size-Only Flows For clock_opt. No reordering done if repartitioning + reordering has wire length increase. • User Interface No user interface or flow change. Customers had to manually remove PARTITION labels to accomplish this previously.12. In 2007. Inc. optimize_dft (in place_opt flow) will now attempt reordering alone if repartitioning + reordering does not produce scan wire length reduction. (127) (127) Predictable Success . This is no longer required © 2007 Synopsys. Feature enabled by default • User Benefit Automatically obtains scan wire length reduction on designs which previously did not have any reduction.Scan Wire Length Reduction • Overview Some design types cause the current scan chain repartitioning algorithm to have scan wire length increase. 12 –SP1 (128) 2007. (128) MCMM CTS and post CTS optimization TTR + QOR RM Placement and Placement based optimization 2007.IC Compiler-RM Roadmap Update Hierarchical Design Planning Flat Design Planning Floorplan Exploration Routing and post route optimization including SI Chipfinishing Cell/metal filler.12 –SP2 Predictable Success Multi-voltage + MTCMOS UPF Based Multivoltage + MTCMOS . antenna. Inc.12 © 2007 Synopsys. CAA Signoff driven closure with Star-RCXT/PrimeTime SI 2007. (129) (129) Predictable Success . Inc.Thank You © 2007 Synopsys.