748IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 5, OCTOBER 1987 Static-Noise EVERT SEEVINCK, Margin Analysis SRAM Cells J. LIST, AND JAN of MOS LOHSTROH, MEMBER, IEEE SENIOR MEMBER, IEEE, FRANS ,4bsfrad —The stability of both resistor-load (R-load) and full-(2MOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device useful tion the parameters in predicting and supply voltage are derived. The expressions SNM It are tbe effect of parameter changes on the stability as well simulawith CMOS process. reduced cell [8]. Cell-area usually However, in future reductions of 30-50 percent have been obtained, at the expense of a more complex will be significantly processes requiring memory this area advantage scaled-down as in optimizing method results the design of SRAM by the analytic cells. An easy-to-use SNM expressions. is presented, predicted the results of which are iir good agreement supply voltage reduction to avoid hot-carrier degradation. The reason is that the SNM for R-load cells becomes much lower cient larger. order than noise for 6T cells at low supply margin the R-load voltage. then For suffiIn cells cell must the SNM be made is further concluded that full-CMOS cells are much more stable than R-load cells at a low supply voltage. This means that 6T cells have greater potential. to explain these statements of SRAM in this paper. I. INTRODUCTION is studied cell design: the a graphical in Section simulation a Section firming In Section II the cell stability cell area and the stability of the cell. The cell area determines about two-thirds of the total chip area. The cell stability determines the soft-error rate and the sensitivity of the memory to process tolerances and operating conditions. The two aspects are interdependent cell for improved area. There has been considerable years to understand yet cells. The basic cross-coupled appearance, attempts effort over the past several of flip-flop simple in the cell Fig. R-load a read power situation l(a) and (b) shows the II. SRAM-CELL is discussed with the aid of Analytical expresand 6T cells are derived easy-to-use in results thus conis developed T WO aspects are important for SRAM representation of the SNM. sions for the SNM method IV. of both R-load for SNM 111 and Appendices In Section Good A and B. An investigation since designing V analytic and simulation stability invariably requires a larger cell are compared. are presented agreement is demonstrated, of the analytic the validity results. The conclusions in Section VI. and model the stability cell is deceptively model STABILITY to analytically stability have achieved only limited success [1]. Much of the published work has been concerned with the statistical and dynamic metastable properties [1]–[3]. of flip-flop The stability synchronizers in the region as expressed by the circuit lines fact diagrams precharged the most of the cell and the 6T full-CMOS access and with supply voltage. because the bit This is in cell, respectively, during to the critical which com- static-noise margin (SNM) [4] has also been investigated f& both resistor-load [5], [6] and full-CMOS [7] SRAM cells. puter This both view, The cells However, these studies have been limited to comsimulations; analytic work has not yet been reported. paper is concerned with the SNM of SRAM cells from an analytic as well as a simulation point of in the context of submicrometer MOS technology. results are useful in optimizing the design of SRAM as well as in predicting the effect of parameter (R-load) compared cells are widely SRAMS used in NMOS(6T) full- the resistor or p-channel load elements are now shunted by the n-channel access transistors, reduces the gain of the cell inverters. Both prised cell types can be represented of two inverters as shown by a flip-flop in Fig. 2. The voltage sources V. are static-noise sources. Static noise is dc disturbance such as offsets and mismatches due to processing and variations in operating conditions. The SNM of the flip-flop is defined as the maximum value of V. that can be tolerated by the flip-flop before changing states [4]. In this paper, only static-noise sources are taken into account. A SRAM cell should be designed such that under all conditions some SNM is reserved to cope with dynamic disturbances caused by a particles, crosstalk, voltage supply ripple, and thermal noise. A basic understanding of the SNM is obtained by drawing and mirroring the inverter characteristics and finding the maximum possible square between them. This 01987 IEEE changes on the SNM. Resistor-load and CMOScell area when (mixed-MOS) owing to their smaller to the six-transistor Manuscript received April 2, 1987: revised June 4, 1987, The authors are with Philips Research Laboratories, 5600 .JA Eindhoven, The Netherlands. IEEE Log Number 8716261. 0018-9200/87/1000-0748$01.00 we assume the right sides to be at level ZERO and the left sides at level ONE. and (b) 6T full +m Vn re&dMa&ccss: (a) R-1oad. we assume Ql. [9]. 2. In Fig.5 for the R-load cell.. sharply as soon as the subthreshold begins dropping current is able to .: STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS 749 l’~~ develop 10 Gfl clamped reduced a noticeable in our voltage drop across the resistor (about the output voltage is further with transistor is in the R-load resistor and role. In. For the cells of Fig.SEEVINCK et d.. however. to B. 3 we see that the R-load inverter it characteris- k(r+l) tic starts at V~~ when Vi. Assumptions The. QI and Qd are assumed saturated while Q ~ and Q5 are in the linear region. ..!J . The currents. These assumptions were verified by simulation as well as by back substitution. . the SNM data before the 6T cell for both cases.Cc. ‘\ ‘‘. Subsequently by the access transistor and drops slope for VI. in spite of the larger value of r for the will likewise does. In decrease cell will the VD~ is decreased. its it is clear that the R-load addition. A. SRAM cells durink R-load cell can only be used with a l’~~ somewhat larger than 2V~ (say 3 V in the case of VT= 1 V) during access to avoid write-time problems.9 V. dimensions SNMR=~VT+r+l-r~: r+i(VDD-VT) (1) 2r+l VDD – — r+l 1[ ~+ r we assume V~~ = 5 V. 1. Curves II have been mirrored with respect to a line passing through the origin at 450 from the horizontal reduction and velocity are presented in Appendices are given below: A and B.\ ing. [5]. (:) Fig. of which is a graphical technique of estimating the SNM [4].. = VT – — ( k+l of ~driv. SNM Kirchhoff ANALYTICAL lIERIVATION OF SNM I and AnaZytic Expressions can be found analytically by solving the equations and applying one of the mathemati- 11 ‘ vn - Fig. This means that the cell circuit diagrams components can be reduced shown dotted to those shown only negligible in Fig. Fig. ‘. factor For for the purpose a square of illustraall are = 2. Explicit expressions for the SNM of the R-load cell dnd the 6T cell were obtained by using the basic MOS model I 3 2 ‘“q. 4(b)./finP voltages in Fig. r is equal to 2 for the 6T cell and 3. or at most to conduct I— --f ul~-CMOS R -load $~ 4(a). and transistor 1. 4. is an important cell parameter called the “cell ratio” r. 1 h ---------- -. that case). = O V. in Fig. 3. In this case.3 (/30 indicates transistor). Note that the cell noise margin in the area where do not play the maximum the load any access turned case is situated subthreshold When SNMc~ R-load When lose I JI current significant it is clear comparing > SNM~. squares.! II >. are assumed to be nonconduct- 5 . . It is illustrated with constant subthreshold tion. . Q3. III. Static-noise voltage cally equivalent noise margin criteria [4]. (equal for n- Vou+ ’11’ [v] and p-channel) and neglecting second-order effects such as The detailed Fig. 3. cell. ~n. The ratio SNM6. A flip-flop comprised of two inverters. I 0123L5 V/~’ resp. 1. sources V. >1 V when the driver on. J equations mobility derivations the results with constant threshold voltages saturation. and Qq operate in the saturation region and Q ~ in the linear region. It determines the cell size as well as the cell stability. the transconductance threshold as shown 1 VT are 0. are included. From Fig.. GraphicaJ representation of SNh4. using the most basic MOS model threshold voltage and a simple exponential current model. e. respectively. VT. local linearity its operat~ that the A simulation in curve of inverter Qz is in the linear See. around both 3/8. assuming Q2 /Q4 region.. A and easy to use was developed R-load and 6T cells depends only on threshold voltage. 7. in Fig. and not on the absolute value of the @‘s. This be is ilr =1.. u) system. 3. only i. y = Fl(x ) and the (x. for the R-load with decreasing V~~. SNM method Section II ple. on the other hand. SIMULATION based on METHOD the here. in either on with proper q = This is due to the coeffir or q cients of V~~ in (2) having opposite where r = ratio= ~d/~a voltage then result of behavior through dence stability obtained lustrated q = BP/B. 5 shows a stylized version of Fig. squares” in a 450 rotated (b) Fig. the full-CMOS curve I in Fig. In the (u. a particular respect choice to varying of r and V~~ can q. I 1 Y ‘Qw)c. On the other cell the SNM will always decrease as can be seen in Fig. coordinates The (u. Changing will be independent will V~~ variations. VT= threshold SNM6T a positive or a negative depenrequired V~~. 4. o x -?1 I . SNMCT will will increase with that the SNM decrease with temperais SNM ~ and VT. accessed. This choice 1s. and proper choice of W/L ratios. and we have already concluded that the SNM independent of the absolute value of the ~ ‘s. It follows temperature since VT decreases with The proximations approximation of the transfer ing point bottom were needed. for particular of values of r and q. VOL. (a). we can draw some the SNM for both diagonals method conclusions.. with Third. which is a measure of the diagonal’s length. graphical To technique B. q = 3/8 and r =2. and /3 ratios. Conclusions from Analytic When interesting studying general the SNM described is presented estimate values. Fig. SNM estimation based on “maximum coordinate system. that the normal by of curve xt represent and mirrored the required charactery = inverter are defined FI the functions of u and into u. 3.a. a procedure which is needed that finds values SNM for the for of the maximum is quick squares as shown in Fig.= ‘R R . o) system. al Fig 1 5. the increased /3 values associated with subrnicrometer processes will not by themselves lead to improved cell stability.zr. The maximum maximum Assume istics l?~(x). It is apparent part is approximately Results expressions First. r = B~/~a must be maximized and also (in the case of 6T cells) q/r= fp/D~ by appropriate course.= ~=~– J-() r+l derivation where right-hand VDD – v. SC-22. hand. Thus. Second. To find must and minimum squares. of (1) was exact. (b) Circuit diagrams of SRAM cells when static-noise sources V. Finally. linear. subtraction of the u values of normal and mirrored inverter characteristics at given u yields curve A.750 IEEE JOURNAL OF SOLID-STATE CIRCUITS. SNM6T signs. y) where the latter is the mirrored in terms be first transformed the version of y = F2(x). OCTOBER 1987 ‘DO I 1 . of small cell area use together with a standard dc circuit simulator [7]. SNM R already becomes zero for r =1. 3 in two coordinate systems which are rotated 450 relative to each other. V~~. no simplifying apone increasing increasing In the case of (2). NO. . Therefore. for examIV. SNMG~ remains larger than zero for all values of r > O. 5. was required. ture. of constrained cell-write by the requirements operation. To design the cells for maximum SNM. both SNM~ and SNM6T increase with r. inserted. 8 where two cases are shown with v. extended model z W o simp~e model 751 Loo X theory @q.: z 300 -- 7 4’ extended o simple model model required transformation is supply voltage VDD [“1 (3a) Fig. ‘— (5) V. 7–10.9 V and q = 3/8. as predicted by (1) and (2).: STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS F] E . The V2 in of (4) and (b). (3b) Substitution of (3) in y = Fl(. UI – V2. The absolute values of the maximum and minimum are the values of the diagonals of the maximum squares.5 f % = 100 q’————y————— -% 3L5 supp[y voltage ‘DD ‘v] 7. Solutions can be found with a standard dc circuit simulator by translating the equations into circuits. For the simulations. a fully extended model with submicrometer transistor parameters (which includes subthreshold conduction. 8 and 10) show a good correspondence between (2) and the simulations for both transistor models. Circuit implementations of (a) (4) and (b) (5).(1) x xx b r= 3. and mobility reduction) were used. ok. b(a) In Figs. and then it is transformed to the is SubFig. the SNMS for the R-load and 6T cells. and (5) are respectively.x) gives ‘=u+fiF(++a (u. body effect. SNM of R-load cell versus supply voltage. r ~ . ratio . Note that the SNM is . using voltage-dependent as shown represented The in Fig.. SNM of full-CMOS cell versus supply voltage. = -1 ? 500 . u) system.= : 300 m . by U1 and voltage sources in a feedback loop solutions Fk. 6. ANALYTIC AND SIMULATION RESUI. SNM of R-load cell versus Fd/& atio v=–u+fiFz ( 1 U~— V . y) system with respect to the u axis. 9. The curves obtained for the 6T cell (Figs. is calculated by the simulator and is represented by curve A in Fig.SEEVINCK et U[.: “ 200 F. Fig. The plots extend down to V~~ = 3 V which is the approximate limit of validity of the analytic models. are plotted as a function of V~~ and r for VT = 0. difference between the two solutions. first Fz is mirrored in the (x. 5.TS 0. 8. . both the most basic MOS model and 6. In the figures the analytically predicted SNM is compared with simulations which were performed according to the method outlined in Section IV. Multiplying the smaller of the two by l/fi yields the SNM of the flip-flop. — > = ~ 600 1 x I 1-1= (b) 1 I “ Fig. They give u as an implicit function of u. 1 Equations (4) and (5) represent the inverters comprising the SRAM flip-flop cell. (4) For F. ‘: c . now stituting The required coordinate transformation the same as (3) but with in y = Fz (x ) gives x and y exchanged. real has SNM transistors been values in to shown velocity causes that deviation. and Qd are saturated. As discussed before. However. this behavior is predicted by (2).P(VGS–VT)2 1 v~~ – VT – ~ ( ‘DS ) (Al) simulation ~~ = ~V~~ in the “saturated” (A2) First that this is caused by velocity the simple model. This reduces the influence of the high bit-line level on the low level in the cell. dent must is then J. expressions (VDD ‘D. 4(a)). VOL. cells at low have supply the avoid will full-CMOS cells better than R-load memory to ~ o voltages. currents appropriate cells to achieve similar voltage. 7 and 9) show a complete fit between (1) and simulations with the simple model. Substituting VI. This makes the R-load cell much more sensitive to ac disturbances and a particles. these into (A3) and (A4) yields +vDs2–vT) VDD – VGS2–vn–vT=J(vn of R-load The and full- (AS) for the SNM SRAM cells have been derived. (A5) (A6) (A7) switched off.~ ‘. the which simulation SNM in it is quick results agreement R-load some . SC-22. The loop r <1 the flip-flop until be larger equal to r.s72 . exfended model Therefore. the impedances in the K--load case are much higher compared to the full-CMOS case. 1 (A9) .7. apparently increasing the SNM. For APPENDIX DERIVATION OF SNM the smaller ratios the SNM increases with decreasing V~~ in contrast to the behavior with larger ratios.v. simple model eq (2) supply hot-carrier suffer cells. follows that The voltage for gain of each inverter gain is therefore loop r >1. For indepenand we the cell will It follows Q2 in equating Q2 and be in a metastable unbalance must linear drain the region. ratio. a significant R-load to SNM by disadvantage to maintain the to compared reasonable area required of full-CMOS In order supply close to at cells a SNM of full-CMOS cell versus /3d/~< voltage. we see that for decreasing v ~~. vGS3 –vT=lF(vGsl-vT) (V. this effect is compensated for by the mobility reduction of Q5 and the drain feedback effects of QI and Q4. This velocity tion effect reduces the effective ~ of the access transistor Q4 for large V~~ (see Fig. 3 V or less when to cells full-CMOS values R-load cells. In and are addition. much of SRAM cells. with from This is expected the extended since the derivation is observed Further saturation model. cells begins disappearing.= T = = VI x 800 700 600 500 Loo 300 12345 ratio r design method The analytic saturation Further. for the and SNMG~ are about These values are much respectively.SA .2 . with cell. than the values obtained in the read-access case to the low-impedance access transistor loads being V&l = Vn + VDS2 ‘GS3 = VDD – VGS2 – V. of (1) for the which saturawas exact. As a general observation. voltage has future be processes. reduced will be reduced conventional x theory: degradation. Clearly.752 IEEE JOURNAL OF SOLID-STATE CIRCUITS. we must know the operating conditions of the transistors (whether “saturated” or “linear”). Analytic CMOS expressions CONCLUSIONS v G~4= VDD – VDS2. 1. So far the noise-margin comparison has been done for the read-access situation.‘T)2= 2rv&2 - are useful in predicting the effect of parameters and operating conditions on the SNM as well as in optimizing the ( ‘.s2 -‘T .5 . for reduced of R-load cells over and “linear” regions.)’= Now we write 2rV~s’ ( the Kirchhoff voltage equations: J’&z -VT -~ v~sz 1 (A3) . Ql. easy in For to use good the an has SNM been simulation developed. simulation has shown was omitted a slope difference We models A CELL 4(a). 5. OCTOBER 1987 . The curves obtained for the R-load cell (Figs. the area advantage bigger ratio than 6T Hence. When those of that r the Q4. wish we to will analyze use are circuit ID= . For example. of Q1 and Q3 we and find using models. for where r = /3~/f?a. NO. (A4) shown in Fig. When the SRAM is in the retention-mode (switched-off access transistors and V~~ = 2 V) the differences by simulation parameters 600 better owing and between SNM ~ and SNMe~ are observed to be much less. Suppose Qz is also saturated. It gain of take is insufficient operation condition than unity [4]. or equal that approximately constant with V~~ for a ratio r =1. Q3. SNM~ 800 mV. The MOS FOR R-LOAD of Fig. 4(b). predictions. full-CMOS V. and will the Qz enters the linear region. However. In the case of the 6T cell of Fig. R-load supply cells need a significantly noise margins. respectively. +r(fi-l)VT -r(fi+l)V. as before.. + VGS2) (B7) (B8) (~ (A15) with When next combining find the minimum valid: 2r4~ = .. 11. The linear approximation is defined by the value of VDs2 and its slope at point is derived from (B8) by sulmtitUt@ (denoted by – k) is determined p. where the threshold (Bl) b2 = 4ac or b=–2G since b <0. which is the approximate operating point when marginal noise is applied. together with a straight-line approximation through point P at V~s2 = V. r = Bd/ba. V&z or V~s2 from approximation these two equations to be to a lower a fourth-degree A simplifying equation which is too complex leading (A14) and (A15) and simplifying we is Eliminating yields useful.VT- ~vDS2 1 V. V. = V~~ – VT. We can choose from stability criteria [4].(L)::::%.VT)2 = zrv~s.. In Fig. yields ( ‘&2 of -V. which (Al) of the result.s~– v. For this case it is roots [4]. these into (Bl) -V. APPENDIX DERIVATION OF SNM -B reduces tO that (A13) the transfer characteristic of the inverter which is ON has a fairly constant slope around its operating point. - Vn ‘2vDs. = ) ( (VGS.. the -: p- VirS2 and are ) (Bz) voltages n-channel devices are assumed equal and The required Kirchhoff q = &/Ba. These assumptions were checked by simulation and back The required linear (see also Fig. } 1 (All) Linearizing the transfer characteristic around its operating point of the Q2 /Q4 P. ‘Dsz at Point ‘&2 = V. 4(b) we assume QI and Q4 to be saturated and Q2 and Q5 to operate in the linear region.7 V for r =1. the SNM: Substituting (All) and solving for (A12) V. supply voltage for which this analysis degree is therefore In Section III-A needed.)2=f(VDD (B6) require and (B2) yields -Vn-VGS2) VT– Vn .. For requires of coinciding root. V&’.VDS2)2 = zrV~s2 ( VGS2. 11 this part of the characteristic is shown.s.: STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS 753 Eliminating V&2 from (A8) and (A9) and simplifying results in a quadratic equation (A1O) av&2+ bvDs2 C= o + with a=l+r+2r3/2 b=–2{~(r+l) ~=vz s “. (A14) the When solving for VDsz from (A1O) and (All) under condition (A12) and substituting (A13). – . results in 2q Equating the drain using currents the models of QI and Q5 and those of Q. when VT= 0. and and (A2). this means VDS2 > we determine is valid. L----LJ o v~ ‘DD ‘GS2 — Fig.. we find . v. 3 that vDD min VT. inverter substitution where V.5 and 2. voltage equations V&l = V. . Together in strong v Gs~ = VDD – VDS2. FOR FuLL-CMOS CELL (B8) with respect to V&2 and then evaluating approximation For the circuit of Fig.e.(K -~.9 V t~s expression 3. It follows is valid for VDD down to about 3 V. we QI the range and of V~~ for wfich with this (A5) Substituting (VDS2+K Qg have to operate VGS1 > VT. The P SIOPe by first is then differentiating at ‘GS2 = V. = VD~ – VT. and Q. ) (A16) { 1+ (r+l)J~–r3/2–l For example. We now find marginal stability several easiest equivalent the SNM by applying a condition for to (A1O) and (All). we noted in connection with Fig.SEEVINCK et al. i. to use the condition (A1O) this means a double (V&. + V&’z v Ds~ = VDD – Vn – (B3) VGS2 (B4) (B5) v ~-5 = VDD – Vn – VDS2 and Next analysis inversion. 11) expressed as v~S2 = V(O kV&2 – (B9) .– VT)2 .2 V for r = 3. “ Design considerations of a static memory cell. pp. J. receiving the B. The Netherlands. E. vol. The Netherlands. Solid-State Circuits. Apr. Pretoria. with a dissertation on integrated Schottky logic (ISL). Uniu . From 1975 to 1981 he was employed at the Council for Scientific and Industrial Research (CSIR) in Pretoria. Ohzone. Currently he is working on a l-Mbit SRAM design. returning to Philips and working on analog IC design. pp. “ The static noise margin of SRAM cells. pp. pp 414-418. Nakano.” Microelectron. So[id-State Circuits. (Auburn. degree in electronic engineering from the Technicaf University of Eindhoven. June 1985. Eindhoven. - L tran. Syrnp. Jan Lohstroh .” IEEE J. SC. where he joined with Philips Gloeilampenfabrieken in Netherlands. Shinohara. +~A2=0 q (B13) From 1970 to 1972 he was Nijmegen and Eindhoven. and J. The Netherlands). “Analysls of metastable operation in T. 1980. F. and application of punch through devices. Solid-State Circuits. where he performed research and development on novel circuit techniques and custom IC’S.D.liqear . 803–807. Aug. Dec. de Groot. we have defined x= VDD Vn vG~2 – – A= As in Appendix criterion solve for V. SC-22. A. Y. After simplifying. and thin polycrystalline-silicon high-vafue M. 12 L and ISL logic. In 1970 he joined the Philips Research Laboratories. He was educated in South Africa. Lohstroh became a member of the European Program Committee of the ISSCC in 1983. F. 1968. modeling. VOL. in 1984. to (B13). no. on April 15./Govt. REFEREFJCES [1] R. Delft. Electron Devices. M. and G. pp. . SC-15. no. SC-20. M. From 1985 to 1987 he was Department Head of the Philips Advanced Memory Design Centre. J. (B12) l+r+r/k V~~z from Next we eliminate we obtain (B7) and (B9). South Africa. Dr. In 1983 he became Department Head of the research group for Digital Circuitry and Memories in the Philips Research Laboratories. Jaeger and R. SC. B. 169-176. continuing IC where. Since 1987 he has been Head of the Centraf Application Laboratory of the Philips Component Division Elcoma in Eindhoven. vol. Feb. fxndhoven. 183-187. Solid-State Circuits. [2] [3] [4] [5] [6] [7] C. + = ( l+r y. on July 11. He received the M. ESSCIRC (Delft. no. 1. pp. we now apply the double-root Next the stability application work. He received the Ph. G. Seevinck. SC. Hirata. Papers. 1986.” in Dig. 5. The Netherlands. V(O kv. degree in electronic engineering (cum laude) in 1975. vol. vol. Odanaka. SC. and telecommunication applications of VLSI. His current interest is in consumer. pp. “Phase plane analysis of the upset characteristics of CMOS RAM cells. 1985.” IEEE J. In this area he worked on device concepts. 4. K. 1983. ‘l’he Netherlands. Initially he worked on integrated magnetic memories and silicon imaging devices for optical memories. where he worked on development and design of memories. SC-22. where he is now performing circuit research.” IEEE Trans. Sept. degree in mathematics and physics in 1966. 2? pp. The Netherlands. .ffops. . 1. In 1981 he remigrated to The Netherhmds. vol. Tech. q 1 V. 6. obtain we substitute SNM: (B14). 383-390. “ Noise margin and noise immunity in logic circuits. and the D. Eindhoven. Schuster. the B. Anami. Lohstroh.” IEEE J.” IEEE J. “The behavior of flip-flops used as synchronizers and prediction of their failure rate. Chappell. . The Netherlands. degree in electrical engineering in 1970. In October 1985 he returned to Philips Research Laboratories. 1. Apr. 1987. SC.” in Proc. He maintains a uart-time professorship at the University of Twente. He received the Ingenieur degree from Twente University. S. OCTOBER 1987 with [8] ~=~– -J() r+l and VT (B1O) [9] T. ED-32. S. and A. 1983.. Sept. Feb. Hill. . NO. no. M. List. Hens. The Netherlands. The design and application of analog to South Africa. In August 1983 he became Professor of Electrical Engineering at the University of Twente. The Netherlands. Then he was involved with bipolar logic circuitry and memories. SC-18. industrial. He has coauthored over 30 papers and holds severaf patents in the area of microelectronics. 16–18. pp. . 16-21. H. no. 9.” IEEE J. List was born in Hong Kong in 1958. where he worked on the integrated circuits. (M’79) was born in Den Haag. ECL memories. “ Stability and SER analysis of static RAM cells. AL). degree in applied physics from the Technical University of Delft. the B. 1945. Fox. in 1981. Shinohara. “Worst-case static noise margin criteria for logic clrcuils and their mathematical equivalence. E. integrated circuits. Kacprzak RS CMOS flip./Industry Microeiectron. . Alblcki. 57–64.. “Ion-implanted resistors for high-density poly-load static RAM applications. The Netherlands. and finally Frans J. 1749-1756. Fuse. and noise-margin analysis of digital circuits. Since then he has been with the Philips Research Laboratones. Since 1985 he has been chairman of this committee. Veendrick. vol. M. His dissertation dealt with the anafysis and synthesis of X2 ( l+2k+Lk2 ‘7 H +2X 1kz4+A+V~-V. for simplicity. Enschede. vol. degree in electronic engineering in 1981. and T. in 1970. J. SC-18. .754 IEEE JOURNAL OF SOLID-STATE CIRCUITS. Solid-State Circuirs. to VO+(k+l)Vn–kV~~– }“ (B14) A. In 1973 he returned Philips in Johannesburg. 1946. S. Eindhoven. Sasago. all from the University of Pretoria. 1985. C. Fukumoto. Evert Seevinck (M75–SM85) was born in Doetinchem. no. Sai-Hafasz. The Netherlands. H. Yoshimoto.
Report "1987 Static-Noise Margin Analysis of MOS SRAM Cells"